CN217607826U - Ethernet interface circuit - Google Patents
Ethernet interface circuit Download PDFInfo
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- CN217607826U CN217607826U CN202221580495.6U CN202221580495U CN217607826U CN 217607826 U CN217607826 U CN 217607826U CN 202221580495 U CN202221580495 U CN 202221580495U CN 217607826 U CN217607826 U CN 217607826U
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Abstract
The application is applicable to the technical field of Ethernet and provides an Ethernet interface circuit which comprises a transceiving control circuit, a network socket circuit, a direct-current power supply and an anti-interference module; the receiving and transmitting control circuit is used for controlling data transmission between the equipment and an external network; the network socket circuit is used for connecting an external network circuit; the direct current power supply is used for supplying power to the receiving and transmitting control circuit and the network socket circuit; the receiving and transmitting control circuit is electrically connected with the network socket circuit; the anti-interference module is used for eliminating circuit interference generated by the transceiving control circuit, the network socket circuit and the direct-current power supply; the receiving and sending control circuit and the network socket circuit are also respectively electrically connected with the anti-interference module, and the anti-interference module is also electrically connected with the direct-current power supply. The anti-interference circuit is introduced into the power input end of the direct-current power supply, the power input pin and the center tap of the voltage conversion module, so that the influence of instability of the direct-current power supply or external electromagnetic interference on the interface circuit is filtered, and the stability of network transmission is ensured.
Description
Technical Field
The application belongs to the field of Ethernet interfaces, and particularly relates to an Ethernet interface circuit.
Background
Since the advent of ethernet in 1975, the field of communications has been rapidly developed, however, in the twenty-first century, ethernet has not only been suitable for use in business and industry, but has even gradually advanced to military applications, with the trend of necessity through various parts of the ethernet control system.
In the current industrial control, the data and instruction communication between the control equipment and the upper computer is realized by means of an ethernet (internet), which is the most important communication mode at present. In the network communication connection technology, the transmission distance of the ethernet interface as the network transmission exceeds one hundred meters.
Common Ethernet interfaces are 10/100Base-TX, 10/100Base-2 and 10/100Base-5, and Ethernet interfaces are usually wired indoors, but in some residential districts with poor environment, towns and rural places, due to the limited number of points at the entrance of broadband network resources, the installation size of the Ethernet lines is usually larger than 50 meters, and in extreme cases, ethernet interface connection cables of some devices may be wired outdoors. Therefore, in practical use, the interface circuit is easily impacted by the electromagnetic pulse, so as to damage the ethernet interface circuit, and further cause unstable signal transmission of the ethernet interface circuit.
In an LED projection device, an LED film screen may be formed by splicing a plurality of LED display screens into a whole screen. Because movie screens are generally of a larger size, there are a greater number of LED display screens used for tiling, and in some cases, the number of LED display screens that may be required for a single LED movie screen may reach around one hundred. The LED screens may receive or transmit video data through network cables, and may also communicate with the control device through the network cables, so that it is necessary to ensure that data transmission of the LED screens is interfered as little as possible.
Therefore, in order to ensure safe and reliable operation of the network device, interference prevention processing needs to be performed on the ethernet interface circuit.
However, the existing ethernet interface circuit is not ideal in anti-interference and is easily affected by external interference signals during power supply transmission to the interface circuit.
Disclosure of Invention
In the prior art, an ethernet interface circuit is easily affected by external interference, resulting in unstable signal transmission.
In order to solve the problems, an anti-interference circuit is introduced into a power input end of a direct-current power supply, a power input pin of a transceiving control circuit and a voltage conversion module center tap of a network socket circuit, so that the influence of instability of the direct-current power supply or external electromagnetic interference on the interface circuit is filtered, and the stability of network transmission is ensured.
An ethernet interface circuit comprising:
a transmit-receive control circuit;
a network socket circuit;
a direct current power supply;
an anti-interference module;
the receiving and transmitting control circuit is used for controlling data transmission between the equipment and an external network;
the network socket circuit is used for connecting an external network circuit;
the direct current power supply is used for supplying power to the transceiving control circuit and the network socket circuit;
the receiving and transmitting control circuit is electrically connected with the network socket circuit;
the anti-interference module is used for eliminating circuit interference generated by the transceiving control circuit, the network socket circuit and the direct-current power supply;
the receiving and sending control circuit and the network socket circuit are respectively electrically connected with the anti-interference module, and the anti-interference module is also electrically connected with the direct-current power supply.
Combine ethernet interface circuit, in a first possible implementation, anti-interference module includes:
a first anti-jamming circuit;
the first anti-jamming circuit is electrically connected with the direct current power supply and used for eliminating interference generated by the direct current power supply in the power supply process.
With reference to the first possible implementation manner of the present invention, in a second possible implementation manner, the transceiver control circuit includes:
a transceiver chip unit;
the anti-jamming module further comprises:
a second anti-jamming circuit;
a third anti-jamming circuit;
the second anti-interference circuit and the third anti-interference circuit are respectively connected with a power pin of the transceiver chip unit and used for carrying out interference suppression on a direct-current power supply input to the chip.
With reference to the second possible implementation manner of the present invention, in a third possible implementation manner, the network socket circuit includes:
a socket chip unit;
the anti-jamming module further comprises:
a fourth anti-jamming circuit;
and two ends of the fourth anti-interference circuit are respectively and electrically connected with a first center tap and a second center tap of a voltage conversion module in the socket chip unit, and are used for anti-interference of the voltage input to the network socket circuit from the transceiving control circuit.
With reference to the first possible implementation manner of the present invention, in a fourth possible implementation manner, the first anti-jamming circuit includes:
the circuit comprises a first inductor, a second inductor, a first capacitor and a second capacitor;
the first end of the first inductor, the first end of the second inductor and the first end of the first capacitor are connected with the input end of the direct-current power supply in common;
the second end of the first inductor, the second end of the second inductor and the first end of the second capacitor are connected together and then output a direct current power supply;
and the second end of the first capacitor and the second end of the second capacitor are grounded after being connected together.
With reference to the second possible implementation manner of the present invention, in a fifth possible implementation manner, the second anti-interference circuit includes:
a third capacitor, a fourth capacitor and a fifth capacitor;
the third immunity circuit includes:
a sixth capacitor and a seventh capacitor;
the first end of the third capacitor, the first end of the fourth capacitor and the first end of the fifth capacitor are respectively connected with the first power input pin, the second power input pin and the third power input pin of the transceiver chip unit, and the second end of the third capacitor, the second end of the fourth capacitor and the second end of the fifth capacitor are grounded after being connected in common;
and the first end of the sixth capacitor and the first end of the seventh capacitor are connected with the fourth power input pin of the transceiving chip unit, and the second end of the sixth capacitor and the second end of the seventh capacitor are connected with the ground.
With reference to the second possible implementation manner of the present invention, in a sixth possible implementation manner, the fourth anti-jamming circuit includes:
an eighth capacitor and a ninth capacitor;
the first end of the eighth capacitor and the first end of the ninth capacitor are electrically connected with a first center tap and a second center tap of the voltage conversion module of the socket chip unit respectively;
and the second end of the eighth capacitor and the second end of the ninth capacitor are respectively connected with the ground in common and then are grounded.
Implement an ethernet interface circuit, take a percentage through the power input end at DC power supply, send and receive control circuit's power input pin and network socket circuit's voltage conversion module center and introduce anti jamming circuit, the filtering has been guaranteed network transmission's stability to the influence that interface circuit caused DC power supply unstability or external electromagnetic interference.
Drawings
Fig. 1 is a first schematic diagram of an ethernet interface circuit module connection according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a module connection of a first interference rejection circuit in an Ethernet interface circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a circuit connection of a first interference rejection circuit in an Ethernet interface circuit according to an embodiment of the present application;
fig. 4 is a schematic diagram of module connection of a transceiver chip unit according to an embodiment of the present disclosure;
fig. 5 is a schematic circuit structure diagram of a transceiver chip unit according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a module connection of a socket chip unit according to an embodiment of the present disclosure;
fig. 7 is a schematic circuit diagram of a socket chip unit according to an embodiment of the present disclosure;
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or intervening elements may also be present.
It should be noted that the terms of orientation such as left, right, up and down in the present embodiment are only relative concepts or are referred to the normal use state of the product, and should not be considered as limiting.
In an LED projection device, an LED movie screen may be formed by splicing a plurality of LED display screens into a single screen. Because movie screens generally have a larger size, the number of LED display screens used for splicing is large, and in some cases, the number of LED display screens that may be required for one LED movie screen may reach about one hundred. The LED screens may receive or transmit video data through network cables, and may also communicate with the control device through the network cables, so that it is necessary to ensure that data transmission of the LED screens is interfered as little as possible.
However, in the prior art, the ethernet interface circuit is easily affected by external interference, which results in unstable signal transmission.
In view of the above problems, an ethernet interface circuit is provided.
An ethernet interface circuit, as shown in fig. 1, fig. 1 is a first schematic diagram illustrating a module connection of an ethernet interface circuit according to an embodiment of the present application; the system comprises a transceiving control circuit 100, a network socket circuit 200, a direct current power supply 400 and an anti-interference module 300; the transceiving control circuit 100 is used for controlling data transmission between the device and an external network; the network socket circuit 200 is used for connecting an external network circuit; the dc power supply 400 is used to provide power to the transceiving control circuit 100 and the network socket circuit 200; the transceiving control circuit 100 is electrically connected with the network socket circuit 200; the anti-interference module 300 is configured to eliminate circuit interference generated by the transceiver control circuit 100, the network socket circuit 200, and the dc power supply 400; the transceiving control circuit 100 and the network socket circuit 200 are electrically connected to the anti-interference module 300, respectively, and the anti-interference module 300 is further electrically connected to the dc power supply 400. The anti-interference circuit is introduced into the power input end of the direct-current power supply 400, the power input pin of the transceiving control circuit 100 and the center tap of the voltage conversion module of the network socket circuit 200, so that the influence of instability of the direct-current power supply 400 or external electromagnetic interference on the interface circuit is filtered, and the stability of network transmission is ensured.
Preferably, the dc power supply is 3.3V.
Preferably, as shown in fig. 2, fig. 2 is a schematic diagram of module connection of a first interference rejection circuit 310 in an ethernet interface circuit provided in the embodiment of the present application; the tamper resistant module 300 includes: a first immunity circuit 310; the first anti-jamming circuit 310 is electrically connected to the dc power supply 400, and is configured to eliminate interference generated by the dc power supply 400 during power supply.
Specifically, as shown in fig. 3, fig. 3 is a schematic circuit connection diagram of a first interference rejection circuit 310 in an ethernet interface circuit provided in the embodiment of the present application; the first immunity circuit 310 includes: a first inductor L1, a second inductor L2, a first capacitor C1 and a second capacitor C2; the first end of the first inductor L1, the first end of the second inductor L2, and the first end of the first capacitor C1 are connected to the input terminal of the dc power supply 400; after the second end of the first inductor L1, the second end of the second inductor L2, and the first end of the second capacitor C2 are connected together, the dc power supply 400 is output; the second end of the first capacitor C1 and the second end of the second capacitor C2 are grounded after being connected together.
The first anti-jamming circuit 310 filters out noise and interference from the dc power supply 400.
Preferably, as shown in fig. 4, fig. 4 is a schematic diagram of module connection of a transceiver chip unit according to an embodiment of the present application; the transceiving control circuit 100 includes a transceiving chip unit 110; the immunity module 300 further includes a second immunity circuit 320, a third immunity circuit 330; the second anti-jamming circuit 320 and the third anti-jamming circuit 330 are respectively connected to the power pins of the transceiver chip unit 110, and are configured to perform jamming suppression on the dc power 400 input to the chip.
Specifically, as shown in fig. 5, fig. 5 is a schematic circuit structure diagram of a transceiver chip unit according to an embodiment of the present disclosure; the second anti-interference circuit 320 comprises a third capacitor C3, a fourth capacitor C4 and a fifth capacitor C5; the third anti-jamming circuit 330 comprises a sixth capacitor C6, a seventh capacitor C7; a first end of the third capacitor C3, a first end of the fourth capacitor C4, and a first end of the fifth capacitor C5 are respectively connected to the first power input pin VDD1A, the second power input pin VDD2A, and the third power input pin VDD1IO of the transceiver chip unit 110, and a second end of the third capacitor C3, a second end of the fourth capacitor C4, and a second end of the fifth capacitor C5 are grounded after being connected in common; the first end of the sixth capacitor C6 and the first end of the seventh capacitor C7 are commonly connected to the fourth power input pin VDDCR of the transceiver chip unit 110, and the second end of the sixth capacitor C6 and the second end of the seventh capacitor C7 are commonly connected to the ground.
Specifically, the transceiver chip unit 110 may select a LAN chip, or select an RTL chip, or select a WG chip, and the specific chip may be selected according to actual needs, and only needs to be used for data transmission of the ethernet.
Fig. 5 is a schematic structural diagram of a chip of the transceiver chip unit 110, which includes pins as shown in fig. 5. Preferably a LAN8720A chip.
The second anti-jamming circuit 320 and the third anti-jamming circuit 330 perform interference filtering on the power input to the power pin of the transceiver chip.
Preferably, as shown in fig. 6, fig. 6 is a schematic diagram of module connection of a socket chip unit according to an embodiment of the present application; the network socket circuit 200 includes a socket chip unit 210; the immunity module 300 also includes a fourth immunity circuit 340; both ends of the fourth interference rejection circuit 340 are electrically connected to the first center tap TCT and the second center tap RCT of the voltage conversion module in the socket chip unit 210, respectively, and are configured to perform interference rejection on the voltage input from the transceiver control circuit 100 to the network socket circuit 200.
Specifically, as shown in fig. 7, fig. 7 is a schematic circuit structure diagram of a socket chip unit according to an embodiment of the present application; the fourth anti-jamming circuit 340 comprises an eighth capacitor C8 and a ninth capacitor C9; a first end of the eighth capacitor C8 and a first end of the ninth capacitor C9 are electrically connected to a first center tap TCT and a second center tap RCT of the voltage conversion module of the socket chip unit 210, respectively; the second end of the eighth capacitor C8 and the second end of the ninth capacitor C9 are respectively connected to the ground.
Specifically, the socket chip in the socket chip unit can select HR series chips, or select KS series chips, or select CS series chips, etc., and specific chips can be selected according to actual needs, and only need be used for the line connection at the ethernet interface.
Fig. 7 is a schematic circuit diagram of a socket chip. The socket chip is preferably an HR911105A chip.
Implement an ethernet interface circuit, take a percentage through the power input end at DC power supply 400, the power input pin of receiving and dispatching control circuit 100 and network socket circuit 200's voltage conversion module center and introduce anti jamming circuit, the filtering has been given a percentage the influence that DC power supply 400 unstability or external electromagnetic interference caused interface circuit, has guaranteed network transmission's stability.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (7)
1. An ethernet interface circuit, comprising:
a transmit-receive control circuit;
a network socket circuit;
a direct current power supply;
an anti-interference module;
the receiving and transmitting control circuit is used for controlling data transmission of the intranet equipment and the extranet;
the network socket circuit is used for connecting an external network circuit;
the direct current power supply is used for supplying power to the transceiving control circuit and the network socket circuit;
the receiving and transmitting control circuit is electrically connected with the network socket circuit;
the anti-interference module is used for eliminating circuit interference generated by the transceiving control circuit, the network socket circuit and the direct-current power supply;
the receiving and sending control circuit and the network socket circuit are respectively electrically connected with the anti-interference module, and the anti-interference module is also electrically connected with the direct-current power supply.
2. An ethernet interface circuit in accordance with claim 1, wherein said immunity module comprises:
a first anti-jamming circuit;
the first anti-jamming circuit is electrically connected with the direct current power supply and used for eliminating interference generated by the direct current power supply in the power supply process.
3. An ethernet interface circuit in accordance with claim 2, wherein said transceive control circuit comprises:
a transceiver chip unit;
the anti-jamming module further comprises:
a second anti-jamming circuit;
a third anti-jamming circuit;
the second anti-interference circuit and the third anti-interference circuit are respectively connected with a power pin of the transceiver chip unit and used for carrying out interference suppression on a direct-current power supply input to the chip.
4. An ethernet interface circuit in accordance with claim 3, wherein said network jack circuit comprises:
a socket chip unit;
the anti-jamming module further comprises:
a fourth anti-jamming circuit;
and two ends of the fourth anti-interference circuit are respectively and electrically connected with a first center tap and a second center tap of the voltage conversion module in the socket chip unit and are used for resisting interference on the voltage input to the network socket circuit from the transceiving control circuit.
5. An ethernet interface circuit in accordance with claim 2, wherein said first immunity circuit comprises:
the circuit comprises a first inductor, a second inductor, a first capacitor and a second capacitor;
the first end of the first inductor, the first end of the second inductor and the first end of the first capacitor are connected with the input end of the direct-current power supply in common;
the second end of the first inductor, the second end of the second inductor and the first end of the second capacitor are connected together, and then a direct-current power supply is output;
and the second end of the first capacitor and the second end of the second capacitor are grounded after being connected together.
6. An ethernet interface circuit in accordance with claim 3, wherein said second anti-interference circuit comprises:
a third capacitor, a fourth capacitor and a fifth capacitor;
the third immunity circuit includes:
a sixth capacitor and a seventh capacitor;
the first end of the third capacitor, the first end of the fourth capacitor and the first end of the fifth capacitor are respectively connected with the first power input pin, the second power input pin and the third power input pin of the transceiver chip unit, and the second end of the third capacitor, the second end of the fourth capacitor and the second end of the fifth capacitor are grounded after being connected in common;
and the first end of the sixth capacitor and the first end of the seventh capacitor are connected with the fourth power input pin of the transceiver chip unit, and the second end of the sixth capacitor and the second end of the seventh capacitor are connected with the ground.
7. An Ethernet interface circuit in accordance with claim 4, wherein said fourth immunity circuit comprises:
an eighth capacitor and a ninth capacitor;
the first end of the eighth capacitor and the first end of the ninth capacitor are electrically connected with a first center tap and a second center tap of the voltage conversion module of the socket chip unit respectively;
and the second end of the eighth capacitor and the second end of the ninth capacitor are respectively connected with the ground in common.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221580495.6U CN217607826U (en) | 2022-06-22 | 2022-06-22 | Ethernet interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221580495.6U CN217607826U (en) | 2022-06-22 | 2022-06-22 | Ethernet interface circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217607826U true CN217607826U (en) | 2022-10-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221580495.6U Active CN217607826U (en) | 2022-06-22 | 2022-06-22 | Ethernet interface circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217607826U (en) |
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2022
- 2022-06-22 CN CN202221580495.6U patent/CN217607826U/en active Active
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