CN217606820U - Display panel and display device - Google Patents

Abstract

The utility model discloses a display panel and display device relates to and shows technical field to shelter from pixel drive circuit. The display panel includes: the display device includes a substrate and a plurality of first pixel units. The plurality of first pixel units are arranged in multiple rows and multiple columns; the first pixel unit comprises a plurality of sub-pixels, and each sub-pixel comprises a pixel driving circuit and a light-emitting device; the light-emitting device is positioned on one side of the pixel driving circuit, which is far away from the substrate, and is electrically connected with the pixel driving circuit; the pixel driving circuit includes a first reset transistor; the plurality of sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel, and the area of the light emitting device of the first sub-pixel is larger than the area of the light emitting device of the second sub-pixel and larger than the area of the light emitting device of the third sub-pixel; the orthographic projection of the first reset transistor in the second sub-pixel and/or the first reset transistor in the third sub-pixel on the substrate is positioned in the orthographic projection of the light-emitting device of the first sub-pixel on the substrate. The display panel is used in a display device.

Description

Display panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

At present, an OLED (organic light-emitting diode) display device is widely used because it has the characteristics of self-luminescence, fast response, wide viewing angle, and being capable of being manufactured on a flexible substrate, and the like.

SUMMERY OF THE UTILITY MODEL

The present disclosure provides a display panel and a display device, so as to shield a pixel driving circuit.

In order to achieve the above object, the present disclosure provides the following technical solutions:

in one aspect, a display panel is provided. The display panel includes: the display device includes a substrate and a plurality of first pixel units. The plurality of first pixel units are positioned on one side of the substrate and are arranged in a plurality of rows and columns; the first pixel unit comprises a plurality of sub-pixels, and each sub-pixel comprises a pixel driving circuit and a light-emitting device; the light-emitting device is positioned on one side of the pixel driving circuit, which is far away from the substrate, and is electrically connected with the pixel driving circuit; the pixel driving circuit includes a first reset transistor.

The plurality of sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel, and the area of the light emitting device of the first sub-pixel is larger than the area of the light emitting device of the second sub-pixel and larger than the area of the light emitting device of the third sub-pixel.

And the orthographic projection of the first reset transistor in the second sub-pixel and/or the first reset transistor in the third sub-pixel on the substrate is positioned in the orthographic projection of the light-emitting device of the first sub-pixel on the substrate.

In some embodiments, the first reset transistor of the first sub-pixel, the first reset transistor of the second sub-pixel, and the first reset transistor of the third sub-pixel are all located within a front projection of the light emitting device of the first sub-pixel on the substrate.

In some embodiments, at least two of the first reset transistor of the first sub-pixel, the first reset transistor of the second sub-pixel, and the first reset transistor of the third sub-pixel are the same transistor.

In some embodiments, the pixel driving circuit further comprises a second reset transistor; the second reset transistor of the first sub-pixel, the second reset transistor of the second sub-pixel and the second reset transistor of the third sub-pixel are the same transistor; the orthographic projection of the second reset transistor on the substrate is positioned in the orthographic projection of the light-emitting device of the first sub-pixel on the substrate; the second reset transistor is connected in series with any of the first reset transistors.

The display panel further comprises a reset signal line and an initialization signal line; a control electrode of each of the first reset transistors and a control electrode of the second reset transistor are electrically connected to the reset signal line; a first pole of the second reset transistor is electrically connected to the initialization signal line, and a second pole of the second reset transistor is electrically connected to the first pole of each of the first reset transistors.

The pixel driving circuit further includes: and a control electrode of the driving transistor of each pixel driving circuit is electrically connected with the second electrode of each first reset transistor.

In some embodiments, the light emitting device of the second sub-pixel and the light emitting device of the third sub-pixel are disposed at intervals in a column direction; the light emitting device of the first sub-pixel is positioned in an adjacent column of the columns where the light emitting device of the second sub-pixel and the light emitting device of the third sub-pixel are positioned; and the light emitting device of the first sub-pixel spans a gap region between the light emitting device of the second sub-pixel and the light emitting device of the third sub-pixel.

The pixel driving circuit further comprises a circuit main body; an orthogonal projection of the circuit body of the first sub-pixel on the substrate is positioned within an orthogonal projection of the light emitting device of the first sub-pixel on the substrate, an orthogonal projection of the circuit body of the second sub-pixel on the substrate is positioned within an orthogonal projection of the light emitting device of the second sub-pixel on the substrate, and an orthogonal projection of the circuit body of the third sub-pixel on the substrate is positioned within an orthogonal projection of the light emitting device of the third sub-pixel on the substrate.

In some embodiments, the second reset transistor, the first reset transistor of the third sub-pixel, and the first reset transistor of the second sub-pixel are located on a side of the first reset transistor of the first sub-pixel close to the circuit body of the third sub-pixel, and sequentially away from the circuit body of the third sub-pixel.

In some embodiments, the reset signal lines extend in a row direction, one of the reset signal lines is electrically connected to the control electrode of the second reset transistor and the control electrode of each of the first reset transistors in one row of the first pixel units, the initialization signal line extends in the row direction, and one of the initialization signal lines is electrically connected to the first electrode of the second reset transistor in one row of the first pixel units.

The orthographic projection of the second reset transistor and each first reset transistor on the substrate is positioned between the orthographic projection of an initialization signal line electrically connected with the second reset transistor on the substrate and the orthographic projection of the circuit main body of the third sub-pixel on the substrate; the orthographic projection of the reset signal line on the substrate is positioned between the orthographic projection of the initialization signal line on the substrate and the orthographic projection of the circuit main body of the third sub-pixel on the substrate.

In some embodiments, the substrate includes a first display region, the plurality of first pixel cells being located within the first display region.

The display panel further includes: a plurality of signal lines between the substrate and the light emitting device; the part of at least one signal wire in the first display area comprises a metal wire and a transparent connecting wire which are electrically connected with each other; at least part of the orthographic projection of the metal wiring on the substrate is positioned in the orthographic projection of the light-emitting device on the substrate.

In some embodiments, the display panel includes: and the first grid metal layer and the first transparent wiring layer are both positioned between the substrate and the light-emitting device, and the first transparent wiring layer is positioned on one side of the first grid metal layer, which deviates from the substrate.

The at least one signal line includes a reset signal line extending in a row direction, and one of the reset signal lines is electrically connected to a control electrode of the second reset transistor and a control electrode of each of the first reset transistors in one row of the first pixel units.

The metal routing of the reset signal line is positioned on the first gate metal layer, and at least part of the orthographic projection of the metal routing of the reset signal line on the substrate is positioned in the orthographic projection of the light-emitting device of the first sub-pixel on the substrate; the transparent connecting wiring of the reset signal line is positioned on the first transparent wiring layer; the orthographic projection of the transparent connecting wiring of the reset signal line on the substrate is positioned outside the orthographic projection of the light-emitting device of the second sub-pixel on the substrate and outside the orthographic projection of the light-emitting device of the third sub-pixel on the substrate; the transparent connecting wires of the reset signal wires are connected with the metal wires of the reset signal wires through via holes.

In some embodiments, the circuit body of the pixel driving circuit includes a write transistor, a compensation transistor, and a third reset transistor; the at least one signal line further includes a scanning signal line, and one scanning signal line is electrically connected to the control electrodes of the writing transistors, the compensation transistors, and the third reset transistors of all the sub-pixels in one row of the first pixel unit.

The metal routing of the scanning signal line is positioned on the first grid metal layer, and at least part of the orthographic projection of the metal routing of the scanning signal line on the substrate is positioned in the orthographic projection of the light-emitting device on the substrate; the transparent connecting wires of the scanning signal wires are positioned on the first transparent wire layer, and the transparent connecting wires of the scanning signal wires are connected with the metal wires of the scanning signal wires through via holes.

In some embodiments, the circuit body of the pixel driving circuit further includes a first light emission control transistor and a second light emission control transistor; the at least one signal line further includes a light emission control signal line, and one of the light emission control signal lines is electrically connected to the control electrodes of the first light emission control transistors and the control electrodes of the second light emission control transistors of all the sub-pixels in one row of the first pixel unit.

The metal wiring of the light-emitting control signal wire is positioned on the first gate metal layer, and at least part of the orthographic projection of the metal wiring of the light-emitting control signal wire on the substrate is positioned in the orthographic projection of the light-emitting device on the substrate; the transparent connecting wires of the light-emitting control signal wires are positioned on the first transparent wire routing layer, and the transparent connecting wires of the light-emitting control signal wires are connected with the metal wires of the light-emitting control signal wires through via holes.

In some embodiments, the display panel includes: and the first source drain metal layer and the first transparent routing layer are positioned between the substrate and the light-emitting device, and the first transparent routing layer is positioned on one side of the first source drain metal layer, which deviates from the substrate.

The at least one signal line further includes: initialization signal lines, one of which is electrically connected to the first poles of the second reset crystals in one row of the first pixel units; the metal wiring of the initialization signal line is positioned on the first source-drain metal layer, and at least part of the orthographic projection of the metal wiring of the initialization signal line on the substrate is positioned in the orthographic projection of the light-emitting device of the first sub-pixel on the substrate; the transparent connecting wiring of the initialization signal wire is positioned on the first transparent wiring layer; the orthographic projection of the transparent connecting wiring of the initialization signal wire on the substrate is positioned outside the orthographic projection of the light-emitting device of the second sub-pixel on the substrate and outside the orthographic projection of the light-emitting device of the third sub-pixel on the substrate; the transparent connecting wires of the initialization signal wires are connected with the metal wires of the initialization signal wires through via holes.

In some embodiments, the display panel includes: the second grid metal layer, the second source drain metal layer and the second transparent wiring layer are located between the substrate and the light-emitting device, the second source drain metal layer is located on one side, deviating from the substrate, of the second grid metal layer, and the second transparent wiring layer is located on one side, deviating from the second grid metal layer, of the second source drain metal layer. The circuit body of the pixel driving circuit further includes: and a capacitor, wherein the first plate of the capacitor is positioned on the second gate metal layer.

The at least one signal line further includes a first power signal line extending in a column direction, one of the first power signal lines being electrically connected to a first plate of a capacitor of the second sub-pixel and a first plate of a capacitor of the third sub-pixel in a column of the first pixel unit.

The metal wire of the first power signal wire is positioned on the second source-drain metal layer, and at least part of the orthographic projection of the metal wire of the first power signal wire on the substrate is positioned in the orthographic projection of the light-emitting device of the second sub-pixel and the light-emitting device of the third sub-pixel on the substrate; the transparent connecting wire of the first power signal wire is positioned on the second transparent wire layer, and the transparent connecting wire of the first power signal wire is connected with the metal wire of the first power signal wire through a via hole.

In some embodiments, the at least one signal line further includes a second power signal line extending in the column direction, one of the second power signal lines being electrically connected to the first plates of the capacitors of the first subpixels in one column of the first pixel units.

The metal wire of the second power signal wire is positioned on the second source-drain metal layer, and the orthographic projection of the metal wire of the second power signal wire on the substrate is at least partially positioned in the orthographic projection of the light-emitting device of the first sub-pixel on the substrate; the transparent connecting wire of the second power signal wire is positioned on the second transparent wire layer, and the transparent connecting wire of the second power signal wire is connected with the metal wire of the second power signal wire through a via hole.

In some embodiments, the display panel further comprises: a plurality of data lines extending in a column direction, an orthographic projection of a portion of the plurality of data lines in the first display area on the substrate being outside an orthographic projection of a light emitting device of any one of the sub-pixels on the substrate, and a portion of at least one data line in the first display area on the second transparent routing layer.

The circuit body of the pixel driving circuit includes: a write transistor; in one of the first pixel units, a first pole of the writing transistor of the first subpixel, a first pole of the writing transistor of the second subpixel, and a first pole of the writing transistor of the third subpixel are connected to different ones of the data lines, respectively.

In some embodiments, the portion of the at least one data line in the first display area is a transparent line segment.

In the same column of the first pixel units, the orthographic projection of a transparent line segment of a data line electrically connected with a writing transistor in the first sub-pixel on the substrate is positioned on one side, away from the orthographic projection of a circuit main body of the second sub-pixel on the substrate, of the circuit main body of the first sub-pixel; the orthographic projection of the light-emitting device of the second sub-pixel on the substrate and the orthographic projection of the light-emitting device of the third sub-pixel on the substrate are positioned between the orthographic projection of the transparent route segment of the data wire electrically connected with the writing transistor of the second sub-pixel on the substrate and the orthographic projection of the transparent route segment of the data wire electrically connected with the writing transistor of the third sub-pixel on the substrate.

In some embodiments, the circuit body of the pixel driving circuit further includes a compensation transistor and a third reset transistor.

In one first pixel unit, a writing transistor, a compensation transistor and a third reset transistor in the first sub-pixel are sequentially far away from a circuit main body of the second sub-pixel; the writing transistor, the compensation transistor and the third reset transistor in the second sub-pixel are sequentially arranged along a first set direction; and the writing transistor, the compensation transistor and the third reset transistor in the third sub-pixel are sequentially arranged along the reverse direction of the first setting direction.

In some embodiments, the light emitting device includes an anode electrically connected to the pixel driving circuit, a light emitting layer on a side of the anode facing away from the substrate, and a cathode on a side of the light emitting layer facing away from the substrate. And the orthographic projection of the first reset transistor in the second sub-pixel and/or the first reset transistor in the third sub-pixel on the substrate is positioned in the orthographic projection of the anode of the first sub-pixel on the substrate.

In some embodiments, the first sub-pixel is a blue sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a red sub-pixel.

In some embodiments, the display panel includes: a first display area and a second display area. The first display area is provided with the first pixel unit; the second display area is provided with a plurality of second pixel units which are arranged in a plurality of rows and a plurality of columns; the second pixel unit comprises a plurality of sub-pixels, and the sub-pixel density of the first display area is equal to that of the second display area; the area of the light emitting device of the sub-pixel in the first display area is 0.4-0.6 times that of the light emitting device of the sub-pixel in the same color in the second display area.

In yet another aspect, a display device is provided. The display device includes: a display panel as claimed in any one of the above embodiments.

The display panel and the display device provided by the disclosure have the following beneficial effects:

the present disclosure provides a display panel in which the area of the light emitting device of the first sub-pixel is the largest, and the area of the light emitting device of the second sub-pixel and the area of the light emitting device of the third sub-pixel are both relatively small. The first reset transistor of the pixel driving circuit in the second sub-pixel and/or the first reset transistor of the pixel driving circuit in the third sub-pixel are hidden under the light emitting device of the first sub-pixel, so that the first reset transistor in the second sub-pixel and/or the first reset transistor in the third sub-pixel can be shielded, and the area of the light emitting device of the first sub-pixel is large, so that the structure of the pixel driving circuit under the light emitting device of the first sub-pixel is not too compact, and the space under the light emitting device of the first sub-pixel is reasonably utilized.

The beneficial effects that the display device that this disclosure can realize are the same with the beneficial effects that the display panel that above-mentioned technical scheme provided can reach, and do not describe here any longer.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings required to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to these drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1A is a block diagram of a display device according to some embodiments;

FIG. 1B is a block diagram of a display device according to some embodiments;

FIG. 2A is a block diagram of a display device according to some embodiments;

FIG. 2B is a block diagram of a display panel according to some embodiments;

FIG. 3A is a block diagram of a display panel according to some embodiments;

FIG. 3B is a block diagram of a display panel according to some embodiments;

FIG. 4A is a block diagram of a pixel drive unit according to some embodiments;

FIG. 4B is a timing diagram of a pixel driving circuit according to some embodiments;

FIG. 4C is a block diagram of a pixel drive unit according to some embodiments;

FIG. 4D is a block diagram of a pixel drive unit according to some embodiments;

FIG. 4E is a block diagram of a pixel drive unit according to some embodiments;

FIG. 4F is a block diagram of a pixel drive unit according to some embodiments;

FIG. 5A is a block diagram of a display panel according to some embodiments;

FIG. 5B is a block diagram of a display panel according to some embodiments;

FIG. 5C is a block diagram of a display panel according to some embodiments;

FIG. 5D is a block diagram of a display panel according to some embodiments;

FIG. 6A is a block diagram of a display panel according to some embodiments;

FIG. 6B is a block diagram of a display panel according to some embodiments;

FIG. 7A is a block diagram of a display panel according to some embodiments;

FIG. 7B is a block diagram of a display panel according to some embodiments;

FIG. 7C is a block diagram of a display panel according to some embodiments;

FIG. 8A is a block diagram of a display panel according to some embodiments;

FIG. 8B is a block diagram of a display panel according to some embodiments;

FIG. 9A is a block diagram of a display panel according to some embodiments;

FIG. 9B is a block diagram of a display panel according to some embodiments;

FIG. 9C is a block diagram of a display panel according to some embodiments;

FIG. 10A is a block diagram of a display panel according to some embodiments;

FIG. 10B is a block diagram of a display panel according to some embodiments;

FIG. 11A is a block diagram of a display panel according to some embodiments;

FIG. 11B is a block diagram of a display panel according to some embodiments;

FIG. 11C is a block diagram of a display panel according to some embodiments;

FIG. 11D is a block diagram of a display panel according to some embodiments;

FIG. 11E is a block diagram of a display panel according to some embodiments;

FIG. 12A is a block diagram of a display panel according to some embodiments;

FIG. 12B is a block diagram of a display panel according to some embodiments;

FIG. 12C is a block diagram of a display panel according to some embodiments;

FIG. 13A is a block diagram of a display panel according to some embodiments;

FIG. 13B is a block diagram of a display panel according to some embodiments;

FIG. 14 is a block diagram of a display panel according to some embodiments.

Detailed Description

The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided in the present disclosure are within the scope of protection of the present disclosure.

Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "some embodiments(s)", "example(s)", or "some example(s)", etc. are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment(s) or example(s) is included in at least one embodiment or example of the present disclosure. The schematic representations of the terms used above are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, the expression "connected" and its derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

As used herein, the term "if" is optionally interpreted to mean "when 8230; \8230, when" or "at 8230; \8230, when", depending on the context.

The use of "configured to" herein means open and inclusive language that does not exclude devices that are suitable or configured to perform additional tasks or steps.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

In describing some embodiments, it is possible to use a ' certain structure ' disposed below the anode ' or

'a structure' is located below the anode 'or' a structure 'is hidden below the anode' means that the orthographic projection of the structure on the substrate is located within the orthographic projection of the anode on the substrate.

In describing some embodiments, the term "area of a structure" may be used to denote the area of the orthographic projection of a structure on a substrate.

As used herein, "substantially" or "approximately" includes the stated value as well as an average value that is within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

As used herein, "parallel," "perpendicular," and "equal" include the stated case and cases that approximate the stated case to within an acceptable range of deviation as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, where an acceptable deviation from approximately parallel may be, for example, within 5 °; "perpendicular" includes absolute perpendicular and approximately perpendicular, where an acceptable deviation from approximately perpendicular may also be, for example, within 5 °. "equal" includes absolute and approximate equality, where the difference between the two, which may be equal within an acceptable deviation of approximately equal, is less than or equal to 5% of either.

It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

Some embodiments of the present disclosure provide a display device. Fig. 1A and 1B are block diagrams of display devices according to some embodiments. Referring to fig. 1A and 1B, a display device 100 is a product having an image (including a still image or a moving image, wherein the moving image may be a video) display function. For example, the display device 100 may be: the mobile phone comprises any one of a watch, a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA for short), a digital camera, a portable video camera, a viewfinder, a navigator, a vehicle, a large-area wall, a household appliance, an information inquiry device (such as a business inquiry device of the departments of electronic government affairs, banks, hospitals, electric power and the like), a monitor and the like.

Referring to fig. 2A, the display device 100 includes a display panel 200 and a sensor 300.

Some embodiments of the present disclosure provide a display panel 200, and fig. 2B is a structural diagram of a display panel according to some embodiments. Referring to fig. 2B, the display panel 200 includes a display area AA and a peripheral area BB disposed on at least one side of the display area AA. The display area AA is used for displaying a picture. In some examples, the peripheral region BB may be disposed on one or more sides of the display region AA. In other examples, the peripheral region BB is disposed around the display region AA once.

The display panel 200 may be an OLED (organic light-emitting diode) display panel. The OLED display panel has the advantages of wide viewing angle, high contrast, fast response, low power consumption, foldability, flexibility and the like.

Referring to fig. 2B, the display panel 200 includes a substrate 210 and a plurality of first pixel units 220, wherein the plurality of first pixel units 220 are disposed on one side of the substrate 210 and arranged in a plurality of rows and a plurality of columns. The first pixel unit 220 includes a plurality of sub-pixels 230 therein. The sub-pixels 230 are the smallest units of the display panel 200 for displaying images, and each sub-pixel 230 can display a single color, such as red, green or blue. By adjusting the brightness (gray scale) of the sub-pixels with different colors, the display of multiple colors can be realized by color combination and superposition, so that the full-color display of the display panel 200 is realized.

In some embodiments, referring to fig. 2B, the display area AA includes a first display area A1, and the plurality of first pixel units 220 are disposed in the first display area A1. Referring to fig. 2A, the display panel 200 includes a backlight side 201 and a display side 202 disposed opposite to each other, wherein the display side 202 is used for displaying a picture. The sensor 300 is disposed on the backlight side 201 of the display panel 200. And is located in the first display area A1 of the display panel 200.

The sensor 300 is, for example, an image sensor or an infrared sensor. The sensor 300 is configured to receive light from the display side 202 of the display panel 200, so that operations such as image capturing, distance sensing, light intensity sensing, and the like can be performed. The light may be transmitted through the first display area A1 and then irradiated onto the sensor 300, thereby being sensed by the sensor 300.

By disposing the sensor 300 in the first display area A1 of the display panel 200 and on the backlight side 201 of the display panel, holes can be prevented from being dug in the display screen, the screen occupation ratio is improved, and better visual experience is achieved.

Fig. 3A is a block diagram of a display panel in a first display area A1 according to some embodiments. Referring to fig. 3A, one sub-pixel 230 includes a pixel driving circuit 231 and a light emitting device 232, and the light emitting device 232 is located on a side of the pixel driving circuit 231 away from the substrate 210 and electrically connected to the pixel driving circuit 231. The pixel driving circuit 231 is used for driving the light emitting device 232 to emit light.

Fig. 3B is a block diagram of a display panel according to some embodiments, and the structure of one sub-pixel is shown in fig. 3B. Referring to fig. 3B, the light emitting device 232 includes an anode AND1, a light emitting layer EL, AND a cathode CTD1. The anode AND1 is located on a side of the pixel driving circuit 231 away from the substrate 210, AND is electrically connected to the pixel driving circuit 231. The light-emitting layer EL is located on the side of the anode AND1 facing away from the substrate 210, AND the cathode CTD1 is located on the side of the light-emitting layer EL facing away from the substrate 210. In some examples, the light emitting device 232 further includes one or more of an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), a Hole Transport Layer (HTL), and a Hole Injection Layer (HIL).

In some examples, an orthographic projection of anode AND1 on substrate 210, an orthographic projection of light-emitting layer EL on substrate 210, AND an orthographic projection of cathode CTD1 on substrate 210 at least partially coincide.

Referring to fig. 3A, the plurality of sub-pixels 230 in one first pixel unit 220 include a first sub-pixel 230B, a second sub-pixel 230G and a third sub-pixel 230R.

In one first pixel unit 220, the area of the light emitting device 232 of the first sub-pixel 230B is larger than the area of the light emitting device 232 of the second sub-pixel 230G, and is larger than the area of the light emitting device 232 of the third sub-pixel 230R. Accordingly, referring to FIG. 3A, in a first pixel unit 220, the area of the anode AND-B of the first sub-pixel 230B is larger than the area of the anode AND-G of the second sub-pixel 230G, AND is larger than the area of the anode AND-R of the third sub-pixel 230R. Accordingly, in one first pixel unit 220, the area of the emission layer EL of the first sub-pixel 230B is larger than that of the emission layer EL of the second sub-pixel 230G and larger than that of the emission layer EL of the third sub-pixel 230R. Accordingly, in one first pixel unit 220, the area of the cathode CTD1 of the first sub-pixel 230B is larger than the area of the cathode CTD1 of the second sub-pixel 230G, and is larger than the area of the cathode CTD1 of the third sub-pixel 230R.

The anodes AND1 are in a block shape, AND the anodes AND1 of different sub-pixels 230 are separated from each other. The light emitting layers EL are in a block shape, and the light emitting layers EL of different sub-pixels 230 are separated from each other.

In some examples, the cathodes CTD1 of the plurality of sub-pixels 230 in the display panel 200 are connected to each other, and the cathodes CTD1 of the plurality of sub-pixels 230 are of a whole-layer structure. In these examples, the area of the cathode CTD1 of one sub-pixel 230 is equal to the area of the light emitting layer EL or the area of the anode AND1. Further, in these examples, the area of the larger of the light-emitting layer EL AND the anode AND1 is the area of the light-emitting device 232. Illustratively, if the area of the orthographic projection of the anode AND1 on the substrate 210 is larger than the area of the orthographic projection of the light-emitting layer EL on the substrate 210, the area of the light-emitting device 232 is the area of the anode AND1. Illustratively, if the area of the orthographic projection of the light-emitting layer EL on the substrate 210 is larger than the area of the orthographic projection of the anode AND1 on the substrate 210, the area of the light-emitting device 232 is the area of the light-emitting layer EL.

In other examples, the cathode CTD1 is in a block shape, AND the cathodes CTD1 of the plurality of sub-pixels 230 in the display panel 200 are separated from each other, AND in this case, the area of the largest one of the cathode CTD1, the light emitting layer EL, AND the anode AND1 is the area of the light emitting device 232. For example, in the cathode CTD1, the light emitting layer EL AND the anode AND1 of one sub-pixel 230, if the area of the cathode CTD1 is the largest, the area of the light emitting device 232 is the area of the cathode CTD1. If the area of the anode AND1 is the largest, the area of the light emitting device 232 is the area of the anode AND1. If the area of the light emitting layer EL is the largest, the area of the light emitting device 232 is the area of the light emitting layer EL.

Illustratively, in the first pixel unit 220, the first sub-pixel 230B is a blue sub-pixel, the second sub-pixel 230G is a green sub-pixel, and the third sub-pixel 230R is a red sub-pixel.

The light-emitting layer EL includes an effective light-emitting area. In some examples, in one first pixel unit 220, the area of the light emitting device 232 of the first sub-pixel 230B is greater than the area of the light emitting device 232 of the second sub-pixel 230G and greater than the area of the light emitting device 232 of the third sub-pixel 230R. Correspondingly, the area of the effective light-emitting area of the first sub-pixel 230B is larger than that of the effective light-emitting area of the second sub-pixel 230G, and is larger than that of the effective light-emitting area of the third sub-pixel 230R. Here, the light emitting layer EL in the light emitting device 232 includes a light emitting material, the efficiency of the light emitting material of the blue sub-pixel is low, and the color shift problem caused by the difference of the light emitting efficiency of the red, green and blue sub-pixels can be reduced by maximizing the effective light emitting area of the blue sub-pixel.

In one implementation, the area of the light emitting device 232 of the sub-pixel 230 is reduced, and the pixel driving circuit 231 is hidden under the light emitting device 232, so that the area of the sub-pixel 230 occupied by the display panel 200 can be reduced, the area of the light transmitting region can be increased, and the light transmittance of the first display region A1 can be improved. Note that the area of the light-emitting device 232 refers to an area covered by an orthogonal projection of the light-emitting device 232 on the substrate 210. The pixel driving circuit 231 is hidden under the light emitting device 232, that is, the pixel driving circuit 231 is located on the side of the light emitting device 232 close to the substrate 210, and the orthographic projection of the pixel driving circuit 231 on the substrate 210 is located within the orthographic projection of the light emitting device 232 on the substrate 210.

However, since the light emitting devices 232 of the second sub-pixel 230G and the third sub-pixel 230R have smaller areas, it is difficult to hide the pixel driving circuits 231-G of the second sub-pixel 230G under the light emitting devices 232 of the second sub-pixel 230G and the pixel driving circuits 231-R of the third sub-pixel 230R under the light emitting devices 232 of the third sub-pixel 230R. If the pixel driving circuit 231 is exposed outside the light emitting device 232, the light transmittance of the first display area A1 is lowered and diffraction is increased, which is disadvantageous for image pickup.

Based on this, the present disclosure provides a pixel driving unit 400, referring to fig. 4A, the pixel driving unit 400 includes a plurality of pixel driving circuits 231.

In some embodiments, the structures of the pixel driving circuit in the present disclosure include a variety of structures, and the arrangement may be selected according to actual needs. For example, the structure of the pixel driving circuit 231 may include "6T1C", "7T1C", "6T2C", or "7T2C", and the like. Here, "T" is expressed as a thin film transistor, and the number located in front of "T" is expressed as the number of thin film transistors; "C" is denoted as a storage capacitor C, and the number located before "C" is denoted as the number of storage capacitors C. The following description will take a 7T1C mode pixel driving circuit as an example.

Referring to fig. 4A, one pixel driving circuit 231 includes a driving transistor T3 and a second reset transistor T12, the second reset transistor T12 is electrically connected to the reset signal terminal Rst, the initialization signal terminal Vin, and the control electrode of the driving transistor T3, the second reset transistor T12 is configured to: in response to the reset signal received at the reset signal terminal Rst, the initialization signal received at the initialization signal terminal Vin is transmitted to the control electrode of the driving transistor T3 to reset the control electrode of the driving transistor T3.

Illustratively, the second reset transistor T12 has a control electrode electrically connected to the reset signal terminal Rst, a first electrode electrically connected to the initialization signal terminal Vin, and a second electrode electrically connected to the control electrode of the driving transistor T3.

Referring to fig. 4A, the pixel driving circuit 231 includes a compensation transistor T2, a writing transistor T4, a first light emission controlling transistor T5, a second light emission controlling transistor T6, a third reset transistor T7, and a capacitor Cst in addition to the second reset transistor T12 and the driving transistor T3.

The control electrode of the compensation transistor T2 is electrically connected to the scanning signal terminal Gt, the first electrode of the compensation transistor T2 is electrically connected to the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is electrically connected to the control electrode of the driving transistor T3.

A control electrode of the write transistor T4 is electrically connected to the scanning signal terminal Gt, a first electrode of the write transistor T4 is electrically connected to the data signal terminal Dt, and a second electrode of the write transistor T4 is electrically connected to a first electrode of the driving transistor T3.

A control electrode of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal terminal Em, a first electrode of the first light-emitting control transistor T5 is electrically connected to the first type power supply signal terminal Vdd, and a second electrode of the first light-emitting control transistor T5 is electrically connected to the first electrode of the driving transistor T3.

A control electrode of the second light emission controlling transistor T6 is electrically connected to the light emission control signal terminal Em, a first electrode of the second light emission controlling transistor T6 is electrically connected to the second electrode of the driving transistor T3, and a second electrode of the second light emission controlling transistor T6 is electrically connected to the anode of the light emitting device 232. The cathode of the light emitting device 232 is electrically connected to the second type power supply signal terminal Vss. Wherein the voltage of the first type of power supply signal received at the first type of power supply signal terminal Vdd is greater than the voltage of the second type of power supply signal received at the second type of power supply signal terminal Vss.

A control electrode of the third reset transistor T7 is electrically connected to the scanning signal terminal Gt, a first electrode of the third reset transistor T7 is electrically connected to the initialization signal terminal Vin, and a second electrode of the third reset transistor T7 is electrically connected to an anode of the light emitting device 232.

A first plate of the capacitor Cst is electrically connected to the first-type power signal terminal Vdd, and a second plate of the capacitor Cst is electrically connected to the control electrode of the driving transistor T3.

In some examples, the second reset transistor T12, the compensation transistor T2, the driving transistor T3, the writing transistor T4, the first light emission controlling transistor T5, the second light emission controlling transistor T6, and the third reset transistor T7 may be either P-type transistors or N-type transistors. The N-type transistor is turned on when the gate receives a high voltage signal, and the P-type transistor is turned on when the gate receives a low voltage signal. It should be noted that, in the above-mentioned "high voltage signal" and "low voltage signal" are common terms, generally, the on condition of the N-type transistor is that the gate-source voltage difference is greater than the threshold voltage thereof, that is, the gate voltage of the N-type transistor is greater than the sum of the source voltage thereof and the threshold voltage thereof, the threshold voltage of the N-type transistor is a positive value, the gate voltage signal for turning on the N-type transistor is called a high voltage signal, the on condition of the P-type transistor is that the absolute value of the gate-source voltage difference is greater than the threshold voltage thereof, the threshold voltage of the P-type transistor is a negative value, that is, the gate voltage of the P-type transistor is less than the sum of the source voltage thereof and the threshold voltage thereof, the gate voltage signal for turning on the P-type transistor is called a low voltage signal, and the high voltage signal and the low voltage signal are relative to the voltage of the source.

In some examples, referring to fig. 4A, the second reset transistor T12, the compensation transistor T2, the driving transistor T3, the writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the third reset transistor T7 may all be P-type transistors, and the timing diagram of the pixel driving circuit 231 is shown in fig. 4B.

The following describes the driving process of the pixel driving circuit 231 based on the transistors in the pixel driving circuit 231 being P-type transistors.

The driving process of the pixel driving circuit 231 is: one frame period includes a reset phase t1, a data refresh and compensation phase t2, and a light emitting phase t3.

In the reset phase T1, the reset signal is low voltage, and at this time, the second reset transistor T12 is turned on, and the second reset transistor T12 transmits the initialization signal to the control electrode of the driving transistor T3, so as to reset the control electrode of the driving transistor T3 and turn on the driving transistor T3. And the compensation transistor T2, the write transistor T4, the first light emission controlling transistor T5, the second light emission controlling transistor T6, and the second reset transistor T7 are all in an off state, and the light emitting device 232 does not emit light.

In the data refresh and compensation phase T2, the reset signal received at the reset signal terminal Rst is a high voltage, and the second reset transistor T12 is turned off. And the scan signal received at the scan signal terminal Gt is a low voltage, the third reset transistor T7 is turned on under the control of the scan signal, and the initialization signal received at the initialization signal terminal Vin is written to the anode of the light emitting device 232 to reset the anode of the light emitting device 232.

Meanwhile, under the control of the scan signal, the write transistor T4 and the compensation transistor T2 are turned on, and the driving transistor T3 maintains the on state of the reset stage T1, so that the data signal received at the data signal terminal Dt can be transmitted to the control electrode of the driving transistor T3 through the write transistor T4, the driving transistor T3 and the compensation transistor T2 in sequence, so that the voltage of the control electrode of the driving transistor T3 is changed until the voltage of the control electrode of the driving transistor T3 reaches the sum of the threshold voltage of the driving transistor T3 and the voltage of the data signal, so that the driving transistor T3 is turned off.

In the data refreshing and compensating phase T2, the threshold voltage of the driving transistor T3 can be written into the control electrode of the driving transistor T3, so as to compensate the threshold voltage shift of the driving transistor T3, thereby reducing the influence on the light emitting intensity of the light emitting device 232. At this stage, the first and second light emission controlling transistors T5 and T6 are in an off state under the control of the light emission control signal.

In the light emitting period T3, the second reset transistor T12, the compensation transistor T2, the write transistor T4, and the third reset transistor T7 are turned off. The capacitor Cst fixes the voltage of the control electrode of the driving transistor T3, so that the control electrode of the driving transistor T3 is maintained at the voltage of the data refresh and compensation stage T2. At this time, the light emitting control signal is a low voltage, the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on under the control of the light emitting control signal, so that the first power signal received at the first power signal terminal Vdd is written into the first electrode of the driving transistor T3, and the driving transistor T3 is turned on, thereby forming a path between the first power signal terminal and the light emitting device 232, and enabling the light emitting device 232 to emit light.

In the pixel driving unit 400 provided in some embodiments of the present disclosure, referring to fig. 4A, the second reset transistors T12 of at least two pixel driving circuits 231 are the same transistor, so that the area of the pixel driving unit 400 can be reduced, which is beneficial to hiding the pixel driving circuits 231 in the pixel driving unit 400 under the light emitting device 232.

In some examples, the second reset transistors T12 of all the pixel driving circuits 231 in one pixel driving unit 400 are the same transistor.

In some examples, in one pixel driving unit 400, the plurality of pixel driving circuits 231 includes a first pixel driving circuit 231B, a second pixel driving circuit 231G, and a third pixel driving circuit 231R. The second reset transistor T12 of the first pixel driving circuit 231B, the second reset transistor T12 of the second pixel driving circuit 231G, and the second reset transistor T12 of the third pixel driving circuit 231R are the same transistor.

Here, the first pixel driving circuit 231B, the second pixel driving circuit 231G and the third pixel driving circuit 231R share the second reset transistor T12, and one second reset transistor T12 can simultaneously reset the control electrodes of the driving transistors T3 in the pixel driving circuits 231B, 231G and 231R.

By sharing the second reset transistor T12, the number of transistors in one pixel driving unit 400 can be reduced, and therefore, the area of the pixel driving unit 400 can be reduced, which is advantageous for hiding the pixel driving circuit 231 in the pixel driving unit 400 under the light emitting device 232.

In some examples, referring to fig. 3A, the first subpixel 230B includes a first pixel driving circuit 231B AND an anode AND-B, AND at this time, the first pixel driving circuit 231B AND the anode AND-B are electrically connected. The second sub-pixel 230G includes a second pixel driving circuit 231G AND anodes AND-G, AND at this time, the second pixel driving circuit 231G AND the anodes AND-G are electrically connected. The third subpixel 230R includes a third pixel driving circuit 231R AND an anode AND-R, AND at this time, the third pixel driving circuit 231R AND the anode AND-R are electrically connected.

In some embodiments, referring to fig. 4A, the pixel driving circuit 231 further includes a first reset transistor T11; in the same pixel driving circuit 231, the first reset transistor T11 is connected in series between the second reset transistor T12 and the control electrode of the driving transistor T3.

The control electrode of the first reset transistor T11 is electrically connected to the reset signal terminal Rst, and the first reset transistor T11 and the second reset transistor T12 are reset together as the control electrode of the driving transistor T3, so that the anti-leakage effect can be achieved.

In some examples, referring to fig. 4C to 4F, in one pixel driving unit 400, the first reset transistors T11 of at least two pixel driving circuits 231 are the same transistor.

The above-based embodiments in which the plurality of pixel driving circuits 231 includes the first pixel driving circuit 231B, the second pixel driving circuit 231G, and the third pixel driving circuit 231R. In some embodiments, referring to fig. 4C to 4F, at least two of the first reset transistor T11-B of the first pixel driving circuit 231B, the first reset transistor T11-G of the second pixel driving circuit 231G, and the first reset transistor T11-R of the third pixel driving circuit 231R are the same transistor.

In some examples, referring to fig. 4C, the first reset transistor T11-B of the first pixel driving circuit 231B and the first reset transistor T11-G of the second pixel driving circuit 231G are the same transistor.

In some examples, referring to fig. 4D, the first reset transistor T11-B of the first pixel driving circuit 231B and the first reset transistor T11-R of the third pixel driving circuit 231R are the same transistor.

In some examples, referring to fig. 4E, the first reset transistors T11-G of the second pixel driving circuit 231G and the first reset transistors T11-R of the third pixel driving circuit 231R are the same transistors.

In some examples, referring to fig. 4F, in one pixel driving unit 400, the first reset transistors T11 of the plurality of pixel driving circuits 231 (i.e., all of the pixel driving circuits 231) are the same transistor. Based on the above embodiment in which the plurality of pixel driving circuits 231 includes the first pixel driving circuit 231B, the second pixel driving circuit 231G, and the third pixel driving circuit 231R, at this time, the first reset transistors T11-B of the first pixel driving circuit 231B, the first reset transistors T11-G of the second pixel driving circuit 231G, and the first reset transistors T11-R of the third pixel driving circuit 231R are the same transistors.

By making at least two of the plurality of pixel driving circuits 231 in one pixel driving unit 400 share the first reset transistor T11, the number of transistors in one pixel driving unit 400 can be reduced, thereby reducing the area of the pixel driving circuit 231 in the pixel driving unit 400, which is beneficial to hiding the pixel driving circuit 231 in the pixel driving unit 400 under the light emitting device 232.

In addition, in some other embodiments, referring to fig. 4A, the first reset transistors T11-B of the first pixel driving circuit 231B, the first reset transistors T11-G of the second pixel driving circuit 231G, and the first reset transistors T11-R of the third pixel driving circuit 231R are all different transistors.

By providing a first reset transistor T11 for each pixel driving circuit 231, the control electrode of the driving transistor T3 is reset by the different first reset transistors T11 in the different pixel driving circuits 231, so that the reset effect on the control electrode of the driving transistor T3 can be ensured.

Some embodiments of the present disclosure provide a display device 100 including: the pixel driving unit 400 provided in any of the above embodiments. Therefore, the display device 100 provided in some embodiments of the present disclosure has all the advantages of the pixel driving unit 400 provided in any one of the above embodiments, and details thereof are not repeated herein.

Some embodiments of the present disclosure further provide a display panel 200, referring to fig. 5A, in the display panel 200, an orthographic projection of the first reset transistor T11-G in the second sub-pixel 230G and/or the first reset transistor T11-R in the third sub-pixel 230R on the substrate 210 is located within an orthographic projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210.

It should be noted that, in the case where the area of the light emitting device 232 is the area of the anode AND1, the orthographic projection of the light emitting device 232 on the substrate 210 coincides with the orthographic projection of the anode AND1 on the substrate 210. In the case where the area of the light-emitting device 232 is the area of the light-emitting layer EL, the orthographic projection of the light-emitting device 232 on the substrate 210 coincides with the orthographic projection of the light-emitting layer EL on the substrate 210. In the case where the area of the light emitting device 232 is the area of the cathode CTD1, the orthographic projection of the light emitting device 232 on the substrate 210 coincides with the orthographic projection of the cathode CTD1 on the substrate 210.

In some examples, in one first pixel unit 220, the area of the light emitting device 232 of the first sub-pixel 230B is the largest, and the area of the light emitting device 232 of the second sub-pixel 230G and the area of the light emitting device 232 of the third sub-pixel 230R are both relatively smaller, and hiding the first reset transistor T11-G in the second sub-pixel 230G and/or the first reset transistor T11-R in the third sub-pixel 230R under the light emitting device 232 of the first sub-pixel 230B may not only shield the first reset transistor T11-G in the second sub-pixel 230G and/or the first reset transistor T11-R in the third sub-pixel 230R. Moreover, since the area of the light emitting device 232 of the first sub-pixel 230B is large, the structure of the pixel driving circuit 231 under the light emitting device 232 of the first sub-pixel 230B is not too compact, and the space under the light emitting device 232 of the first sub-pixel 230B is reasonably utilized.

In some examples, the orthographic projection of the first reset transistors T11-G in the second sub-pixel 230G on the substrate 210 may only be made to be within the orthographic projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210. In one first pixel unit 220, the area of the light emitting device 232 of the second sub-pixel 230G is smaller, and the first reset transistors T11-G in the second sub-pixel 230G are disposed under the light emitting device 232 of the first sub-pixel 230B, so that the number of transistors in the pixel driving circuit 231 under the light emitting device 232 of the second sub-pixel 230G can be reduced, the area of the pixel driving circuit 231 under the light emitting device 232 of the second sub-pixel 230G can be reduced, and the light emitting device 232 of the second sub-pixel 230G can shield the pixel driving circuit 231 under the light emitting device 232.

In other examples, only the orthographic projection of the first reset transistor T11-R in the third sub-pixel 230R on the substrate 210 may be made to be within the orthographic projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210. By disposing the first reset transistors T11-R in the third sub-pixel 230R under the light emitting device 232 of the first sub-pixel 230B, the number of transistors in the pixel driving circuit 231 under the light emitting device 232 of the third sub-pixel 230R can be reduced, and the area of the pixel driving circuit 231 under the light emitting device 232 of the third sub-pixel 230R can be reduced, which is beneficial for the light emitting device 232 of the third sub-pixel 230R to shield the pixel driving circuit 231 under it.

In other embodiments, referring to FIG. 5A, the first reset transistor T11-B of the first sub-pixel 230B, the first reset transistor T11-G of the second sub-pixel 230G, and the first reset transistor T11-R of the third sub-pixel 230R are all located within the front projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210.

The first reset transistors T11-G of the second sub-pixel 230G and the first reset transistors T11-R of the third sub-pixel 230R are disposed under the light emitting device 232 of the first sub-pixel 230B, so that the area of the pixel driving circuit 231 under the light emitting device 232 of the second sub-pixel 230G and the area of the pixel driving circuit 231 under the light emitting device 232 of the third sub-pixel 230R can be reduced, which is beneficial to shielding the pixel driving circuit 231 in the second sub-pixel 230G and the pixel driving circuit 231 in the third sub-pixel 230R and reducing diffraction phenomena. And the first reset transistor T11-B of the first sub-pixel 230B is located under the light emitting device 232 disposed at the first sub-pixel 230B, so as to prevent the first reset transistor T11-B from occupying other space, thereby improving light transmittance.

In some embodiments, referring to fig. 4C to 4F, at least two of the first reset transistor T11-B of the first sub-pixel 230B, the first reset transistor T11-G of the second sub-pixel 230G, and the first reset transistor T11-R of the third sub-pixel 230R are the same transistor.

In one first pixel unit 220, the first reset transistors T11 of at least two sub-pixels 230 are the same transistor, so that the number of the first reset transistors T11 in the first pixel unit 220 can be reduced. When the first reset transistor T11-B of the first sub-pixel 230B, the first reset transistor T11-G of the second sub-pixel 230G, and the first reset transistor T11-R of the third sub-pixel 230R are all disposed under the light emitting device 232 of the first sub-pixel 230B, the area of the pixel driving circuit 231 under the light emitting device 232 of the first sub-pixel 230B can be reduced by reducing the number of the first reset transistors T11, and thus the area of the light emitting device 232 of the first sub-pixel 230B can be reduced, and the light transmittance of the first display area A1 is improved.

In some examples, the material of the anode AND1 includes a transparent conductive oxide material such as ITO, IZO, AND a metal material such as Au, ag, ni, pt. For example, the anode layer AND may include a stacked composite structure of a transparent conductive oxide, a metal AND a transparent conductive oxide, which may be referred to as a transparent conductive oxide/metal/transparent conductive oxide, for example, the anode layer AND may have a structure of: ITO/Ag/ITO. The anode AND1 has poor light transmittance or no light transmittance.

In some embodiments, referring to FIG. 5A, the orthographic projection of the first reset transistor T11-G of the second sub-pixel 230G AND/or the first reset transistor T11-R of the third sub-pixel 230R on the substrate 210 is within the orthographic projection of the anode AND-B of the first sub-pixel 230B on the substrate 210. Here, it should be noted that, at this time, the areas of the light emitting device 232 AND the anode AND1 may be equal or different, AND it is also understood that the orthographic projection of the light emitting device 232 on the substrate 210 may be completely or partially overlapped with the orthographic projection of the anode AND1 on the substrate 210.

The anode AND1 has poor or opaque light transmittance, so that the anode AND1 can shield the pixel driving circuit 231 AND the signal line, etc. under the anode AND1, thereby reducing the exposure of the pixel driving circuit 231 AND the signal line, reducing the diffraction of the sensor 300 when photographing through the first display area A1, AND increasing the light transmittance of the first display area A1.

In some examples, the orthographic projection of the first reset transistor T11-B in the first sub-pixel 230B, the first reset transistor T11-G in the second sub-pixel 230G, AND the first reset transistor T11-R in the third sub-pixel 230R on the substrate 210 are all located within the orthographic projection of the anode AND-B of the first sub-pixel 230B on the substrate 210.

In some embodiments, referring to fig. 5A and 5B, the display panel 200 further includes a reset signal line RST and an initialization signal line VIN.

Referring to fig. 5A, the pixel driving circuit 231 further includes a second reset transistor T12, and the second reset transistor T12 is connected in series with any of the first reset transistors T11. As shown in fig. 5B, the control electrode of each of the first reset transistor T11 and the second reset transistor T12 is electrically connected to a reset signal line RST; a first pole of the second reset transistor T12 is electrically connected to the initialization signal line VIN, and a second pole of the second reset transistor T12 is electrically connected to a first pole of each of the first reset transistors T11. The pixel driving circuit 231 further includes: and a driving transistor T3, and a control electrode of the driving transistor T3 of each pixel driving circuit 231 is electrically connected to a second electrode of each first reset transistor T11.

The reset signal line RST is used for transmitting a reset signal, and the initialization signal line VIN is used for transmitting an initialization signal. In a case where the first reset transistor T11 and the second reset transistor T12 are both P-type transistors, when the reset signal is a low voltage signal, the first reset transistor T11 and the second reset transistor T12 are turned on, and the first reset transistor T11 and the second reset transistor T12 may transmit the initialization signal to the control electrode of the driving transistor T3, so as to reset the control electrode of the driving transistor T3. The control electrode of the driving transistor T3 is reset by the two transistors, so that the effect of preventing current leakage can be achieved.

In some embodiments, referring to fig. 5A, the second reset transistor T12 of the first sub-pixel 230B, the second reset transistor T12 of the second sub-pixel 230G, and the second reset transistor T12 of the third sub-pixel 230R are the same transistor; the orthographic projection of the second reset transistor T12 on the substrate 210 is located within the orthographic projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210.

As shown in fig. 5A, the second reset transistor T12 of the first sub-pixel 230B, the second reset transistor T12 of the second sub-pixel 230G, and the second reset transistor T12 of the third sub-pixel 230R are the same transistor, which can reduce the number of transistors under the light emitting device 232 of the first sub-pixel 230B, so as to reduce the area of the pixel driving circuit 231 under the light emitting device 232 of the first sub-pixel 230B, which is beneficial for the light emitting device 232 of the first sub-pixel 230B to shield the pixel driving circuit 231 under the light emitting device 232, thereby avoiding the exposure of the pixel driving circuit 231 and reducing the diffraction phenomenon.

Meanwhile, in the case where the number of transistors under the light emitting device 232 of the first subpixel 230B is small, the area of the light emitting device 232 of the first subpixel 230B may be reduced, and thus the light transmittance may be increased.

In other examples, referring to fig. 5A, the orthographic projection of the second reset transistor T12 on the substrate 210 is within the orthographic projection of the anode AND-B of the first sub-pixel 230B on the substrate 210. The anode AND-B of the first sub-pixel 230B is opaque, so that the shielding effect of the second reset transistor T12 is good, AND the diffraction phenomenon of the sensor 300 when the sensor photographs through the first display area A1 is reduced.

In some embodiments, referring to fig. 5C, the light emitting devices 232 of the second sub-pixel 230G and the light emitting devices 232 of the third sub-pixel 230R are spaced along the column direction Y. The direction indicated by the arrow Y is the column direction Y. The light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R are sequentially disposed in the column direction Y, and thus the light emitting devices 232 of the second sub-pixel 230G and the light emitting devices 232 of the third sub-pixel 230R in one column of the first pixel unit 220 may be aligned in one column. The light emitting devices 232 of the first sub-pixels 230B in a column of the first pixel unit 220 may be arranged in a column. Referring to fig. 5B and 5C, the light emitting device 232 of the first sub-pixel 230B is located in a column adjacent to the columns of the light emitting devices 232 of the second sub-pixel 230G and the third sub-pixel 230R; and the light emitting device 232 of the first sub-pixel 230B crosses the gap region between the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R.

Please refer to fig. 5B and 5C, a direction indicated by an arrow X is a row direction X, and in some examples, the row direction X is perpendicular to the column direction Y. The light emitting devices 232 of the third sub-pixels 230R in a row of the first pixel unit 220 may be arranged in a row. The light emitting devices 232 of the second sub-pixels 230G in a row of the first pixel unit 220 may be arranged in a row. The light emitting devices 232 of the first sub-pixels 230B in a row of the first pixel unit 220 may be arranged in a row. And the gap region between the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R refers to a gap region between the light emitting device 232 of the adjacent row of the third sub-pixel 230R and the light emitting device 232 of the row of the second sub-pixel 230G.

The light emitting device 232 of the first sub-pixel 230B spans the gap region between the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R, and it can be understood that the projection of the light emitting device 232 of the first sub-pixel 230B in the row direction X overlaps with the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R.

The arrangement of the sub-pixels 230 disclosed in some embodiments above may be referred to as "REAL pixel arrangement", and by using the REAL pixel arrangement, in the case that the PPI (pixel per inch) of the display panel 200 is low (for example, lower than 400), the graininess may be reduced, and the display effect may be improved. The display panel 200 described above may be applied to a watch device.

In some embodiments, referring to fig. 5A, the pixel driving circuit 231 further includes a circuit body 2311. Illustratively, the circuit body 2311 of each sub-pixel 230 includes a compensation transistor T2, a driving transistor T3, a writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a third reset transistor T7, and a capacitor Cst.

The orthographic projection of the circuit bodies 2311-B of the first sub-pixel 230B on the substrate 210 is within the orthographic projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210, the orthographic projection of the circuit bodies 2311-G of the second sub-pixel 230G on the substrate 210 is within the orthographic projection of the light-emitting device 232 of the second sub-pixel 230G on the substrate 210, and the orthographic projection of the circuit bodies 2311-R of the third sub-pixel 230R on the substrate 210 is within the orthographic projection of the light-emitting device 232 of the third sub-pixel 230R on the substrate 210.

In one sub-pixel 230, the circuit body 2311 electrically connected thereto is shielded by the light emitting device 232, thereby preventing the circuit body 2311 from being exposed to the outside of the light emitting device 232 and reducing diffraction. Meanwhile, the light transmittance of the first display area A1 may also be improved.

In other examples, referring to fig. 5A, the orthographic projection of the circuit body 231 of each sub-pixel 230 on the substrate 210 is located within the orthographic projection of the anode AND1 of the sub-pixel 230B on the substrate 210. Illustratively, the orthographic projection of the circuit body 2311-B of the first subpixel 230B on the substrate 210 is within the orthographic projection of the anode AND-B of the first subpixel 230B on the substrate 210, the orthographic projection of the circuit body 2311-G of the second subpixel 230G on the substrate 210 is within the orthographic projection of the anode AND-G of the second subpixel 230G on the substrate 210, AND the orthographic projection of the circuit body 2311-R of the third subpixel 230R on the substrate 210 is within the orthographic projection of the anode AND-R of the third subpixel 230R on the substrate 210. The anode AND1 of the sub-pixel 230B is opaque, so that the shielding effect of the sub-pixel on each circuit body 23112 is good, AND the diffraction phenomenon of the sensor 300 when the sensor photographs through the first display area A1 is reduced.

In some examples, referring to fig. 5A, the direction of the second sub-pixel 230G pointing to the third sub-pixel 230 is a second designated direction C2, the direction indicated by the arrow C2 is the second designated direction C2, and the second designated direction C2 is parallel to the column direction Y.

In some embodiments, referring to fig. 5D, in the row of the first pixel units 220, the second reset transistor T12 and the first reset transistors T11 are located at a side of the circuit body 2311-R of the third sub-pixel 230R away from the row of the light emitting device 232 of the second sub-pixel 230G, and at this time, a direction in which the circuit body 2311-R of the third sub-pixel 230R points to the second reset transistor T12 and the first reset transistors T11 is the second specified direction C2.

In some embodiments, referring to FIG. 5D, the second reset transistor T12, the first reset transistors T11-R of the third sub-pixel 230R, and the first reset transistors T11-G of the second sub-pixel 230G are located on a side of the first reset transistors T11-B of the first sub-pixel 230B near the circuit bodies 2311-R of the third sub-pixel 230R, and are sequentially away from the circuit bodies 2311-R of the third sub-pixel 230R.

In some examples, in one first pixel unit 220, a direction in which the third sub-pixel 230R points to the first sub-pixel 230B is a first designated direction C1, a direction indicated by an arrow C1 is the first designated direction C1, and the first designated direction C1 is parallel to the row direction X.

The second reset transistor T12, the first reset transistor T11-R of the third sub-pixel 230R, the first reset transistor T11-G of the second sub-pixel 230G, and the first reset transistor T11-B of the first sub-pixel 230B are sequentially disposed along the first designated direction C1, so that the first reset transistor T11-R of the third sub-pixel 230R and the driving transistor T3 of the third sub-pixel 230R can be conveniently and electrically connected, and the first reset transistor T11-G of the second sub-pixel 230G and the driving transistor T3 of the second sub-pixel 230G can be conveniently and electrically connected.

In some embodiments, referring to fig. 5B and 5C, the reset signal lines RST extend along the row direction X, and one reset signal line RST is electrically connected to the control electrodes of the second reset transistors T12 and the control electrodes of the first reset transistors T11 in one row of the first pixel units 220. Here, the second reset transistor T12 is not shown in fig. 5B and 5C, and refer to fig. 5A.

The pattern of the reset signal line RST may be a straight line pattern or an approximately straight line pattern, and the "extending of the reset signal line RST in the row direction X" means a tendency of the main body pattern of the reset signal line RST to extend in a certain row direction X.

The second reset transistor T12 in the first pixel unit 220, the first reset transistor T11-B of the first sub-pixel 230B, the first reset transistor T11-G of the second sub-pixel 230G, and the first reset transistor T11-R of the third sub-pixel 230R in one row receive the same reset signal. Therefore, the control electrodes of the driving transistors T3 in the respective sub-pixels 230 in one row of the first pixel unit 220 are simultaneously reset.

Referring to fig. 5B, the initialization signal lines VIN extend along the row direction X, and one initialization signal line VIN is electrically connected to the first poles of the second reset transistors T12 in one row of the first pixel units 220. In fig. 5B, the second reset crystal T12 is not shown, and fig. 5A may be referred to.

The pattern of the initialization signal line VIN may be a straight line pattern or an approximate straight line pattern, and the "extending along the row direction X" of the initialization signal line VIN refers to a tendency that the main body pattern of the initialization signal line VIN extends along a certain row direction X.

The initialization signal line VIN is used for transmitting an initialization signal, and the initialization signal is transmitted to each first reset transistor T11 through the second reset transistor T12, and further transmitted to the control electrode of the driving transistor T3 of each sub-pixel 230, so as to reset the control electrode of the driving transistor T3.

Referring to fig. 5A, the orthographic projection of the second reset transistor T12 and each of the first reset transistors T11 on the substrate 210 is located between the orthographic projection of the initialization signal line VIN electrically connected to the second reset transistor T12 on the substrate 210 and the orthographic projection of the circuit main bodies 2311-R of the third sub-pixels 230R on the substrate 210; the orthographic projection of the reset signal line RST on the substrate 210 is located between the orthographic projection of the strip of initialization signal line VIN on the substrate 210 and the orthographic projection of the circuit bodies 2311-G of the third sub-pixel 230R on the substrate 210.

For convenience of description, the second reset transistor T12 and each of the first reset transistors T11 are defined as a first-type reset transistor.

Referring to FIG. 5A, the circuit bodies 2311-R, the first type reset transistors and the initialization signal line VIN of the third sub-pixel 230R are sequentially arranged along a second designated direction C2.

In the row of the first pixel unit 220, the second reset transistor T12 and the control electrode of each of the first reset transistors T11 are located on the reset signal line RST.

The position of the control electrode of the first reset transistor T11 in combination with the plurality of film layers in the display panel 200 will be described below.

In some examples, referring to fig. 5D, the display panel 200 includes an active film layer 240 and a first Gate metal layer Gate1 disposed on one side of the substrate 210, the active film layer 240 and the first Gate metal layer Gate1 are both located between the substrate 210 and the light emitting device 232, and the first Gate metal layer Gate1 is located on one side of the active film layer 240 away from the substrate 210. In some examples, a first Gate insulating layer is disposed between the active film layer 240 and the first Gate metal layer Gate1.

The active film layer 240 includes active layers of transistors in the pixel driving circuit 231, wherein the active layers of the transistors include a first electrode region, a second electrode region, and a channel region connecting the first electrode region and the second electrode region.

For example, referring to fig. 6A, the active layer 240 includes an active layer T12-P of the second reset transistor T12 and an active layer T11-P of each first reset transistor T11.

Referring to fig. 6A, the active layers T12-P of the second reset transistors T12 extend in the row direction X, and the active layers T11-P of the first reset transistors T11 extend in the column direction Y. One end of the active layer T12-P of the second reset transistor T12, which is remote from the circuit body 2311-R of the third sub-pixel 230R, is connected to one end of the active layer T11-P of each first reset transistor T11, which is remote from the circuit body 2311-B of the first sub-pixel 230B.

Wherein the active layers T11-RP of the first reset transistors T11-R of the third sub-pixel 230R, the active layers T11-GP of the first reset transistors T11-G of the second sub-pixel 230G, and the active layers T11-BP of the first reset transistors T11-B of the first sub-pixel 230B are sequentially disposed along the first designated direction C1.

Referring to fig. 6B, the first Gate metal layer Gate1 includes a reset signal line RST. The reset signal line RST is located on a side of the active film layer 240 away from the substrate 210. Referring to fig. 5D, the overlapping portions of the reset signal line RST, the active layers T12-P of the second reset transistor T12 and the active layers T11-P of the first reset transistors T11 are multiplexed into the control electrode of the second reset transistor T12 and the control electrode of the first reset transistors T11.

In some embodiments, referring to fig. 2B, the substrate 210 includes a first display area A1, and a plurality of first pixel units 220 are located in the first display area A1; the display panel 200 further includes: and a plurality of signal lines between the substrate 210 and the light emitting device 232. Note that the first display region A1 in the substrate 210 is the same region as the first display region A1 in the display panel 200. In fig. 2B, the light emitting device 232 is not shown, and fig. 3A, fig. 5B and the like can be referred to.

Referring to fig. 5B, a portion of the at least one signal line in the first display area A1 includes a metal trace 250 and a transparent connection trace 260 electrically connected to each other. An orthographic projection of at least a portion of the metal traces 250 on the substrate 210 is located within an orthographic projection of the light emitting device 232 on the substrate 210. Illustratively, referring to fig. 5C, the plurality of signal lines in the display panel 200 include a reset signal line RST, a scan signal line GT, a light emission control signal line EM, an initialization signal line VIN, a first power signal line VDD1, and a second power signal line VDD2.

In some examples, the orthographic projection of all of the metal traces 250 on the substrate 210 is within the orthographic projection of the light emitting device 232 on the substrate 210.

In other examples, referring to fig. 5B, an orthographic projection of a portion of the metal trace 250 on the substrate 210 is located inside an orthographic projection of the light emitting device 232 on the substrate 210, and an orthographic projection of the remaining portion of the metal trace 250 on the substrate 210 is located outside the orthographic projection of the light emitting device 232 on the substrate 210.

For example, referring to fig. 5A and 5B, a metal connection portion 2501 is disposed at an end of the metal trace 250. Referring to fig. 5B, a transparent connection portion 2601 is disposed at an end of the transparent connection trace 260, and an orthogonal projection of the metal connection portion 2501 on the substrate 210 at least partially coincides with an orthogonal projection of the transparent connection portion 2601 on the substrate 210. Wherein, in some examples, an orthographic projection of metal connection 2501 on substrate 210 is at least partially within an orthographic projection of light-emitting device 232 on substrate 210. In other examples, the orthographic projection of metal connection 2501 on substrate 210 is entirely outside the orthographic projection of light-emitting device 232 on substrate 210.

The metal traces 250 in one signal line can be connected by a transparent connection trace 260, at least a portion of the transparent connection trace 260 is exposed outside the light emitting device 232, and the transparent connection trace 260 is a transparent trace and is light-permeable. Therefore, the transparent connection trace 260 is connected to the metal trace 250, so that the light transmittance of the first display area A1 can be improved.

In other examples, referring to fig. 5B, an orthographic projection of at least a portion of the metal trace 250 on the substrate 210 is located within an orthographic projection of the anode AND1 of the sub-pixel 230 on the substrate 210.

The reset signal line RST, the scanning signal line GT, the emission control signal line EM, the initialization signal line VIN, the first power signal line VDD1, and the second power signal line VDD2 will be described in sequence below.

In some embodiments, referring to fig. 7A, the display panel 200 includes: and a first transparent wiring layer 271, wherein the first transparent wiring layer 271 is positioned between the substrate 210 and the light emitting device 232, and the first transparent wiring layer 271 is positioned at one side of the first Gate metal layer Gate1, which is far away from the substrate 210.

In some examples, the material of the first Gate metal layer Gate1 is a metal, such as Al, ag, cu, cr, or the like. The material of the first transparent routing layer 271 is a transparent conductive oxide material, such as ITO, IZO, etc.

Referring to fig. 7B, at least one signal line includes a reset signal line RST. The reset signal line RST includes a metal trace 251 and a transparent connection trace 261. The metal trace 251 of the reset signal line RST is located on the first Gate metal layer Gate1, and at least a portion of an orthographic projection of the metal trace 251 of the reset signal line RST on the substrate 210 is located within an orthographic projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210. In fig. 7B, the light emitting device 232 of the first sub-pixel 230B is not shown, and refer to fig. 5B.

One reset signal line RST includes a plurality of metal traces 251, and at least a portion of one metal trace 251 is located under the light emitting device 232 of the first sub-pixel 230B. In some examples, all of the metal trace 251 is located under the light emitting device 232 of one first sub-pixel 230B. In other examples, a portion of one of the metal traces 251 is located under the light emitting device 232 of one of the first sub-pixels 230B.

Referring to fig. 6B, the metal trace 251 in the reset signal line RST includes a main trace segment 2511 and a connection trace segment 2512, the main trace segment 2511 extends along the row direction X, and the main trace segment 2511 overlaps the active layer T11-P of each first reset transistor T11 on the substrate 210, wherein the gate of the first reset transistor T11 is located on the main trace segment 2511. And the connection trace segment 2512 extends in the column direction Y and overlaps the active layer T12-P of the second reset transistor T12. The portion of the connecting line segment 2512 overlapping the active layer T12-P of the second reset transistor T12 is the gate of the second reset transistor T12, i.e., the gate of the second reset transistor T12 is located on the connecting line segment 2512. In fig. 6B, the active layer T12-P of the second reset transistor T12 is not shown, as can be seen from fig. 5D and 6A.

Referring to fig. 7B, the transparent connecting trace 261 of the reset signal line RST is located on the first transparent trace layer 271, and the transparent connecting trace 261 of the reset signal line RST is connected to the metal trace 251 of the reset signal line RST through a via.

The orthographic projection of the transparent connection trace 261 of the reset signal line RST on the substrate 210 is located outside the orthographic projection of the light emitting device 232 of the second sub-pixel 230G on the substrate 210, and is located outside the orthographic projection of the light emitting device 232 of the third sub-pixel 230R on the substrate 210. Therefore, the transparent connection wire 261 of the reset signal line RST does not occupy the space under the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R, so that the areas of the light emitting device 232 of the second sub-pixel 230G and the pixel driving circuit 231 under the light emitting device 232 of the third sub-pixel 230R are increased, and the phenomenon that the light emitting device 232 of the second sub-pixel 230G and the pixel driving circuit 231 under the light emitting device 232 of the third sub-pixel 230R are coupled due to too compact structures is avoided. In fig. 7B, the light emitting device 232 of the third sub-pixel 230R is not shown, and reference may be made to fig. 5A and 5B.

In other examples, referring to fig. 7B, at least a portion of the orthographic projection of the metal trace 251 of the reset signal line RST on the substrate 210 is located within the orthographic projection of the anode AND-B of the first sub-pixel 230B on the substrate 210. The orthographic projection of the transparent connection wire 261 of the reset signal wire RST on the substrate 210 is located outside the orthographic projection of the anode AND-G of the second sub-pixel 230G on the substrate 210, AND outside the orthographic projection of the anode AND-R of the third sub-pixel 230R on the substrate 210. In fig. 7B, the anode AND1 of each sub-pixel 230 is not shown, AND refer to fig. 5B.

In some embodiments, referring to fig. 5D, the circuit body 2311 of the pixel driving circuit 231 includes a writing transistor T4, a compensating transistor T2 and a third resetting transistor T7.

The at least one signal line further includes a scanning signal line GT, and one scanning signal line GT is electrically connected to the control electrodes of the write transistors T4, the compensation transistor T2, and the third reset transistor T7 of all the sub-pixels 230 in one row of the first pixel units 220.

The scan signal line GT is used to transmit a scan signal, and all the sub-pixels 230 in the first pixel unit 220 in one row receive the same scan signal. The write transistor T4, the compensation transistor T2, and the third reset transistor T7 in the first pixel unit 220 of one row are simultaneously turned on.

Referring to fig. 7B, the metal trace 252 of the scanning signal line GT is located on the first Gate metal layer Gate1, and at least a portion of an orthogonal projection of the metal trace 252 of the scanning signal line GT on the substrate 210 is located within an orthogonal projection of the light emitting device 232 on the substrate 210. The transparent connecting trace 262 of the scanning signal line GT is located on the first transparent trace layer 271, and the transparent connecting trace 262 of the scanning signal line GT is connected with the metal trace 252 of the scanning signal line GT through a via hole.

Referring to fig. 7B, the scan signal line GT includes a plurality of metal traces 252, and an orthogonal projection of one metal trace 252 on the substrate 210 is at least partially located within an orthogonal projection of one light emitting device 232 on the substrate 210. In some examples, all of each of the metal traces 252 is disposed under the light emitting device 232. In other examples, a portion of each of the metal traces 252 is disposed under the light emitting device 232.

In other examples, referring to fig. 7B, at least a portion of the orthographic projection of the metal trace 252 of the scan signal line GT on the substrate 210 is located within the orthographic projection of the anode AND1 of the sub-pixel 230 on the substrate 210.

In some examples, referring to fig. 5D, a section of metal trace 252 in the scan signal line GT is electrically connected to the control electrode of the write transistor T4, the control electrode of the compensation transistor T2 and the control electrode of the third reset transistor T7 in one sub-pixel 230.

In some examples, referring to fig. 6A, the active film 240 includes an active layer T4-P of the write transistor T4, an active layer T2-P of the compensation transistor T2, and an active layer T7-P of the third reset transistor T7.

Referring to fig. 5D, the overlapping portion of a metal trace 252 and the active layer T4-P of the write transistor T4 is multiplexed as the control electrode of the write transistor T4. The overlapping portion of a segment of metal trace 252 and the active layer T2-P of the compensation transistor T2 is multiplexed as the gate of the compensation transistor T2. The overlapping portion of one metal trace 252 and the active layer T7-P of the third reset transistor T7 is multiplexed as the control electrode of the third reset transistor T7. That is, the control electrode of the writing transistor T4, the control electrode of the compensating transistor T2, and the control electrode of the third resetting transistor T7 in one sub-pixel 230 are located on one metal trace 252.

In some examples, referring to fig. 4A and 5D, the compensation transistor T2 of each sub-pixel 230 includes a first compensation transistor T21 and a second compensation transistor T22. Wherein the first compensation transistor T21 and the second compensation transistor T22 are connected in series.

A control electrode of the first compensation transistor T21 is electrically connected to the scanning signal line GT, a first electrode of the first compensation transistor T21 is electrically connected to a second electrode of the driving transistor T3 and a first electrode of the second emission control transistor T6, and a second electrode of the first compensation transistor T21 is electrically connected to a first electrode of the second compensation transistor T22.

A control electrode of the second compensation transistor T22 is electrically connected to the scan signal line GT, and a second electrode of the second compensation transistor T22 is electrically connected to a second electrode of the first reset transistor T11 and a control electrode of the driving transistor T3.

By providing the compensation transistor T2 as the first compensation transistor T21 and the second compensation transistor T22 connected in series, an anti-leakage effect can be achieved.

Based on the example that the compensation transistor T2 includes the first compensation transistor T21 and the second compensation transistor T22, referring to fig. 6B, the metal trace 252 of the scan signal line GT includes a main trace segment 2521 and a connection trace segment 2522. The main body trace segment 2521 extends along the row direction X, the connection trace segment 2522 extends along the column direction, and one end of the connection trace segment 2522 is connected to the main body trace segment 2521. The overlapped portion of the active layer T2-P connecting the line segment 2522 and the compensation transistor T2 is multiplexed as the control electrode of the second compensation transistor T22. The overlapping reset of the body trace segment 2521 and the active layers T4-P of the write transistor T4, the compensation transistor T2, and the third reset transistor T7 is multiplexed into the control electrode of the write transistor T4, the first compensation transistor T21, and the third reset transistor T7, respectively. In fig. 6B, active layers of the transistors are not shown, and refer to fig. 5D and 6A.

In some examples, referring to fig. 7C, one scan signal line GT includes multiple metal traces 252 and multiple transparent connecting traces 262. The plurality of metal traces 252 include a first metal trace 252A, a second metal trace 252B, and a third metal trace 252C. In fig. 7C, the metal trace 252 and the multi-segment transparent connecting trace 262 are not shown, and refer to fig. 7B.

Wherein, the orthographic projection of the first segment of metal trace 252A on the substrate 210 is at least partially located within the orthographic projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210.

The orthographic projection of the second metal trace 252B on the substrate 210 is at least partially located within the orthographic projection of the light-emitting device 232 of the second sub-pixel 230G on the substrate 210.

The orthographic projection of the third segment of metal wiring 252C on the substrate 210 is at least partially located within the orthographic projection of the light emitting device 232 of the third sub-pixel 230R on the substrate 210.

In some examples, referring to fig. 7C, the display panel 200 further includes a second transparent wiring layer 272. The second transparent routing layer 272 is located on a side of the first transparent routing layer 271 facing away from the substrate 210, or a side facing the substrate 210.

The plurality of transparent connection traces 262 in one scanning signal line GT include a first transparent connection trace 262A, a second transparent connection trace 262B, a third transparent connection trace 262C, and a fourth transparent connection trace 262D. The first transparent connecting trace 262A, the second transparent connecting trace 262B and the third transparent connecting trace 262C are disposed on the first transparent trace layer 271. And the fourth transparent connecting trace 262D is located on the second transparent trace layer 272.

The first metal trace 252A electrically connected to the first sub-pixel 230B in each first pixel unit 220 is electrically connected to the third metal trace 252C electrically connected to the third sub-pixel 230R through the first transparent connecting trace 262A.

The first metal trace 252A electrically connected to the first sub-pixel 230B in one first pixel unit 220 is electrically connected to the third metal trace 252C electrically connected to the third sub-pixel 230R in the first pixel unit 220 adjacent to the first pixel unit 220 in the row direction X through the second transparent connection trace 262B.

One end of the third transparent connecting trace 262C is electrically connected to one end of the second metal trace 252B far away from the first sub-pixel 230B, the other end is electrically connected to the fourth transparent connecting trace 262D, and one end of the fourth transparent connecting trace 262D far away from the third transparent connecting trace 262C is electrically connected to the second transparent connecting trace 262B.

In some embodiments, referring to fig. 5D, the circuit body 2311 of the pixel driving circuit 231 further includes a first light-emitting control transistor T5 and a second light-emitting control transistor T6. The at least one signal line further includes an emission control signal line EM electrically connected to the control electrodes of the first and second emission control transistors T5 and T6 of all the sub-pixels 230 in one row of the first pixel unit 220.

The emission control signal line EM is used for transmitting an emission control signal, and all the sub-pixels 230 in the first pixel unit 220 in one row receive the same emission control signal. The first and second light emission controlling transistors T5 and T6 in the first pixel unit 220 of one row are simultaneously turned on.

Referring to fig. 7B and 7C, the metal trace 253 of the emission control signal line EM is located on the first Gate metal layer Gate1. At least a part of the orthographic projection of the metal wiring 253 of the light emission control signal line EM on the substrate 210 is located within the orthographic projection of the light emitting device 232 on the substrate 210. The transparent connection wire 263 of the light emitting control signal line EM is located on the first transparent wire layer 271, and the transparent connection wire 263 of the light emitting control signal line EM is connected with the metal wire 253 of the light emitting control signal line EM through a via hole. In fig. 7B and 7C, the light emitting device 232 is not shown, and fig. 5A can be referred to.

In some other examples, referring to fig. 5A, at least a portion of the orthogonal projection of the metal trace 253 of the light-emitting control signal line EM on the substrate 210 is located within the orthogonal projection of the anode AND1 of the sub-pixel 230 on the substrate 210.

Referring to fig. 7B and 7C, the emission control signal line EM includes a plurality of metal traces 253, and an orthogonal projection of one metal trace 253 on the substrate 210 is at least partially located within an orthogonal projection of one light emitting device 232 on the substrate 210. In some examples, all of each metal trace 253 is disposed under the light emitting device 232. In other examples, a portion of each metal trace 253 is disposed under the light emitting device 232.

In some examples, referring to fig. 5A, a metal trace 253 in the emission control signal line EM is electrically connected to the control electrode of the first emission control transistor T5 and the control electrode of the second emission control transistor T6 in one sub-pixel 230.

In some examples, referring to fig. 6A, the active film layer 240 includes an active layer T5-P of the first light emission control transistor T5 and an active layer T6-P of the second light emission control transistor T6.

Referring to fig. 5D, the overlapped portion of the metal trace 253 and the active layer T5-P of the first light-emitting control transistor T5 is reused as the control electrode of the first light-emitting control transistor T5. The overlapping portion of the metal trace 253 and the active layer T6-P of the second emission control transistor T6 is reused as the control electrode of the second emission control transistor T6. That is, the control electrode of the first light-emitting control transistor T5 and the control electrode of the second light-emitting control transistor T6 in one sub-pixel 230 are located on one metal trace 252.

In some examples, referring to fig. 6A, the active film 240 further includes an active layer T3-P of the driving transistor T3, referring to fig. 6B, a second plate Cst2 of the capacitor Cst is further included in the first Gate metal layer Gate1, referring to fig. 5D, a forward projection of the second plate Cst2 on the substrate 210 overlaps a forward projection of the active layer T3-P of the driving transistor T3 on the substrate 210, wherein an overlapping portion of the second plate Cst2 and the active layer T3-P of the driving transistor T3 serves as a control electrode of the driving transistor T3.

In some examples, referring to fig. 7C, one emission control signal line EM includes a plurality of metal traces 253 and a plurality of transparent connection traces 263. The multiple metal traces 253 includes a fourth metal trace 253D, a fifth metal trace 253E, and a sixth metal trace 253F. In fig. 7C, the light-emitting control signal line EM, the metal trace 253, and the transparent connecting trace 263 are not shown, which can be referred to in fig. 7B.

The orthographic projection of the fourth metal wire 253D on the substrate 210 is at least partially located within the orthographic projection of the light-emitting device 232 of the first sub-pixel 230B on the substrate 210.

The orthographic projection of the fifth metal trace 253E on the substrate 210 is at least partially located within the orthographic projection of the light-emitting device 232 of the second sub-pixel 230G on the substrate 210.

The orthographic projection of the sixth metal trace 253F on the substrate 210 is at least partially located within the orthographic projection of the light-emitting device 232 of the third sub-pixel 230R on the substrate 210.

Referring to fig. 7B, the multiple transparent connection traces 263 in one light-emitting control signal line EM include a fifth transparent connection trace 263E, a sixth transparent connection trace 263F and a seventh transparent connection trace 263G, which are all disposed on the first transparent trace layer 271.

Referring to fig. 7B, a fourth metal trace 253D electrically connected to the first sub-pixel 230B of the first pixel unit 220 is electrically connected to a sixth metal trace 253F electrically connected to the third sub-pixel 230R by a fifth transparent connecting trace 263E.

The fourth metal trace 253D electrically connected to the first sub-pixel 230B in one first pixel unit 220 is electrically connected to the sixth metal trace 253F electrically connected to the third sub-pixel 230R in the first pixel unit 220 adjacent to the first pixel unit 220 in the first designated direction C1 through the sixth transparent connection trace 263F.

One end of the seventh transparent connecting trace 263G is electrically connected to one end of the fifth metal trace 253E, which is electrically connected to the second sub-pixel 230G and is far away from the first sub-pixel 230B, and the other end of the seventh transparent connecting trace 263G is electrically connected to the sixth transparent connecting trace 263F.

In addition to the first Gate metal layer Gate1, in some embodiments, referring to fig. 8A and 8B, the display panel 200 further includes: and a second Gate metal layer Gate2, the second Gate metal layer Gate2 being located between the active film layer 240 and the light emitting device 232.

In some examples, the material of the second Gate metal layer Gate2 is a metal, such as Al, ag, cu, cr, or the like.

Referring to fig. 8A and 8B, the circuit body 2311 of the pixel driving circuit 231 further includes: the capacitor Cst, and the first plate Cst1 of the capacitor Cst is located at the second Gate metal layer Gate2.

In some examples, referring to fig. 8B, the second Gate metal layer Gate2 is located on a side of the first Gate metal layer Gate1 away from the substrate 210. Wherein, the first plate Cst1 of the capacitor Cst, and an orthogonal projection of the first plate Cst1 on the substrate 210 at least partially overlaps an orthogonal projection of the second plate Cst2 on the substrate 210.

In some embodiments, referring to fig. 9A and 9B, the display panel 200 includes: the first source-drain metal layer SD1 is located between the substrate 210 and the light-emitting device 232, the first source-drain metal layer SD1 is located on one side of the second Gate metal layer Gate1 departing from the substrate 210, the first transparent wiring layer 271 is located on one side of the first source-drain metal layer SD1 departing from the substrate 210, and the first transparent wiring layer 271 is located between the first source-drain metal layer SD1 and the light-emitting device 232. Referring to fig. 9C, an interlayer dielectric layer ILD is disposed between the second Gate metal layer Gate1 and the first source/drain metal layer SD1, and a plurality of via holes ILDO are disposed in the interlayer dielectric layer ILD, where the positions of the via holes in the interlayer dielectric layer ILD are as shown in fig. 9C.

In some examples, the material of the first source drain metal layer SD1 is a metal, such as Al, ag, cu, cr, or the like.

Referring to fig. 7B and 7C, at least one signal line further includes: an initialization signal line VIN, one of which is electrically connected to the first pole of the second reset crystal T12 in the first pixel unit 220 of one row. The metal trace 254 of the initialization signal line VIN is located on the first source-drain metal layer SD1. Referring to fig. 5A, at least a portion of the orthographic projection of the metal trace 254 of the initialization signal line VIN on the substrate 210 is located within the orthographic projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210.

In some examples, one initialization signal line VIN includes a plurality of metal traces 254, and one metal trace 254 overlaps with the light emitting device 232 of one first sub-pixel 230B.

In some examples, a segment of the metal trace 254 in the initialization signal line VIN is disposed under the light emitting device 232 of the first sub-pixel 230B.

In other examples, a portion of one metal trace 254 in the initialization signal line VIN is disposed under the light emitting device 232 of the first sub-pixel 230B. At this time, the transparent connection trace 264 of the initialization signal line VIN is partially located under the light emitting device 232 of the first sub-pixel 230B.

Referring to fig. 7B, the transparent connection trace 264 of the initialization signal line VIN is disposed on the first transparent trace layer 271; the transparent connecting trace 264 of the initialization signal line VIN is connected to the metal trace 254 of the initialization signal line VIN through a via. The orthographic projection of the transparent connecting trace 264 of the initialization signal line VIN on the substrate 210 is located outside the orthographic projection of the light emitting device 232 of the second sub-pixel 230G on the substrate 210, and is located outside the orthographic projection of the light emitting device 232 of the third sub-pixel 230R on the substrate 210. Therefore, the transparent connecting trace 264 of the initialization signal line VIN does not occupy the space under the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R, and further the area of the pixel driving circuit 231 under the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R is increased, so that the light emitting device 232 of the second sub-pixel 230G and the pixel driving circuit 231 under the light emitting device 232 of the third sub-pixel 230R are prevented from being coupled due to too compact structure. In fig. 7B, the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R are not shown, please refer to fig. 5B.

In other examples, referring to fig. 5A, at least a portion of an orthographic projection of the metal trace 254 of the initialization signal line VIN on the substrate 210 is located within an orthographic projection of the anode AND-B of the first sub-pixel 230B on the substrate 210. The orthographic projection of the transparent connection trace 264 of the initialization signal line VIN on the substrate 210 is located outside the orthographic projection of the anode AND-G of the second sub-pixel 230G on the substrate 210, AND outside the orthographic projection of the anode AND-R of the third sub-pixel 230R on the substrate 210.

In some examples, referring to fig. 5A and fig. 9A, the metal trace 254 in the initialization signal line VIN includes a main trace segment 2541 and a connection trace segment 2542, wherein the main trace segment 2541 extends along the row direction X, the connection trace segment 2542 extends along the column direction Y, and one end of the main trace segment 2541 close to the third sub-pixel 230R is connected to the connection trace segment 2542.

Referring to fig. 5A, one end of the active layer T12-P of the second reset transistor T12 close to the third sub-pixel 230R is connected to the middle of the connection trace segment 2542 through a via, and one end of the connection trace segment 2542 away from the main trace segment 2541 is connected to the active layer T7-P of the third reset transistor T7 in the first sub-pixel 230B through a via.

In some examples, referring to fig. 7B, the display panel 200 further includes a first transparent wire 281, the first transparent wire 281 is disposed on the first transparent wire layer 271, one end of the first transparent wire 281 is electrically connected to one end of the connection wire 2542 far away from the main body wire 2541, and the other end of the first transparent wire 281 is electrically connected to the active layer T7-P of the third reset transistor T7 in the third sub-pixel 230R.

In some examples, referring to fig. 7C, the display panel 200 further includes a second transparent wire 282 and a third transparent wire 283, wherein the second transparent wire 282 is disposed on the first transparent wire layer 271, and the third transparent wire 283 is disposed on the second transparent wire layer 272. One end of the second transparent connection line 282 is electrically connected to the active layer T7-P of the third reset transistor T7 of the second sub-pixel 230G, the other end is electrically connected to the third transparent connection line 283, and one end of the third transparent connection line 283, which is far away from the second transparent connection line 282, is connected to one end of the first transparent connection line 281, which is connected to the connection line segment 2542, through the via hole.

Referring to fig. 7B, the display panel 200 further includes a fourth transparent wire 284 and a fifth transparent wire 285, wherein the fourth transparent wire 284 and the fifth transparent wire 285 are both located on the first transparent wiring layer 271.

One end of the fifth transparent wire 285 is electrically connected to the active layer T11-GP of the first reset transistor T11-G in the second sub-pixel 230G, and the other end thereof is electrically connected to the control electrode of the driving transistor T3 in the second sub-pixel 230G, that is, the second electrode Cst2 of the capacitor Cst.

One end of the fourth transparent wire 284 is electrically connected to the active layer T11-RP of the first reset transistor T11-R in the third sub-pixel 230R, and the other end is electrically connected to the control electrode of the driving transistor T3 in the third sub-pixel 230R, i.e., the second electrode Cst2 of the capacitor Cst.

Besides the metal trace 254 in the initialization signal line VIN, the first source-drain metal layer SD1 further includes a plurality of bridge patterns, and the bridge patterns are connected to the active film layer 240, the first Gate metal layer Gate1, and the second Gate metal layer Gate2 through via holes.

In some examples, referring to fig. 9A and 9B, the plurality of bridge patterns include a first bridge pattern 510, one end of the first bridge pattern 510 is connected to the active layer T6-P of the second emission control transistor T6 through a via, and the other end is connected to the active layer T7-P of the third reset transistor T7 through a via.

In some examples, referring to fig. 9A and 9B, a second bridge pattern 520 is included in the plurality of bridge patterns, and one end of the second bridge pattern 520 is connected to the control electrode of the driving transistor T3, i.e., the second electrode Cst2 of the capacitor Cst through a via, and the other end is connected to the active layer T2-P of the compensating transistor T2 through a via.

In some examples, referring to fig. 9A and 9B, a third bridge pattern 530 is included in the plurality of bridge patterns, and one end of the third bridge pattern 530 is connected to the first plate Cst1 of the capacitor Cst through a via hole and the other end is connected to the active layer T5-P of the first light emitting control transistor T5 through a via hole.

In some other examples, the orthogonal projection of the plurality of bridge patterns on the substrate 210 is also located within the orthogonal projection of the anode AND1 on the substrate 210.

In some embodiments, referring to fig. 10A and 10B, the display panel 200 includes: and the second source-drain metal layer SD2 is located between the substrate 210 and the light emitting device 232, and the second source-drain metal layer SD2 is located on a side of the second Gate metal layer Gate2 departing from the substrate 210.

Referring to fig. 11A and 11B, the display panel 200 further includes: and the second transparent wiring layer 272, the second transparent wiring layer 272 are both located between the substrate 210 and the light emitting device 232, and the second transparent wiring layer 272 is located on one side of the second source-drain metal layer SD2 departing from the second Gate metal layer Gate2.

In some examples, the second source-drain metal layer SD2 is located on a side of the first source-drain metal layer SD1 facing away from the substrate 210. The second source drain metal layer SD2 is made of metal, such as Al, ag, cu, cr, or the like. The material of the second transparent routing layer 272 is a transparent conductive oxide material, such as ITO, IZO, etc.

In the case that the display panel 200 further includes a first source-drain metal layer SD1 and a first transparent routing layer 271, in some examples, the first source-drain metal layer SD1, the second source-drain metal layer SD2, the first transparent routing layer 271 and the second transparent routing layer 272 are sequentially disposed on a side of the second Gate metal layer Gate2 away from the substrate 210.

In other examples, the first source-drain metal layer SD1, the first transparent routing layer 271, the second source-drain metal layer SD2, and the second transparent routing layer 272 are sequentially disposed on a side of the second Gate metal layer Gate2 away from the substrate 210. Referring to fig. 11C, a passivation layer PVX is disposed between the first source-drain metal layer SD1 and the first transparent routing layer 271, and a plurality of via holes PVXO are disposed in the passivation layer PVX. Referring to fig. 11D, a first planarization layer PLN1 is disposed between the first transparent wiring layer 271 and the second source-drain metal layer SD2, and a plurality of via holes PLNO1 are disposed in the first planarization layer PLN 1. Referring to fig. 11E, a second planarization layer PLN2 is disposed between the second source/drain metal layer SD2 and the second transparent routing layer 272, and a plurality of via holes PLNO2 are disposed in the second planarization layer PLN 2.

Referring to fig. 11B, at least one signal line further includes a first power signal line VDD1, the first power signal line VDD1 extends along the column direction Y, and one first power signal line VDD1 is electrically connected to the first plate Cst1 of the capacitors Cst1 of the second sub-pixel 230G and the third sub-pixel 230R in the column of the first pixel unit 220.

The first power signal line VDD1 extends along the column direction Y, which means that the body pattern of the first power signal line VDD1 tends to extend along the column direction Y. The pattern of the first power signal line VDD1 may be a straight line pattern or an approximately straight line pattern.

The first power signal line VDD1 is used for transmitting a first power signal. The first power signal line VDD1 is electrically connected to the first plate Cst1 of the capacitor Cst, thereby transmitting the first power signal to the first plate Cst1.

Referring to fig. 11B, the metal trace 255 of the first power signal line VDD1 is located on the second source-drain metal layer SD2, and at least a portion of the orthographic projection of the metal trace 255 of the first power signal line VDD1 on the substrate 210 is located within the orthographic projection of the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R on the substrate 210. The transparent connection trace 265 of the first power signal line VDD1 is disposed on the second transparent trace 272, and the transparent connection trace 265 of the first power signal line VDD1 is connected to the metal trace 255 of the first power signal line VDD1 through a via. In fig. 11B, the light emitting device 232 of the second sub-pixel 230G and the light emitting device 232 of the third sub-pixel 230R are not shown, and fig. 5C may be referred to.

In some other examples, referring to fig. 11B, at least a portion of the orthographic projection of the metal trace 255 of the first power signal line VDD1 on the substrate 210 is located within the orthographic projection of the anode AND-G of the second sub-pixel 230G AND the anode AND-R of the third sub-pixel 230R on the substrate 210. The anodes AND-G of the second sub-pixel 230G AND the anodes AND-R of the third sub-pixel 230R are not shown in FIG. 11B, as can be seen in FIG. 5C.

In some examples, referring to fig. 11B, the first power signal line VDD1 includes a plurality of metal traces 255, wherein the plurality of metal traces 255 in the first power signal line VDD1 includes a seventh metal trace 255G and an eighth metal trace 255H.

In some examples, the whole of the orthographic projection of the seventh segment of metal routing 255G on the substrate 210 is located within the orthographic projection of the light emitting device 232 of the second sub-pixel 230G on the substrate 210. The whole of the orthographic projection of the eighth segment of metal wiring 255H on the substrate 210 is located within the orthographic projection of the light emitting device 232 of the third sub-pixel 230R on the substrate 210. At this time, the seventh metal wire 255G and the eighth metal wire 255H are electrically connected through the transparent connection wire 265, and the transparent connection wire 265 extends to the lower portion of the light emitting device 232 of the third sub-pixel 230R and the lower portion of the light emitting device 232 of the second sub-pixel 230G.

In other examples, the orthographic projection of the seventh metal routing line 255G on the substrate 210 is located inside the orthographic projection of the light emitting device 232 of the second sub-pixel 230G on the substrate 210, and the rest is located outside the orthographic projection of the light emitting device 232 of the second sub-pixel 230G on the substrate 210. The orthographic projection of the eighth metal trace 255H on the substrate 210 is located inside the orthographic projection of the light-emitting device 232 of the third sub-pixel 230R on the substrate 210, and the rest is located outside the orthographic projection of the light-emitting device 232 of the third sub-pixel 230R on the substrate 210.

In some examples, referring to fig. 11B, the first power signal line VDD1 includes a plurality of transparent connecting traces 265 therein, and the plurality of transparent connecting traces 265 includes an eighth transparent connecting trace 265H and a ninth transparent connecting trace 265I therein.

In one first pixel unit 220, the seventh metal trace 255G electrically connected to the second sub-pixel 230G and the eighth metal trace 255H electrically connected to the third sub-pixel 230R are electrically connected to each other through the eighth transparent connecting trace 265H.

The eighth metal trace 255H electrically connected to the third sub-pixel 230R of one first pixel unit 220 is electrically connected to the seventh metal trace 255G electrically connected to the second sub-pixel 230G of the first pixel unit 220 adjacent to the second pixel unit 220 in the second designated direction C2 through the ninth transparent connecting trace 265I.

In some examples, referring to fig. 12A, the seventh metal wire 255G of the first power signal line VDD1 is connected to the third bridge pattern 530 under the light emitting device 232 of the second sub-pixel 230G through a via hole, so that the first type power signal line is transmitted to the first plate Cst1 of the capacitor Cst in the second sub-pixel 230G and the active layer T5-P of the first light emitting control transistor T5 through the third bridge pattern 530.

In some examples, referring to fig. 12B, the eighth metal routing wire 255H of the first power signal line VDD1 is connected to the third bridge pattern 530 under the light emitting device 232 of the third sub-pixel 230R through a via hole, thereby transmitting the first type power signal line to the first plate Cst1 of the capacitor Cst in the third sub-pixel 230R and the active layer T5-P of the first light emitting control transistor T5 through the third bridge pattern 530.

In some embodiments, referring to fig. 11B, at least one of the signal lines further includes a second power signal line VDD2, the second power signal line VDD2 extends in the column direction Y, and one of the second power signal lines VDD2 is electrically connected to the first plate Cst1 of the capacitor Cst of the first subpixel 230B in one column of the first pixel unit 220.

The second power signal line VDD2 extends along the column direction Y, which means that the body pattern of the second power signal line VDD2 tends to extend along the column direction Y. The pattern of the second power signal line VDD2 may be a straight line pattern or an approximate straight line pattern.

The second power signal line VDD2 is used for transmitting the first power signal. The second power signal line VDD2 is electrically connected to the first plate Cst1 of the capacitor Cst of the first sub-pixel 230B, so as to transmit the first power signal to the first plate Cst1 of the first sub-pixel 230B.

Referring to fig. 11B, the metal trace 256 of the second power signal line VDD2 is located on the second source-drain metal layer SD2, and an orthographic projection of the metal trace 256 of the second power signal line VDD2 on the substrate 210 is at least partially located within an orthographic projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210; the transparent connection trace 266 of the second power signal line VDD2 is disposed on the second transparent trace layer 272, and the transparent connection trace 266 of the second power signal line VDD2 is connected to the metal trace 256 of the second power signal line VDD2 through a via. In fig. 11B, the light emitting device 232 of the first sub-pixel 230B is not shown, and fig. 5C can be referred to.

In some examples, the orthographic projection of the metal trace 256 of the second power supply signal line VDD2 on the substrate 210 is entirely located within the orthographic projection of the light emitting device 232 of the first subpixel 230B on the substrate 210. At this time, the orthographic projection of the transparent connection trace 266 of the second power supply signal line VDD2 on the substrate 210 partially overlaps the orthographic projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210.

In other examples, the orthographic projection of the metal trace 256 of the second power signal line VDD2 on the substrate 210 is located within the orthographic projection of the light emitting device 232 of the first sub-pixel 230B on the substrate 210.

In some other examples, the orthographic projection of the metal trace 256 of the second power signal line VDD2 on the substrate 210 is at least partially within the orthographic projection of the AND-B of the first sub-pixel 230B on the substrate 210.

In some examples, referring to fig. 12C, the metal trace 256 of the second power signal line VDD2 is connected to the third bridge pattern 530 under the light emitting device 232 of the first subpixel 230B through a via hole, so that the first type of power signal is transmitted to the first plate Cst1 of the capacitor Cst in the first subpixel 230B and the active layer T5-P of the first light emitting control transistor T5 through the third bridge pattern 530.

The reset signal line RST, the scanning signal line GT, the emission control signal line EM, the first power signal line VDD1, and the second power signal line VDD2 in the display panel 200 have been described above. In addition to some of the signal lines described above, the display panel 200 further includes data lines DT. In some embodiments, referring to fig. 11B, the display panel 200 further includes: and a plurality of data lines DT extending in the column direction Y.

The data line DT extends in the column direction Y, and means that the main pattern of the data line DT tends to extend in the column direction Y. The data line DT pattern may be a straight line pattern or an approximately straight line pattern.

Referring to fig. 11B, the orthographic projection of the plurality of data lines DT in the first display area A1 on the substrate 210 is located outside the orthographic projection of the light emitting device 232 of any one of the sub-pixels 230 on the substrate 210.

Therefore, the data line DT does not occupy the space below the light emitting device 232, and thus the space occupied by the pixel driving circuit 231 below the light emitting device 232 can be increased, and the structure of the pixel driving circuit 231 below the light emitting device 232 is prevented from being too compact.

The portion of the at least one data line DT in the first display area A1 is located on the second transparent wiring layer 272. The portion of the data line DT in the first display area A1 is disposed on the second transparent routing layer 272, and the portion of the data line DT in the first display area A1 does not block light, so that the light transmittance of the first display area A1 in the display panel 200 can be improved.

Referring to fig. 7C, the circuit body 2311 of the pixel driving circuit 231 includes: the transistor T4 is written. In one first pixel unit 220, the first pole of the writing transistor T4 of the first sub-pixel 230B, the first pole of the writing transistor T4 of the second sub-pixel 230G, and the first pole of the writing transistor T4 of the third sub-pixel 230R are connected to different data lines DT, respectively. In fig. 7C, the writing transistor T4 of the first sub-pixel 230B, the first pole of the writing transistor T4 of the second sub-pixel 230G, and the writing transistor T4 of the third sub-pixel 230R are not shown, as shown in fig. 5D.

The data line DT is used to transmit a data signal, and in each sub-pixel 230, the first pole of the write transistor T4 is electrically connected to the data line DT, so that the data signal can be transmitted to the first pole of the write transistor T4. In one first pixel unit 220, the sub-pixels 230 are respectively connected to different data lines DT, and voltages of data signals in different data lines DT may be different, so that the light emitting devices 232 in different sub-pixels 230 may have different gray scales.

In addition, in some embodiments described above, in one first pixel unit 220, the first reset transistor T11 and the second reset transistor T12 in the plurality of sub-pixels 230 are simultaneously turned on, and thus the pixel driving circuits 231 in the plurality of sub-pixels 230 are simultaneously in the reset phase. The compensation transistor T2, the write transistor T4 and the third reset transistor T7 are turned on simultaneously, so that the pixel driving circuits 231 in the plurality of sub-pixels 230 are in the data refreshing and compensating period T2 simultaneously, and in the data refreshing and compensating period T2, the data signal is written into the control electrode of the driving transistor T3 through the write transistor T4 and the compensation transistor T2, so that the data signal is written into the pixel driving circuit 231 in one first pixel unit 220 simultaneously. The first and second light emission controlling transistors T5 and T6 are simultaneously turned on, and thus the pixel driving circuits 231 in the plurality of sub-pixels 230 are simultaneously in the light emission period T3. In summary, in the first pixel unit 220, the sub-pixels 230 emit light simultaneously.

In some embodiments, referring to fig. 7C, a portion of the at least one data line DT in the first display area A1 is a transparent line segment 27.

The transparent routing segment 27 is located on the second transparent routing layer 272, and in addition to the transparent routing segment 27, the second transparent routing layer 272 further includes a transparent connection pattern 2701, wherein the transparent connection pattern 2701 extends substantially along the row direction X, one end of the transparent connection pattern 2701 is connected to the transparent routing segment 27, and the other end is electrically connected to the active layer T4-P of the writing transistor T4.

In some examples, referring to fig. 9A, the first source/drain metal layer SD1 further includes a fourth bridge pattern 540. The first transparent routing layer 271 and the second source drain metal layer SD2 are both provided with a via pattern. One end of the transparent connection pattern 2701, which is far away from the transparent routing segment 27, is connected with a via hole of a transfer pattern in the second source-drain metal layer SD2 through a via hole, a transfer pattern in the second source-drain metal layer SD2 is connected with a via hole of a transfer pattern in the first transparent routing layer 271 through a via hole, a transfer pattern in the first transparent routing layer 271 is connected with a via hole of a fourth bridging pattern 540, and the fourth bridging pattern 540 is connected with an active layer T4-P of the writing transistor T4 through a via hole, so that a data signal is transmitted to the first pole of the writing transistor T4. In which the via depth can be reduced by disposing the fourth bridge pattern 540 and the plurality of via patterns on the transparent connection pattern 2701 and the active layer T4-P of the write transistor T4. Since the deeper the via, the greater the impedance, in some examples of the disclosure, the impedance may be reduced.

In some examples, the portion of each data line DT in the first display area A1 is located on the second transparent routing layer 272, i.e., each data line DT includes a transparent routing segment 27.

Referring to fig. 11B, in the first pixel unit 220 in the same column, the orthographic projection of the transparent line segment 27-B of the data line DT-B electrically connected to the write transistor T4 in the first sub-pixel 230B on the substrate 210 is located on a side of the orthographic projection of the circuit main body 2311-B of the first sub-pixel 230B on the substrate 210 away from the orthographic projection of the circuit main body 2311-G of the second sub-pixel 230G on the substrate 210.

The orthographic projection of the light-emitting device 232 of the second sub-pixel 230G on the substrate 210 and the orthographic projection of the light-emitting device 232 of the third sub-pixel 230R on the substrate 210 are located between the orthographic projection of the transparent wire segment 27-G of the data line DT-G electrically connected to the write transistor T4 of the second sub-pixel 230G on the substrate 210 and the orthographic projection of the transparent wire segment 27-R of the data line DT-R electrically connected to the write transistor T4 of the third sub-pixel 230G on the substrate 210.

The transparent line segment 27-G electrically connected to the second sub-pixel 230G and the transparent line segment 27-R electrically connected to the third sub-pixel 230G are disposed on two sides of the row of the second sub-pixel 230G and the third sub-pixel 230G, respectively.

In some examples, referring to FIGS. 11A and 11B, the transparent line segment 27-R, the transparent line segment 27-G, and the transparent line segment 27-B are arranged in sequence along a first designated direction C1.

In other examples, the transparent line segment 27-G, the transparent line segment 27-R, and the transparent line segment 27-B are sequentially arranged along the first designated direction C1.

In some embodiments, referring to FIG. 5D, in a first pixel unit 220, the third reset transistor T7, the compensation transistor T2 and the write transistor T4 of the first sub-pixel 230B are sequentially far away from the circuit bodies 2311-G of the second sub-pixel 230G. That is, the third reset transistor T7, the compensation transistor T2 and the write transistor T4 in the first sub-pixel 230B are sequentially away from the column where the second sub-pixel 230G and the third sub-pixel 230R are located, so that the transparent line segment 27-B electrically connected to the first sub-pixel 230B can be located at a side of the first sub-pixel 230B away from the column where the second sub-pixel 230G and the second sub-pixel 230R are located.

In some embodiments, referring to fig. 5D, in one first pixel unit 220, the third reset transistor T7, the compensation transistor T2 and the write transistor T4 of the second sub-pixel 230G are sequentially arranged along a first setting direction; the third reset transistor T7, the compensation transistor T2, and the write transistor T4 in the third subpixel 230R are sequentially disposed in a reverse direction of the first setting direction.

Referring to fig. 11B in conjunction with fig. 5D, the transparent wire segment 27 is electrically connected to the active layer T4-P of the write transistor T4. In one sub-pixel 230 of the second sub-pixel 230G and the third sub-pixel 230R, the writing transistor T4 is located on a side of the compensation transistor T2 away from the first sub-pixel 230B. In the other sub-pixel 230, the writing transistor T4 is located on the side of the compensation transistor T2 close to the first sub-pixel 230B. Therefore, the transparent wire segment 27-G electrically connected to the second sub-pixel 230G and the transparent wire segment 27-R of the third sub-pixel 230R can be disposed on two sides of the column of the second sub-pixel 230G and the third sub-pixel 230R, respectively, and the transparent wire segment 27-R can be connected to the writing transistor T4 of the third sub-pixel 230R, and the transparent wire segment 27-G can be connected to the writing transistor T4 of the second sub-pixel 230G.

In some examples, referring to fig. 11B, the first setting direction D is opposite to the first designated direction C1, and at this time, the transparent line segment 27-R electrically connected to the third sub-pixel 230R, the transparent line segment 27-G electrically connected to the second sub-pixel 230G, and the data line 27-B electrically connected to the first sub-pixel 230B are sequentially disposed along the first designated direction C1.

In other examples, the first setting direction D is the same as the first designated direction C1, and the transparent line segment 27-G electrically connected to the second sub-pixel 230G, the transparent line segment 27-R electrically connected to the third sub-pixel 230R, and the data line 27-B electrically connected to the first sub-pixel 230B are sequentially disposed along the first designated direction C1.

Referring to fig. 13A AND 13B, the display panel 200 further includes an anode layer AND including a plurality of anodes AND1, such as anodes AND-B of the first sub-pixel 230B, anodes AND-G of the second sub-pixel 230G, AND anodes AND-R of the third sub-pixel 230R.

In some embodiments, referring to fig. 2B, in addition to the first display area A1, the display panel 200 further includes: the second display area A2, the first display area A1 is provided with the first pixel unit 220. A plurality of second pixel units 290 are arranged in the second display area A2, and the plurality of second pixel units 290 are arranged in multiple rows and multiple columns; the second pixel unit 290 includes a plurality of sub-pixels 291. The plurality of sub-pixels 291 includes a first sub-pixel 291B, a second sub-pixel 291G, and a third sub-pixel 291R,

the second display area A2 is located on at least one side of the first display area A1. In some examples, the second display area A2 may be disposed at one or more sides of the first display area A1. In other examples, the second display area A2 may be disposed around the first display area A1 by one turn. It should be noted that, in fig. 2B, an area framed by the smaller dashed box is a first display area A1, the larger dashed box is located outside the smaller dashed box, an area between the smaller dashed box and the larger dashed box is a second display area A2, and the first display area A1 and the second display area A2 together form a display area AA.

Referring to fig. 14, the sub-pixel 291 of the second pixel unit 290 includes a light emitting device 232, and the area of the light emitting device 232 of the first sub-pixel 291B of the second pixel unit 290 is larger than the area of the light emitting device 232 of the second sub-pixel 291G of the second pixel unit 290 and larger than the area of the light emitting device 232 of the third sub-pixel 291R of the second pixel unit 290.

Wherein the light emitting device 232 includes an anode AND1. In some examples, the area of the anode AND1 of the first sub-pixel 291B of the second pixel unit 290 is greater than the area of the anode AND1 of the second sub-pixel 291G of the second pixel unit 290 AND is greater than the area of the anode AND1 of the third sub-pixel 291R of the second pixel unit 290.

In some embodiments, the area of the light emitting device 232 of the sub-pixel 230 in the first display area A1 is 0.4 to 0.6 times the area of the light emitting device 232 of the sub-pixel 291 of the same color in the second display area A2.

In some examples, in the second display area A2, the first sub-pixel 291B of the second pixel unit 290 may be a blue sub-pixel, the second sub-pixel 291G may be a green sub-pixel, and the third sub-pixel 291R may be a red sub-pixel.

As can be seen from the above, in some examples, in the first display area A1, the first sub-pixel 230B of the first pixel unit 220 is a blue sub-pixel, the second sub-pixel 230G is a green sub-pixel, and the third sub-pixel 230R is a red sub-pixel.

In some examples, the area of the light emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 is 0.4 to 0.6 times the area of the light emitting device 232 of the first sub-pixel 291B of the second pixel unit 290, so that it can be avoided that the area of the light emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 is too large (e.g., greater than 0.6 times the area of the light emitting device 232 of the first sub-pixel 291B), which results in a low light transmittance of the first display region A1. Meanwhile, it can be avoided that the area of the light emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 is too small (for example, smaller than 0.4 times the area of the light emitting device 232 of the first sub-pixel 291B), which results in that the area occupied by the pixel driving circuit 231 located under the light emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 is small, so that the structure in the pixel driving circuit 231 of the light emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 is too compact, and coupling occurs between the structures.

Illustratively, the area of the light emitting device 232 of the first sub-pixel 230B of the first pixel unit 220 is 0.5 times the area of the light emitting device 232 of the first sub-pixel 291B of the second pixel unit 290.

Referring to fig. 14, the area of the light emitting device 232 of the second sub-pixel 230G of the first pixel unit 220 is 0.4 to 0.6 times the area of the light emitting device 232 of the second sub-pixel 291G of the second pixel unit 290, so as to prevent the light transmittance of the first display area A1 from being low due to the excessively large area of the light emitting device 232 of the second sub-pixel 230G of the first pixel unit 220 (for example, larger than 0.6 times the area of the light emitting device 232 of the second sub-pixel 291G). Meanwhile, it can be avoided that the area of the light emitting device 232 of the second sub-pixel 230G of the first pixel unit 220 is too small (for example, smaller than 0.4 times the area of the light emitting device 232 of the second sub-pixel 291G), which results in a small area occupied by the circuit body 2311-G of the second sub-pixel 230G under the light emitting device 232 of the second sub-pixel 230G of the first pixel unit 220, so that the structures in the circuit body 2311-G of the second sub-pixel 230G of the first pixel unit 220 are too compact, and coupling occurs between the structures.

Illustratively, the area of the light emitting device 232 of the second sub-pixel 230G of the first pixel unit 220 is 0.5 times the area of the light emitting device 232 of the second sub-pixel 291G of the second pixel unit 290.

Referring to fig. 14, the area of the light emitting device 232 of the third sub-pixel 230R of the first pixel unit 220 is 0.4 to 0.6 times the area of the light emitting device 232 of the third sub-pixel 291R of the second pixel unit 290. Accordingly, it is possible to prevent the light emitting device 232 of the third sub-pixel 230R of the first pixel unit 220 from having an excessively large area (e.g., larger than 0.6 times the area of the light emitting device 232 of the third sub-pixel 291R), which results in a low light transmittance of the first display region A1. Meanwhile, the area of the light emitting device 232 of the third sub-pixel 230R of the first pixel unit 220 is also prevented from being too small (for example, smaller than 0.4 times the area of the light emitting device 232 of the third sub-pixel 291R), which results in a small area occupied by the circuit main body 2311-R of the third sub-pixel 230R under the light emitting device 232 of the third sub-pixel 230R of the first pixel unit 220, and thus the structures in the circuit main bodies 2311-R of the third sub-pixel 230R are too compact, which causes coupling between the structures.

Illustratively, the area of the light emitting device 232 of the third sub-pixel 230R of the first pixel unit 220 is 0.5 times the area of the light emitting device 232 of the third sub-pixel 291R of the second pixel unit 290.

In some examples, the sub-pixel density of the first display area A1 is equal to the sub-pixel density of the second display area A2. Note that the sub-pixel density of the first display area A1 refers to the number of sub-pixels 230 per unit area in the first display area A1. The sub-pixel density of the second display area A2 refers to the number of sub-pixels 291 per unit area in the second display area A2.

Here, although the area of the light emitting device 232 of the sub-pixel 291 in the second display area A2 is larger than the area of the light emitting device 232 of the sub-pixel 230 in the first display area A1 having the same color as that of the sub-pixel, the sub-pixel density of the first display area A1 is equal to that of the second display area A2, and thus, the display difference between the first display area A1 and the second display area A2 can be reduced.

In addition, the light transmittance of the first display area A1 is greater than that of the second display area A2, thereby ensuring that the sensor 300 can sense sufficient light.

The structure of the light emitting device 232 of the sub-pixel 291 is the same as that of the light emitting device 232 of the sub-pixel 230, and is not described herein again. Here, it is understood that, in the cathode CTD1, the light-emitting layer EL AND the anode AND1 of one sub-pixel 291, if the area of the cathode CTD1 is the largest, the area of the light-emitting device 232 of the sub-pixel 291 is the area of the cathode CTD1. If the area of the anode AND1 is the largest, the area of the light emitting device 232 of the sub-pixel 291 is the area of the anode AND1. If the area of the light-emitting layer EL is the largest, the area of the light-emitting device 232 of the sub-pixel 291 is the area of the light-emitting layer EL.

Some embodiments of the present disclosure provide a display device 100 including: the display panel 200 provided in any of the above embodiments. Therefore, the display device 100 provided in some embodiments of the present disclosure has all the advantages of the display panel 200 provided in any of the above embodiments, which are not repeated herein.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can appreciate that the variations or substitutions within the technical scope of the present disclosure should be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (20)

1. A display panel, comprising:

a substrate;

the first pixel units are positioned on one side of the substrate and are arranged in multiple rows and multiple columns; the first pixel unit comprises a plurality of sub-pixels, and each sub-pixel comprises a pixel driving circuit and a light-emitting device; the light-emitting device is positioned on one side of the pixel driving circuit far away from the substrate and is electrically connected with the pixel driving circuit; the pixel driving circuit includes a first reset transistor;

the plurality of sub-pixels comprise a first sub-pixel, a second sub-pixel and a third sub-pixel, and the area of the light emitting device of the first sub-pixel is larger than that of the light emitting device of the second sub-pixel and is larger than that of the light emitting device of the third sub-pixel;

and the orthographic projection of the first reset transistor in the second sub-pixel and/or the first reset transistor in the third sub-pixel on the substrate is positioned within the orthographic projection of the light-emitting device of the first sub-pixel on the substrate.

2. The display panel according to claim 1,

the first reset transistor of the first sub-pixel, the first reset transistor of the second sub-pixel and the first reset transistor of the third sub-pixel are all located within the orthographic projection of the light-emitting device of the first sub-pixel on the substrate.

3. The display panel according to claim 1,

at least two of the first reset transistor of the first sub-pixel, the first reset transistor of the second sub-pixel, and the first reset transistor of the third sub-pixel are the same transistor.

4. The display panel according to any one of claims 1 to 3,

the pixel driving circuit further comprises a second reset transistor; the second reset transistor of the first sub-pixel, the second reset transistor of the second sub-pixel and the second reset transistor of the third sub-pixel are the same transistor; an orthographic projection of the second reset transistor on the substrate is positioned in the orthographic projection of the light emitting device of the first sub-pixel on the substrate; the second reset transistor is connected in series with any one of the first reset transistors;

the display panel further comprises a reset signal line and an initialization signal line; a control electrode of each of the first reset transistors and a control electrode of the second reset transistor are electrically connected to the reset signal line; a first electrode of the second reset transistor is electrically connected to the initialization signal line, and a second electrode of the second reset transistor is electrically connected to a first electrode of each of the first reset transistors;

the pixel driving circuit further includes: and a control electrode of the driving transistor of each pixel driving circuit is electrically connected with the second electrode of each first reset transistor.

5. The display panel according to claim 4,

the light emitting device of the second sub-pixel and the light emitting device of the third sub-pixel are arranged at intervals in a column direction; the light emitting device of the first sub-pixel is positioned in an adjacent column of the column where the light emitting device of the second sub-pixel and the light emitting device of the third sub-pixel are positioned; and the light emitting device of the first sub-pixel spans a gap region between the light emitting device of the second sub-pixel and the light emitting device of the third sub-pixel;

the pixel driving circuit further comprises a circuit main body; an orthographic projection of the circuit body of the first sub-pixel on the substrate is positioned within an orthographic projection of the light-emitting device of the first sub-pixel on the substrate, an orthographic projection of the circuit body of the second sub-pixel on the substrate is positioned within an orthographic projection of the light-emitting device of the second sub-pixel on the substrate, and an orthographic projection of the circuit body of the third sub-pixel on the substrate is positioned within an orthographic projection of the light-emitting device of the third sub-pixel on the substrate;

the second reset transistor, the first reset transistor of the third sub-pixel and the first reset transistor of the second sub-pixel are located on one side, close to the circuit main body of the third sub-pixel, of the first reset transistor of the first sub-pixel, and are sequentially far away from the circuit main body of the third sub-pixel.

6. The display panel according to claim 5,

the reset signal lines extend along a row direction, and one of the reset signal lines is electrically connected to the control electrodes of the second reset transistors and the control electrodes of the first reset transistors in one row of the first pixel units;

the initialization signal lines extend in a row direction, one of the initialization signal lines is electrically connected to the first poles of the second reset crystals in one row of the first pixel units;

the orthographic projection of the second reset transistor and each first reset transistor on the substrate is positioned between the orthographic projection of an initialization signal line electrically connected with the second reset transistor on the substrate and the orthographic projection of the circuit main body of the third sub-pixel on the substrate; the orthographic projection of the reset signal line on the substrate is positioned between the orthographic projection of the initialization signal line on the substrate and the orthographic projection of the circuit main body of the third sub-pixel on the substrate.

7. The display panel according to claim 5 or 6,

the substrate comprises a first display area, and the plurality of first pixel units are positioned in the first display area;

the display panel further includes: a plurality of signal lines between the substrate and the light emitting device;

the part of at least one signal line in the first display area comprises a metal routing line and a transparent connecting routing line which are electrically connected with each other; and the orthographic projection of at least part of the metal wiring on the substrate is positioned in the orthographic projection of the light-emitting device on the substrate.

8. The display panel according to claim 7, comprising:

the first grid metal layer and the first transparent wiring layer are positioned between the substrate and the light-emitting device, and the first transparent wiring layer is positioned on one side, away from the substrate, of the first grid metal layer;

the at least one signal line includes a reset signal line extending in a row direction, one of the reset signal lines being electrically connected to the control electrodes of the second reset transistors and the control electrodes of the respective first reset transistors in one row of the first pixel units;

the metal wiring of the reset signal line is positioned on the first gate metal layer, and at least part of the orthographic projection of the metal wiring of the reset signal line on the substrate is positioned in the orthographic projection of the light-emitting device of the first sub-pixel on the substrate;

the transparent connecting wiring of the reset signal line is positioned on the first transparent wiring layer; the orthographic projection of the transparent connecting wiring of the reset signal wire on the substrate is positioned outside the orthographic projection of the light-emitting device of the second sub-pixel on the substrate and outside the orthographic projection of the light-emitting device of the third sub-pixel on the substrate; the transparent connecting wires of the reset signal wires are connected with the metal wires of the reset signal wires through via holes.

9. The display panel according to claim 8,

the circuit main body of the pixel driving circuit comprises a writing transistor, a compensation transistor and a third reset transistor;

the at least one signal line further comprises a scanning signal line, and one scanning signal line is electrically connected with the control electrodes of the writing transistors, the control electrodes of the compensating transistors and the control electrodes of the third reset transistors of all the sub-pixels in one row of the first pixel units;

the metal wiring of the scanning signal line is positioned on the first gate metal layer, and at least part of the orthographic projection of the metal wiring of the scanning signal line on the substrate is positioned in the orthographic projection of the light-emitting device on the substrate;

the transparent connecting wires of the scanning signal wires are positioned on the first transparent wire routing layer, and the transparent connecting wires of the scanning signal wires are connected with the metal wires of the scanning signal wires through via holes.

10. The display panel according to claim 8 or 9,

the circuit main body of the pixel driving circuit further comprises a first light-emitting control transistor and a second light-emitting control transistor;

the at least one signal line further includes a light emission control signal line, and one of the light emission control signal lines is electrically connected to the control electrodes of the first light emission control transistors and the control electrodes of the second light emission control transistors of all the sub-pixels in one row of the first pixel unit;

the metal wiring of the light-emitting control signal wire is positioned on the first gate metal layer, and at least part of the orthographic projection of the metal wiring of the light-emitting control signal wire on the substrate is positioned in the orthographic projection of the light-emitting device on the substrate;

the transparent connecting wires of the light-emitting control signal wires are positioned on the first transparent wire routing layer, and the transparent connecting wires of the light-emitting control signal wires are connected with the metal wires of the light-emitting control signal wires through via holes.

11. The display panel according to claim 7, comprising: the first source drain metal layer and the first transparent routing layer are both positioned between the substrate and the light-emitting device, and the first transparent routing layer is positioned on one side, away from the substrate, of the first source drain metal layer;

the at least one signal line further includes: an initialization signal line, one of which is electrically connected to the first poles of the second reset crystals in one row of the first pixel units;

the metal wiring of the initialization signal line is positioned on the first source-drain metal layer, and at least part of the orthographic projection of the metal wiring of the initialization signal line on the substrate is positioned in the orthographic projection of the light-emitting device of the first sub-pixel on the substrate;

the transparent connecting wiring of the initialization signal wire is positioned on the first transparent wiring layer; the orthographic projection of the transparent connecting wiring of the initialization signal wire on the substrate is positioned outside the orthographic projection of the light-emitting device of the second sub-pixel on the substrate and outside the orthographic projection of the light-emitting device of the third sub-pixel on the substrate; the transparent connecting wires of the initialization signal wires are connected with the metal wires of the initialization signal wires through via holes.

12. The display panel according to claim 7, comprising: the second gate metal layer, the second source drain metal layer and the second transparent wiring layer are positioned between the substrate and the light-emitting device, the second source drain metal layer is positioned on one side, away from the substrate, of the second gate metal layer, and the second transparent wiring layer is positioned on one side, away from the second gate metal layer, of the second source drain metal layer;

the circuit main body of the pixel driving circuit further includes: a capacitor, wherein a first plate of the capacitor is positioned on the second gate metal layer;

the at least one signal line further includes a first power supply signal line extending in a column direction, one of the first power supply signal lines being electrically connected to a first plate of the capacitor of the second sub-pixel and a first plate of the capacitor of the third sub-pixel in one column of the first pixel unit;

the metal wire of the first power signal wire is positioned on the second source-drain metal layer, and at least part of the orthographic projection of the metal wire of the first power signal wire on the substrate is positioned in the orthographic projection of the light-emitting device of the second sub-pixel and the light-emitting device of the third sub-pixel on the substrate;

the transparent connecting wire of the first power signal wire is positioned on the second transparent wire layer, and the transparent connecting wire of the first power signal wire is connected with the metal wire of the first power signal wire through a via hole.

13. The display panel according to claim 12,

the at least one signal line further includes a second power supply signal line extending in a column direction, one of the second power supply signal lines being electrically connected to the first plate of the capacitor of the first sub-pixel in one column of the first pixel unit;

the metal wire of the second power signal wire is positioned on the second source-drain metal layer, and the orthographic projection of the metal wire of the second power signal wire on the substrate is at least partially positioned in the orthographic projection of the light-emitting device of the first sub-pixel on the substrate;

the transparent connecting wire of the second power signal wire is positioned on the second transparent wire layer, and the transparent connecting wire of the second power signal wire is connected with the metal wire of the second power signal wire through a via hole.

14. The display panel according to claim 12 or 13, further comprising:

a plurality of data lines extending along a column direction, wherein orthographic projections of the parts of the data lines in the first display area on the substrate are positioned outside orthographic projections of the light-emitting devices of any sub-pixels on the substrate, and the part of at least one data line in the first display area is positioned on the second transparent routing layer;

the circuit body of the pixel driving circuit includes: a write transistor; in one of the first pixel units, a first pole of the writing transistor of the first sub-pixel, a first pole of the writing transistor of the second sub-pixel, and a first pole of the writing transistor of the third sub-pixel are connected to different ones of the data lines, respectively.

15. The display panel according to claim 14,

the part of the at least one data line in the first display area is a transparent route segment;

in the same column of the first pixel units, the orthographic projection of a transparent line segment of a data line electrically connected with a writing transistor in the first sub-pixel on the substrate is positioned on one side, away from the orthographic projection of a circuit main body of the second sub-pixel on the substrate, of the circuit main body of the first sub-pixel; the orthographic projection of the light-emitting device of the second sub-pixel on the substrate and the orthographic projection of the light-emitting device of the third sub-pixel on the substrate are positioned between the orthographic projection of the transparent line segment of the data wire electrically connected with the writing transistor of the second sub-pixel on the substrate and the orthographic projection of the transparent line segment of the data wire electrically connected with the writing transistor of the third sub-pixel on the substrate.

16. The display panel according to claim 15,

the circuit main body of the pixel driving circuit further comprises a compensation transistor and a third reset transistor;

in one first pixel unit, a third reset transistor, a compensation transistor and a writing transistor in the first sub-pixel are sequentially far away from a circuit main body of the second sub-pixel; a third reset transistor, a compensation transistor and a write-in transistor in the second sub-pixel are sequentially arranged along a first set direction; and a third reset transistor, a compensation transistor and a write transistor in the third sub-pixel are sequentially arranged along the reverse direction of the first setting direction.

17. The display panel according to any one of claims 1 to 3,

the light-emitting device comprises an anode, a light-emitting layer and a cathode, wherein the anode is electrically connected with the pixel driving circuit, the light-emitting layer is positioned on one side of the anode, which is far away from the substrate, and the cathode is positioned on one side of the light-emitting layer, which is far away from the substrate;

and the orthographic projection of the first reset transistor in the second sub-pixel and/or the first reset transistor in the third sub-pixel on the substrate is positioned in the orthographic projection of the anode of the first sub-pixel on the substrate.

18. The display panel according to any one of claims 1 to 3,

the first sub-pixel is a blue sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a red sub-pixel.

19. The display panel according to any one of claims 1 to 3, comprising:

the display device comprises a first display area and a second display area, wherein the first display area is provided with a first pixel unit;

the second display area is provided with a plurality of second pixel units which are arranged in a plurality of rows and a plurality of columns; the second pixel unit comprises a plurality of sub-pixels, and the sub-pixel density of the first display area is equal to that of the second display area;

the area of the light emitting device of the sub-pixel in the first display area is 0.4-0.6 times that of the light emitting device of the sub-pixel in the same color in the second display area.

20. A display device, comprising:

the display panel according to any one of claims 1 to 19.

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