CN217563650U

CN217563650U - Digital signal transmission analyzer

Info

Publication number: CN217563650U
Application number: CN202220386353.XU
Authority: CN
Inventors: 郭乃天; 员雪峰; 张建成; 徐仲春; 张雷; 房行
Original assignee: Shandong Institute for Product Quality Inspection
Current assignee: Shandong Institute for Product Quality Inspection
Priority date: 2022-02-24
Filing date: 2022-02-24
Publication date: 2022-10-11
Anticipated expiration: 2032-02-24

Abstract

The utility model provides a digital signal transmission analysis appearance, including complicated programmable device, clock signal generator, digital signal generator, active low pass filter, pseudo-random signal generator, adder, frequency-selecting network, synchronizing signal draw module and oscilloscope. A Complex Programmable Logic Device (CPLD) is taken as a core, a necessary analog circuit is used as an auxiliary circuit to form a digital signal transmission performance analyzer, a phase-locked loop circuit is adopted to extract synchronous signals, so that input signals and output signals are strictly synchronous, the automatic control of phase synchronization is completed, and the digital signal transmission performance test with high precision and low cost is realized.

Description

Digital signal transmission analyzer

Technical Field

The present disclosure relates to the field of testing technologies, and in particular, to a digital signal transmission analyzer.

Background

A digital signal analyzer is an apparatus that analyzes a frequency spectrum, a correlation function, a power spectral density, and the like of an input signal using a digital technique. Because the digital signal is influenced by factors such as transmission line impedance and noise in the transmission process, the signal has phenomena such as propagation fading, intersymbol interference, adjacent channel interference and the like. The existing digital signal analyzer cannot efficiently eliminate various interferences in the process of digital signal transmission, so that the data analysis result is inaccurate, and the overall experimental effect is influenced. For the digital signal transmission performance test with high precision requirement, the required equipment and instruments are too complex and expensive. The prior art lacks research on a digital signal transmission analyzer with high precision and low cost.

SUMMERY OF THE UTILITY MODEL

In order to solve the deficiency of the prior art, the utility model provides a digital signal transmission analyzer to complicated programmable device (CPLD) is the core, is aided with necessary analog circuit, constitutes digital signal transmission performance analyzer, realizes high accuracy, low-cost digital signal transmission performance test.

The utility model adopts the following technical scheme: a digital signal transmission analyzer comprises a complex programmable device, a clock signal generator, a digital signal generator, an active low-pass filter, a pseudo-random signal generator, an adder, a frequency selection network, a synchronous signal extraction module and an oscilloscope, wherein the output end of the complex programmable device is connected with the input end of the clock signal generator; one output end of the clock signal generator is connected with the digital signal generator, and the other output end of the clock signal generator is connected with the input end of the pseudo-random signal generator; the output end of the digital signal generator is connected with the input end of the active low-pass filter; one output end of the active low-pass filter is connected with the input end of the pseudo-random signal generator, and the other output end of the active low-pass filter is connected with one input end of the adder; the output end of the pseudo-random signal generator is connected with the other input end of the adder; one output end of the adder is connected with one input end of the oscilloscope, and the other output end of the adder is connected with the input end of the frequency selection network; the output end of the frequency selection network is connected with the input end of the synchronous signal extraction module; and the output end of the synchronous signal extraction module is connected with the other input end of the oscilloscope. The adder, the frequency selection network, the synchronous signal extraction module and the oscilloscope form a phase-locked loop circuit, so that the input signal and the output signal are strictly synchronous.

Further, the synchronization signal extraction module comprises a phase comparator, an M-time frequency divider, a narrow pulse former and an oscillator.

Further, the digital signal generator employs a shift register 74LS299 and an xor gate 74F86 chip.

Further, the pseudo-random signal generator adopts a shift register 74F673 and an exclusive-or gate 74F86 chip; the pseudo-random signal generator is used for receiving signals of the active low-pass filter and the clock signal generator and transmitting the signals to the adder.

Furthermore, the active low-pass filter adopts a third-order active low-pass filter, and the third-order active low-pass filter is formed by cascading a first-order low-pass filter and a second-order low-pass filter.

Further, the complex programmable device is used for frequency division to generate a clock signal.

Further, the adder is composed of a same direction proportion summation operation circuit and is used for receiving signals transmitted by the active low-pass filter and the pseudo-random signal generator.

Further, the frequency selection network adopts an LC circuit.

Compared with the prior art, the beneficial effects of the utility model are that:

the utility model discloses use Complicated Programmable Logic Device (CPLD) as the core, be aided with necessary analog circuit, constitute digital signal transmission performance analysis appearance. The filter function is realized under the condition of low cost, and the synchronous signal extraction of the digital signal analysis circuit is realized after the phase-locked loop passes through the frequency selection network.

Digital signal transmission analysis appearance advantage enables input signal and output signal through phase-locked loop circuit and strict synchronization, realizes phase synchronization's automatic control, can accomplish two signal of telecommunication phase synchronization's automatic control, can reach main technical index such as synchronous hold time and synchronous set-up time through the parameter that changes loop filter moreover.

Drawings

The accompanying drawings, which form a part of the specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention without unduly limiting the scope of the invention.

Fig. 1 is a schematic structural diagram of the digital signal transmission analyzer of the present invention;

fig. 2 is a schematic structural diagram of a synchronization signal extraction module in the digital signal transmission analyzer of the present invention;

in the figure: 1. a complex programmable device; 2. a clock signal generator; 3. a digital signal generator; 4. an active low pass filter; 5. a pseudo-random signal generator; 6. an adder; 7. a frequency selective network; 8. a synchronization signal extraction module; 9. an oscilloscope.

Detailed Description

The present invention will be further described with reference to the accompanying drawings and examples.

It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the invention. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof;

for convenience of description, the words "upper", "lower", "left" and "right" in the present application, if any, merely indicate correspondence with the upper, lower, left and right directions of the drawings themselves, and do not limit the structure, but merely facilitate the description of the present invention and simplify the description, rather than indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention.

Examples

The utility model provides a digital signal transmission analyzer for solving the technical problem in the background art on the basis of the prior art, including complicated programmable device 1, clock signal generator 2, digital signal generator 3, active low pass filter 4, pseudo-random signal generator 5, adder 6, frequency-selecting network 7, synchronizing signal extraction module 8 and oscilloscope 9, the output of complicated programmable device 1 is connected with the input of clock signal generator 2; one output end of the clock signal generator 2 is connected with the digital signal generator 3, and the other output end of the clock signal generator 3 is connected with the input end of the pseudo-random signal generator 5; the output end of the digital signal generator 3 is connected with the input end of the active low-pass filter 4; one output end of the active low-pass filter 4 is connected with an input end of a pseudo-random signal generator 5, and the other output end of the active low-pass filter 4 is connected with one input end of an adder 6; the output end of the pseudo-random signal generator 5 is connected with the other input end of the adder 6; one output end of the adder 6 is connected with one input end of the oscilloscope 9, and the other output end of the adder 6 is connected with the input end of the frequency selection network 7; the output end of the frequency selection network 7 is connected with the input end of the synchronous signal extraction module 8; the output end of the synchronization signal extraction module 8 is connected with the other input end of the oscilloscope 9.

The digital signal generator 3 adopts a chip of a shift register 74LS299 and an exclusive-OR gate 74F 86.

The pseudo-random signal generator 5 adopts a shift register 74F673 and an exclusive-OR gate 74F86 chip; the pseudo-random signal generator is used for receiving signals of the active low-pass filter and the clock signal generator, generating an m-sequence, performing code division multiple access and transmitting the m-sequence to the adder.

The active low-pass filter 4 adopts a third-order active low-pass filter, and the third-order active low-pass filter is formed by cascading a first-order low-pass filter and a second-order low-pass filter.

The complex programmable device 1 is used for generating a clock signal by frequency division, and the clock signal can realize the step adjustment of the clock frequency through 4 peripheral dial switches.

The adder 6 is composed of a same direction proportional summation operation circuit and is used for receiving signals transmitted by the active low-pass filter and the pseudo-random signal generator.

The synchronous signal extraction module 8 comprises a phase comparator, an M-time frequency divider, a narrow pulse former and an oscillator; the method is used for extracting the synchronous signals, and the synchronous signals are extracted by a phase-locked loop circuit after passing through a frequency selection network 7. The method can strictly synchronize the input signal with the output signal, realize the automatic control of phase synchronization, complete the automatic control of phase synchronization of two electric signals, and achieve main technical indexes such as synchronization holding time, synchronization establishing time and the like by changing the parameters of a loop filter.

A phase-locked loop circuit is a closed-loop electronic circuit that maintains both the frequency and phase of a controlled oscillator in a determined relationship to an input signal. The frequency tracking circuit is a typical feedback control circuit, and the frequency and the phase of an internal oscillation signal of a loop are controlled by using an externally input reference signal, so that the frequency of an output signal is automatically tracked to the frequency of an input signal. The specific working principle is as follows: one part of the signal is given as output, the other part of the signal is compared with the phase of the generated local oscillation signal through frequency division, the phase difference is required to be unchanged in order to keep the frequency unchanged, if the phase difference is changed, the voltage of the voltage output end is changed, and the control is carried out until the phase difference is recovered, so that the purpose of phase locking is achieved.

The frequency selection network 7 adopts an LC circuit for selecting and comparing the stored signals with the frequency to realize the synchronization of the signals.

The utility model discloses a theory of operation does: the complex programmable device generates a clock signal through frequency division of a clock signal generator, and the clock frequency is adjusted in a stepping mode through 4 peripheral dial switches and transmitted to a digital signal generator and a pseudo-random signal generator. The method comprises the steps that a digital signal sequence generated by a digital signal generator is subjected to Manchester coding and then is sent to one input end of an adder module after passing through an active low-pass filter, a pseudo-random signal sequence generated by a pseudo-random signal generator is sent to the other input end of the adder as an analog noise signal, the adder carries out superposition processing on two paths of input signals, the processed signals are directly sent to an oscilloscope through the output end of the adder, meanwhile, the processed signals are sent to a synchronous signal extraction module through a frequency selection network through the other output end of the adder, the signals are also output to the oscilloscope after being extracted by the synchronous signal extraction module, and then the two paths of input signals are observed through an oscilloscope display eye diagram, wherein the signals extracted by the synchronous signal extraction module play a role in adjusting and synchronizing the signals directly sent to the oscilloscope through the output end of the adder.

Finally, it should be noted that the above mentioned embodiments are only preferred embodiments of the present invention, and not intended to limit the present invention, and although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that the technical solutions described in the foregoing embodiments can be modified or some technical features can be replaced equally, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A digital signal transmission analyzer is characterized by comprising a complex programmable device, a clock signal generator, a digital signal generator, an active low-pass filter, a pseudo-random signal generator, an adder, a frequency selection network, a synchronous signal extraction module and an oscilloscope; one output end of the adder is connected with one input end of the oscilloscope, and the other output end of the adder is connected with the input end of the frequency selection network; the synchronous signal extraction module is used for extracting synchronous signals, and the synchronous signal extraction is realized by applying a phase-locked loop circuit after passing through a frequency selection network; the synchronization signal extraction module comprises a phase comparator, an M-time frequency divider, a narrow pulse former and an oscillator.

2. The digital signal transmission analyzer of claim 1 wherein said digital signal generator employs a shift register 74LS299 and an xor gate 74F86 chip.

3. The digital signal transmission analyzer of claim 1 wherein said pseudo-random signal generator employs a shift register 74F673 and an xor gate 74F86 chip.

4. A digital signal transmission analyzer according to claim 3 wherein the pseudo-random signal generator is adapted to receive the signals from the active low pass filter and the clock signal generator, generate m-sequences, code division multiple access, and transmit the m-sequences to the summer.

5. The digital signal transmission analyzer of claim 1, wherein said active low pass filter is a third order active low pass filter.

6. The digital signal transmission analyzer of claim 5, wherein said third order active low pass filter is formed by a first order low pass filter and a second order low pass filter in cascade.

7. The digital signal transmission analyzer of claim 1, wherein the complex programmable device is configured to divide to generate the clock signal.

8. The digital signal transmission analyzer of claim 7, wherein the clock signal is capable of step adjustment of the clock frequency by 4 peripheral dip switches.

9. A digital signal transmission analyzer according to claim 1 wherein the summer is formed by a proportional and homodyne summation circuit for receiving the signals transmitted by the active low pass filter and the pseudo-random signal generator.

10. The digital signal transmission analyzer of claim 1 wherein said frequency selective network employs LC circuits.