CN217561604U - CWD time frequency analysis implementation device - Google Patents

Abstract

The utility model provides a CWD time frequency analysis realization device, the device include, a signal buffer circuit, a cluster conversion circuit, a data preprocessing circuit and a Discrete Fourier Transform (DFT) circuit. The utility model provides a problem that analysis speed is slow when the tradition uses software calculation CWD, can carry out quick time frequency analysis to radar signal and other non-stationary signals for the arithmetic speed shortens the calculating time.

Description

CWD time frequency analysis implementation device

Technical Field

The utility model belongs to the technical field of signal analysis, be applicable to the time frequency analysis to nonstationary signals such as radar signal, more specifically relates to a CWD time frequency analysis realization device.

Background

In order to improve the analysis capability of radar signals and other non-stationary signals, the mainstream method at present is to use an analysis method based on time-frequency distribution and use a joint distribution function of time and frequency to describe the change relationship between the frequency and the time of the non-stationary signals. The existing time-frequency analysis methods are mainly divided into two types: linear methods and non-linear methods. Typical representatives of the linear method are short-time fourier transform (STFT), wavelet analysis (WF), etc. Typical representatives of the nonlinear method are the Wigner-Ville distribution (WVD) and the Choi-Williams distribution (CWD). The CWD time-frequency analysis has the characteristic of minimum cross-item interference in all unprocessed Cohen type distributions, and has stronger analysis capability on non-stationary signals such as radar signals, so that the CWD time-frequency analysis method is used for obtaining the time-frequency distribution of the non-stationary signals in many application scenes.

Although the CWD time-frequency analysis method can improve the analysis capability of the non-stationary signals, the non-stationary signals need to be subjected to two-dimensional distribution calculation, the calculation amount is huge, and the time consumption is long when software is used for calculating the non-stationary signals. The method has no problem in the scene with low real-time requirement, but the calculation time length is very important for the analysis of radar signals in electronic reconnaissance. Therefore, in order to shorten the calculation time and increase the calculation speed, it is necessary to use a novel CWD time-frequency analysis implementation apparatus to increase the calculation speed.

SUMMERY OF THE UTILITY MODEL

To CWD time frequency analysis method, the longer problem of software calculation time, the utility model provides a device is realized to CWD time frequency analysis uses hardware circuit to accomplish the calculation of CWD time frequency analysis, improves the computational speed, shortens calculation time, satisfies the demand when requiring higher application scene to the real-time. Therefore, the utility model adopts the following technical scheme:

a CWD time frequency analysis implementation device is characterized by comprising a signal buffer circuit, a serial-parallel conversion circuit, a data preprocessing circuit and a Discrete Fourier Transform (DFT) circuit;

the signal buffer circuit is connected with the serial-parallel conversion circuit and is used for buffering a time domain signal needing CWD time frequency analysis and providing the buffered time domain signal to the serial-parallel conversion circuit;

the serial-parallel conversion circuit is connected with the data preprocessing circuit and is used for converting serial time domain signals into parallel time domain signals and providing the parallel time domain signals to the data preprocessing circuit;

the data preprocessing circuit is connected with a Discrete Fourier Transform (DFT) circuit, and is used for preprocessing parallel time domain signals and providing the preprocessed signals to the DFT circuit.

Preferably, the CWD time-frequency analysis implementation apparatus is characterized in that the data preprocessing circuit includes a first memory circuit, a first multiplier circuit, an accumulator circuit, a second memory circuit, and a second multiplier circuit;

the first memory circuit is connected with the first multiplier circuit, and the first memory circuit provides coefficients required by calculation for the first multiplier circuit;

the first multiplier circuit is connected with the accumulator circuit, and the first multiplier circuit provides the calculated result to the accumulator circuit for accumulation;

said accumulator circuit is coupled to a second multiplier circuit and provides an accumulated result to said second multiplier circuit;

the second memory circuit is coupled to a second multiplier circuit for providing coefficients needed for the calculation to the second multiplier circuit.

Preferably, the data preprocessing circuit is characterized in that the first memory circuit stores a product result of a coefficient of a preset time-domain window function and a kernel function.

Preferably, the data preprocessing circuit is characterized in that the second memory circuit stores coefficients of a preset frequency domain window function.

The utility model provides an use hardware circuit to calculate the computing device that non-stationary signal time frequency distributes such as radar signal. Compare with the mode that software calculated, the utility model discloses the analysis realization device has obvious advantage in the computational rate when the CWD, has improved the computational rate greatly, consequently the utility model is suitable for an electronic reconnaissance etc. other require the real-time higher, and need acquire in the embedded system that non-stationary signal time frequency distributes.

Drawings

Fig. 1 is a block diagram illustrating the structure of the present invention.

Fig. 2 is a schematic block diagram of the data preprocessing circuit of the present invention.

Detailed Description

Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in fig. 1 and 2, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present invention, and should not be construed as limiting the present invention.

In order to fully understand the technical content of the present invention, specific embodiments are given below, and the technical solution of the present invention is described and explained in more detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of a CWD time-frequency analysis implementation device of the present invention, which comprises a signal buffer circuit 11 (e.g., SN74V283 memory chip of Texas Instruments (TI)), a serial-to-parallel conversion circuit 12 (e.g., SN74HCS596 shift register chip of TI), a data pre-processing circuit 13 and a Discrete Fourier Transform (DFT) circuit 14 (e.g., FFT chip dedicated to A41102, the FFT being fast algorithm of DFT);

the signal buffer circuit 11 is connected to the serial-parallel conversion circuit 12, and the signal buffer circuit 11 is configured to buffer a time domain signal to be subjected to CWD time frequency analysis and provide the buffered time domain signal to the serial-parallel conversion circuit 12;

the serial-parallel conversion circuit 12 is connected to the data preprocessing circuit 13, and the serial-parallel conversion circuit 12 is configured to convert a serial time domain signal into a parallel time domain signal and provide the parallel time domain signal to the data preprocessing circuit 13;

the data preprocessing circuit 13 is connected to a Discrete Fourier Transform (DFT) circuit 14, and the data preprocessing circuit 13 performs preprocessing operation on parallel time domain signals and provides the preprocessed signals to the DFT (DFT) circuit 14;

FIG. 2 is a schematic block diagram of a data preprocessing circuit of a CWD time-frequency analysis implementation apparatus of the present invention, which comprises a first memory circuit 21 (e.g., JBP28S42 bipolar PROM chip of TI), a first multiplier circuit 22 (e.g., mc1496 multiplier chip), an accumulator circuit 23 (e.g., SN54LS283 full adder chip of TI), a second memory circuit 24 (e.g., JBP28S42 bipolar PROM chip of TI), and a second multiplier circuit 25 (e.g., mc1496 multiplier chip); the serial-to-parallel conversion circuit 12 is connected to the first multiplier circuit 22 of the data preprocessing circuit, and provides parallel time domain signals.

The first memory circuit 21 is connected to a first multiplier circuit 22, and the first memory circuit 21 supplies coefficients required for calculation to the first multiplier circuit 22;

the first multiplier circuit 22 is connected to the accumulator circuit 23, and the first multiplier circuit 22 provides the calculated result to the accumulator circuit 23 for accumulation;

said accumulator circuit 23 is connected to a second multiplier circuit 25 and provides an accumulated result to said second multiplier circuit 25;

the second memory circuit 24 is connected to a second multiplier circuit 25, and supplies coefficients required for calculation to the second multiplier circuit 25;

the first memory circuit 21 stores a product result of a coefficient of a preset time domain window function and a kernel function;

the second memory circuit 24 stores coefficients of a predetermined frequency domain window function;

it should be understood that the technical contents of the present invention described above are further disclosed from the perspective of specific embodiments, which aim to make the contents of the present invention easier to understand, but do not represent embodiments of the present invention and the protection of the claims is limited thereto. The scope of protection of the invention is set forth in the appended claims, and all obvious modifications which are within the spirit of the invention are intended to be covered by the protection of the invention.

Claims (4)

1. A CWD time frequency analysis implementation device is characterized by comprising a signal buffer circuit, a serial-parallel conversion circuit, a data preprocessing circuit and a Discrete Fourier Transform (DFT) circuit;

the signal buffer circuit is connected with the serial-parallel conversion circuit and is used for buffering a time domain signal needing CWD time frequency analysis and providing the buffered time domain signal to the serial-parallel conversion circuit;

the serial-parallel conversion circuit is connected with the data preprocessing circuit and is used for converting serial time domain signals into parallel time domain signals and providing the parallel time domain signals to the data preprocessing circuit;

the data preprocessing circuit is connected with the discrete Fourier transform circuit, and carries out preprocessing operation on the parallel time domain signals and provides the preprocessed signals to the discrete Fourier transform circuit.

2. The apparatus for performing CWD time-frequency analysis of claim 1, wherein the data pre-processing circuitry comprises: a first memory circuit, a first multiplier circuit, an accumulator circuit, a second memory circuit, a second multiplier circuit;

the first memory circuit is connected with the first multiplier circuit, and the first memory circuit provides coefficients required by calculation for the first multiplier circuit;

the first multiplier circuit is connected with the accumulator circuit, and the first multiplier circuit provides the calculated result to the accumulator circuit for accumulation;

said accumulator circuit is coupled to a second multiplier circuit and provides an accumulated result to said second multiplier circuit;

the second memory circuit is coupled to a second multiplier circuit for providing coefficients needed for the calculation to the second multiplier circuit.

3. The apparatus of claim 2, wherein the first memory circuit stores a result of multiplying a kernel function by a coefficient of a predetermined time window function.

4. The apparatus of claim 2 wherein the second memory circuit stores coefficients of a predetermined frequency window function.

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