CN217468460U - Integrated chip and wearable device for noninvasive blood glucose detection - Google Patents

Abstract

The application discloses can be used to not invade integrated chip and wearing equipment that blood sugar detected, this application technical scheme with the different light source chips of light transmission subassembly, a plurality of luminous wave bands and a plurality of detector integration that are used for surveying different wave bands in same chip, form a monolithic and mix integrated chip. According to the technical scheme, the wide-spectrum blood glucose parameter detection can be realized through different light source chips of a plurality of light-emitting wave bands and a plurality of detectors for detecting different wave bands, so that the resolution and the test accuracy are improved; the transmission optical path design in the chip is realized by arranging the transmission components in the chip; and can realize the mixed integrated technology of light transmission subassembly, light source subassembly and optical detection subassembly and realize single-chip integration based on same SOI, the equipment miniaturization of being convenient for can reduce equipment volume and consumption, is applicable to the wearing equipment miniaturization and the design demand of low-power consumption.

Description

Integrated chip and wearing equipment that can be used to non-invasion blood sugar to detect

Technical Field

The application relates to the technical field of semiconductor devices, in particular to an integrated chip and wearable equipment for noninvasive blood glucose detection.

Background

Blood glucose test devices can be divided into two categories in use: the first type is invasive blood sugar detection equipment, which needs to collect a certain amount of blood when measuring the blood sugar value of a human body, has constant operation, can cause certain psychological stress on a detected person, and can bring infection risk; the second type is a non-invasive blood sugar detection device, which can determine the blood sugar level by measuring the absorption of the glycosylation matters in the human body to the light with specific wavelength when in use.

Compared with the invasive blood sugar detection equipment, the noninvasive blood sugar detection equipment has the advantages of safety, convenient operation, real-time display of detection results and the like, and becomes the main development direction of the blood sugar detection equipment. At present, a noninvasive blood glucose detecting device generally adopts an LED as a detecting light source, and detects blood glucose parameters based on visible light spectrum analysis, but due to the narrow spectral wavelength range available for analysis, the resolution of a detection result is low, and the data accuracy is insufficient.

SUMMERY OF THE UTILITY MODEL

In view of this, the present application provides an integrated chip and a wearable device for noninvasive blood glucose detection, and the scheme is as follows:

an integrated chip for non-invasive blood glucose testing, comprising:

a semiconductor substrate;

the first insulating layer is positioned on the surface of the semiconductor substrate;

a first functional layer on a surface of the first insulating layer facing away from the semiconductor substrate, the first functional layer comprising: the device comprises an optical modulation component, a first waveguide and an optical detection component;

a second functional layer on a side of the first functional layer facing away from the semiconductor substrate, the second functional layer comprising: a second waveguide;

a light source assembly coupled to the light transmitting assembly;

the optical modulation component and the optical detection component both comprise doped active structures; the light source assembly includes: a plurality of light source chips with different light-emitting wave bands; the light detection assembly includes: a plurality of detectors for detecting different wavelength bands; the semiconductor substrate has a light exit structure for exiting detection light and collecting reflected detection light.

Preferably, in the integrated chip, the light source module includes: a visible light source chip and an infrared light source chip; the light detection assembly includes: visible light detectors and infrared light detectors.

Preferably, in the integrated chip, the light modulation module includes: a MOS capacitive type electro-optical modulator;

a first polycrystalline silicon layer is arranged between the first functional layer and the second functional layer and comprises a grid of the MOS capacitance type photoelectric modulator;

and the first polycrystalline silicon layer is also used for forming an ion implantation window of an active structure in the first functional layer.

Preferably, in the integrated chip, the optical modulation component further includes: MZM type electro-optical modulators.

Preferably, in the integrated chip, the first functional layer is a monocrystalline silicon layer, and the first waveguide is a silicon waveguide;

the second functional layer is a silicon nitride layer, and the second waveguide is a silicon nitride waveguide.

Preferably, in the integrated chip, a top insulating layer is arranged on a side of the second functional layer away from the first functional layer, and a first trench and a second trench are arranged on the surface of the top insulating layer; the first groove is used for fixing a first light source chip, and the first light source chip is coupled with the first waveguide below the first groove; the second groove is used for fixing the second light source chip, and the second light source chip is coupled with the second waveguide below the second groove.

Preferably, in the integrated chip, the first functional layer further includes a grating; the side, away from the first functional layer, of the second functional layer is provided with a top insulating layer; the light source assembly is arranged on the top insulating layer; and an extended light source component can be arranged in the region of the surface of the top insulating layer opposite to the grating.

Preferably, in the integrated chip, a side of the first functional layer facing away from the semiconductor substrate has multiple insulating layers, and the second functional layer is located between two insulating layers;

the integrated chip further comprises a first wiring layer and a second wiring layer; the first wiring layer is positioned between two adjacent layers of the insulating layers and comprises a plurality of first signal lines; the optical detection assembly and the optical modulation assembly are respectively connected with the corresponding first signal line through a through hole; the second wiring layer is positioned on the surface of one side, away from the second functional layer, of the outermost insulating layer and comprises a plurality of second signal lines; the second signal line is connected with the first signal line through a through hole, and the second signal line is used for connecting an external circuit.

The application also provides a wearing equipment, includes:

a circuit board to which an electrical chip is connected;

the integrated chip of any one of the above claims, wherein the integrated chip is fixed on the circuit board and connected with the electrical chip;

the electrical chip is used for determining the biological characteristic parameters of the detection target based on the detection signals generated by the optical detection component for detecting the optical signals, and the biological characteristic parameters at least comprise blood sugar parameters.

According to the integrated chip and the wearable device, the light transmission assembly, the light source chips with different light-emitting wave bands and the detectors used for detecting the different wave bands are integrated in the same chip, and a single-chip hybrid integrated chip is formed. According to the technical scheme, the wide-spectrum blood glucose parameter detection can be realized through different light source chips of a plurality of light-emitting wave bands and a plurality of detectors for detecting different wave bands, so that the resolution and the test accuracy are improved; the transmission optical path design in the chip is realized by arranging the transmission components in the chip; and can realize that the mixed integrated technology of optical transmission subassembly, light source subassembly and optical detection subassembly realizes single-chip integration based On same SOI (Silicon-On-Insulator, the Silicon On the insulating substrate), the equipment miniaturization of being convenient for can reduce equipment volume and consumption, is applicable to the wearing equipment miniaturization and the design demand of low-power consumption.

Drawings

In order to more clearly illustrate the embodiments of the present application or technical solutions in related technologies, the drawings used in the embodiments or descriptions of the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

The structures, proportions, and dimensions shown in the drawings and described in the specification are for illustrative purposes only and are not intended to limit the scope of the present disclosure, which is defined by the claims, but rather by the claims, it is understood that these drawings and their equivalents are merely illustrative and not intended to limit the scope of the present disclosure.

Fig. 1-27 are process flow diagrams of a fabrication method provided by an embodiment of the present application;

FIG. 28 is a block diagram of an integrated chip for noninvasive glucose sensing according to an embodiment of the present disclosure;

fig. 29 is a schematic structural diagram of a wearable device provided in an embodiment of the present application.

Detailed Description

Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown, and in which it is to be understood that the embodiments described are merely illustrative of some, but not all, of the embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

As described in the background, the conventional non-invasive blood glucose detecting device generally uses an LED as a detecting light source to detect blood glucose parameters based on visible light spectrum analysis, but the resolution of the detecting result is low and the data accuracy is not sufficient due to the narrow spectrum wavelength range available for analysis.

In view of this, an embodiment of the present application provides an integrated chip for noninvasive blood glucose detection, and a manufacturing method and a wearable device thereof, where the manufacturing method includes:

providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a first insulating layer and a first film layer positioned on the surface of one side, away from the semiconductor substrate, of the first insulating layer;

patterning the first film layer to form a first functional layer, the first functional layer comprising: the device comprises an optical modulation component, a first waveguide and an optical detection component;

forming a second functional layer on a side of the first film layer facing away from the semiconductor substrate, the second functional layer comprising: a second waveguide;

forming a light source assembly coupled to a light delivery assembly, the light delivery assembly including the first waveguide and the second waveguide;

the optical modulation component and the optical detection component both comprise doped active structures; the light source assembly includes: a plurality of light source chips with different light-emitting wave bands; the light detection assembly includes: a plurality of detectors for detecting different wavelength bands; the semiconductor substrate has a light exit structure for exiting detection light and collecting reflected detection light.

According to the technical scheme, the wide-spectrum blood glucose parameter detection can be realized through different light source chips of a plurality of light-emitting wave bands and a plurality of detectors for detecting different wave bands, so that the resolution and the test accuracy are improved; the transmission optical path design in the chip is realized by arranging the transmission components in the chip; and can realize the mixed integrated technology of light transmission subassembly, light source subassembly and optical detection subassembly and realize single-chip integration based on same SOI, the equipment miniaturization of being convenient for can reduce equipment volume and consumption, is applicable to the wearing equipment miniaturization and the design demand of low-power consumption.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.

As shown in fig. 1 to fig. 27, fig. 1 to fig. 27 are process flow charts of a manufacturing method provided in an embodiment of the present application, the manufacturing method is used for preparing an integrated chip that can be used for non-invasive blood glucose testing, and the manufacturing method includes:

step S11: as shown in fig. 1, a semiconductor substrate 100 is provided, and the surface of the semiconductor substrate 100 has a first insulating layer 101 and a first film layer 102 on a surface of the first insulating layer 101 facing away from the semiconductor substrate 100.

In the embodiment of the present application, the integrated chip is directly fabricated by using an SOI wafer, the first insulating layer 101 is silicon oxide and has a thickness ranging from 1 μm to 3 μm, and the first film layer 102 is monocrystalline silicon and has a thickness ranging from 150nm to 500 nm.

Step S12: as shown in fig. 2-6, the first film layer 102 is patterned to form a first functional layer, which includes: the device comprises an optical modulation component, a first waveguide and an optical detection component.

In step S12, the method of forming the first functional layer includes:

first, as shown in fig. 2, a second insulating layer 103 and a third insulating layer 104 are sequentially formed on a surface of the first film layer 102 facing away from the semiconductor substrate 100.

A thermal oxide layer with a thickness of 5nm to 50nm may be grown on the surface of the first film 102 as the second insulating layer 103, and a SiN layer may be formed on the surface of the second insulating layer 103 by a deposition process such as LPCVD as the third insulating layer 104. The thickness of the SiN layer is 10nm-200 nm. In the embodiment of the present application, each oxide layer is silicon oxide.

Then, as shown in fig. 3, the second insulating layer 103 and the third insulating layer 104 are patterned. A layer of photoresist may be formed on the surface of the third insulating layer 104 by using a photolithography process, and after the photoresist is patterned based on a mask, the second insulating layer 103 and the third insulating layer 104 are etched based on the photoresist.

As shown in fig. 4, etching the first film layer 102 based on the patterned second insulating layer 103 and the patterned third insulating layer 104 to form the first functional layer; the first functional layer comprises a plurality of waveguide structures with different etching depths so as to form the first waveguide, the light modulation component and the light detection component.

As shown in fig. 5, fig. 5 is a schematic diagram illustrating an etching principle of a first film layer 102 according to an embodiment of the present disclosure, in fig. 5, (a) shows a shallow-etched waveguide structure, (b) shows a deep-etched waveguide unit, and (c) shows a full-etched waveguide unit, by etching three waveguide structures with different etching depths on the first film layer 102, various optical chip structures, including but not limited to those used for manufacturing an optical detection assembly, an optical modulation assembly, and a first waveguide, can be constructed through the same first film layer 102.

Finally, as shown in fig. 6 and 7, a planarized fourth insulating layer 105 is formed on a side of the first insulating layer facing away from the semiconductor substrate, and the fourth insulating layer 105 covers the first functional layer. Specifically, as shown in fig. 6, an oxide layer is formed on the first functional layer as the fourth insulating layer 105 by a deposition process such as CVD, and the etched waveguide unit in the first film layer 102 may be subjected to sidewall oxidation, and then the fourth insulating layer 105 is deposited and filled. As shown in fig. 7, the fourth insulating layer 105 is planarized by a CMP process so that the fourth insulating layer 105 is flush with the surface of the third insulating layer 104.

Step S13: as shown in fig. 8 to 17, a second functional layer is formed on a side of the first film layer facing away from the semiconductor substrate, and the second functional layer includes: a second waveguide;

as shown in fig. 8 and 9, the light detection assembly includes a MOS capacitor type photoelectric modulator 1021; before forming the second functional layer, the method further comprises: as shown in fig. 8, the third insulating layer 104 is removed to expose the second insulating layer 103; as further shown in fig. 9, the active structure of the MOS capacitance type electro-optical modulator 1021 is doped. When the SiN layer is used as the third insulating layer 104, the third insulating layer 104 may be removed by dry etching or a hot phosphoric acid etching cleaning process.

As described above, the surface of the first functional layer facing away from the semiconductor substrate 100 has the second insulating layer 103; in step S13, the method of forming the second functional layer includes:

step S21, as shown in fig. 10 to 13, forming a patterned first polysilicon layer 106 on a side surface of the second insulating layer 103 facing away from the first functional layer, where the first polysilicon layer 106 includes: the window sacrificial layer 1061.

Before forming the first polysilicon layer 106, the fourth insulating layer 105 may be planarized such that the fourth insulating layer 105 and the second insulating layer 103 are flush.

Specifically, as shown in fig. 10 and 10, a first polysilicon layer 106 is formed on the surface of the third insulating layer 105, and then as shown in fig. 11 and 12, the first polysilicon layer is etched by using a mask 107, the first polysilicon layer 106 is patterned, and the first polysilicon layer above the undoped active structure is retained as a window sacrificial layer 1061. Finally, as shown in fig. 13, after removing the mask 107, the first polysilicon layer 106 is etched to fill the oxide layer 108, and then planarized so that the oxide layer 108 is flush with the first polysilicon layer 106. The oxide layer 108 may be formed by a CVD process and planarized by a CMP process.

In a subsequent ion implantation process, the window sacrificial layer 1061 is used to form an ion implantation window of the active structure in the first functional layer.

The first polysilicon layer 106 may be formed using an LPCVD process to a thickness of 20nm to 300 nm. The etched first polysilicon layer 106 includes: a window sacrificial layer 1061, a gate 1062 of the MOS capacitance type electro-optical modulator 1021, and a first coupling sacrificial layer 1063. The first polysilicon layer 106 is also deposited on the back side of the semiconductor substrate 100, and the first polysilicon layer 106 on the back side of the semiconductor substrate 100 needs to be removed.

Step S22, as shown in fig. 14 and 15, a fifth insulating layer 109 and a second film layer 110 are sequentially formed on the side of the first polysilicon layer 106 away from the first functional layer.

First, as shown in fig. 14, another oxide layer may be formed on the surfaces of the first polysilicon layer 106 and the oxide layer 108 by a CVD process as a fifth insulating layer 109, the fifth insulating layer 109 is a high-temperature thermal oxide layer, the film layer is dense, and the high-temperature annealing process for forming the second waveguide subsequently and the subsequent active processes such as a silicide process and a Ge epitaxy process may be used as a better barrier layer for contamination diffusion, so as to prevent diffusion from entering the SOI waveguide structure (i.e., the waveguide structure of the first functional layer), and avoid the problem of transmission loss deterioration of the SOI waveguide structure due to diffusion. The thickness of the fifth insulating layer 109 is 10nm to 300 nm.

As shown in fig. 15, a silicon nitride waveguide layer is formed on the surface of the fifth insulating layer 109 by PECVD or LPCVD process as the second layer 110, wherein the thickness of the silicon nitride waveguide layer is 100nm-1000 nm. When the silicon nitride waveguide layer is formed, the silicon nitride waveguide layer can be grown for multiple times in a segmented mode, so that the second film layer comprises a plurality of laminated sub-film layers, the stress of the film layer is reduced, the thickness of the film layer is improved, and meanwhile the distribution uniformity of RI (refractive index parameter) can be improved. After the silicon nitride waveguide layer is formed, a furnace tube annealing process treatment is carried out on the silicon nitride waveguide layer at the temperature of 800-1200 ℃ to remove and reduce Si-H and N-H bonds of the silicon nitride waveguide layer in the deposition process, so that the transmission loss of the silicon nitride waveguide layer is reduced. The time of the annealing treatment is 0.5 hours to several hours, and the annealing treatment may be performed in a plurality of times.

Step S23, as shown in fig. 16, the second film layer 110 is patterned to form the second functional layer.

The second film layer 110 may be patterned using a photolithography process to form a second waveguide having a desired pattern structure. The annealing of the silicon nitride waveguide layer may be performed before patterning the second layer 110 or after patterning the second layer 110. The mechanism of reducing transmission loss by annealing after etching the silicon nitride waveguide layer is the same as that by annealing before etching.

Optionally, the second functional layer includes a plurality of second waveguides with different etching depths, for example, the second functional layer may be configured to include a partially etched second waveguide WG1 and a fully etched second waveguide WG 2. The thickness of the second waveguide WG1 which is partially etched is set to be 150nm-250nm, so that a single-mode condition which is good for visible light is formed, and the subsequent spectral analysis of a visible light wave band is formed. The fully etched second waveguide WG2 enables a single mode condition to be formed that is better for the near-infrared NIR and mid-infrared MIR bands of the infrared IR, resulting in a subsequent spectral analysis of the near-infrared NIR and mid-infrared MIR bands of the infrared IR. Particularly, a certain over-etching amount of the lower oxide layer can be formed in the dry etching process of the silicon nitride waveguide layer, and the etching ratio of the etching gas of the SiN material to the polycrystalline silicon is very low, so that the first polycrystalline silicon layer can also be used as an etching protective layer of the silicon nitride waveguide layer, and the damage to the key SOI waveguide structure at the bottom in the etching process of the silicon nitride waveguide layer is avoided.

Step S14: as shown in fig. 17-27, a light source module is formed that is coupled to a light delivery assembly that includes the first waveguide and the second waveguide, forming a chip structure as shown in fig. 27.

The optical modulation assembly and the optical detection assembly respectively comprise doped active structures; the light source assembly includes: a plurality of light source chips having different light emission bands; the light detection assembly includes: a plurality of detectors for detecting different wavelength bands; the semiconductor substrate has a light exit structure for exiting detection light and collecting reflected detection light.

As mentioned above, a patterned first polysilicon layer 106 is provided between the first functional layer and the second functional layer, and the optical detection component includes a MOS capacitor type photoelectric modulator 1021; the first polysilicon layer 106 further includes a gate 1062 of the MOS capacitor type electro-optical modulator 1021. The first polysilicon layer 106 includes: 1061 window sacrificial layer. Based on this, the method for forming the active structure comprises the following steps:

step S31: as shown in fig. 17 to 20, an ion implantation window K is formed in the insulating layer on the side of the window sacrificial layer 1061 facing away from the first functional layer, and the ion implantation window K exposes the window sacrificial layer 1061;

specifically, first, as shown in fig. 17, a planarized sixth insulating layer 111 is formed on the side of the second functional layer away from the first functional layer.

Forming an oxide layer serving as a sixth insulating layer 111 by using a CVD (chemical vapor deposition) process, wherein the sixth insulating layer 111 covers the second waveguide and fills the hollow areas between the second functional layers; and then, carrying out planarization treatment on the sixth insulating layer 111 through a CMP process, wherein after the planarization treatment, the minimum distance between the second functional layer and the sixth insulating layer is 50nm-500 nm.

As further shown in fig. 18, the manufacturing method according to the embodiment of the present application further includes: and forming a patterned second polysilicon layer 112 on the planarized surface of the sixth insulating layer 111, wherein the patterned second polysilicon layer is used as an etching barrier layer for forming a trench for placing a light source assembly in a subsequent process. The thickness of the second polysilicon layer 112 is 20nm-300nm, and the second polysilicon layer 112 with a required pattern structure is formed through a photolithography process.

The patterned second polysilicon layer 112 may be used as a deep etching barrier layer for opening a thicker oxide layer above the waveguide in a subsequent process to form a deep trench for placing light source chips in the light source assembly, the light source chips including compound light source chips, such as a group III-V InP semiconductor Laser (LD), a VCSEL (vertical cavity surface emitting laser) structured visible or infrared light source chip, or a GaSb mid-infrared light source chip, to construct monolithic integration of the visible/infrared/mid-infrared light source.

It should be noted that, in other manners, the second polysilicon layer 112 may not be provided, and the etching depth of the deep trench may be controlled by controlling parameters such as the etching speed.

As further shown in fig. 19, an oxide layer 113 is formed covering the sixth insulating layer 111 and the second polysilicon layer 112. The oxide layer 113 may be formed by a deposition process.

As shown in fig. 20, an ion implantation window K exposing the window sacrificial layer 1061 is formed by an etching process. The insulating layer above the window sacrificial layer 1061 may be removed by photolithography and dry etching. When the dry method ion etching process in the CMOS process is adopted, the oxide layer and the polysilicon can form high etching selection ratio. When etching the oxide layer above the window sacrificial layer 1061, the etching gas (including CF) with high selection ratio of selective oxide layer/polysilicon ₄ And/or CHF ₃ ) And an etching process, wherein the oxide layer above the window sacrificial layer 1061 is etched off, and the etching is stopped at the window sacrificial layer 1061, and a certain amount of etching is performed on the window sacrificial layer 1061 in the etching process.

Step S32: as shown in fig. 21, the window sacrificial layer 1061 is removed based on the ion implantation window K.

When the window sacrificial layer 1061 is removed by etching, an etching gas (including HBr) having a high selectivity ratio of the polysilicon/selective oxidation layer and an etching process are selected to etch away the remaining window sacrificial layer 1061.

Step S33: as shown in fig. 22, after removing the window sacrificial layer 1061, ion implantation is performed based on the ion implantation window K to dope the active structure under the ion implantation window K.

According to the technical scheme, the ion implantation window K is formed through the first polycrystalline silicon layer 106, so that the process integration scheme of the ion implantation of the active structure in the SOI waveguide structure is completed conveniently.

Wherein the optical detection assembly comprises an MZM (mach-zehnder) type electro-optical modulator 1022. The light detection assembly includes: a visible light detector 1023 and an infrared light detector 1024. For convenience of illustration in fig. 22, the visible light detector 1023 and the MZM type photoelectric modulator 1022 are shown based on the same waveguide structure, and obviously, the positions of the detector and the modulator can be arranged based on the requirement of the waveguide structure layout in the first functional layer, and the arrangement is not limited to the manner shown in fig. 22.

Visible light detector 1023 includes a silicon PN junction photodiode and/or a silicon Avalanche Photodiode (APD). The infrared light detector 1024 may be a Ge Photodiode (PD).

Based on the ion implantation window K, when ion implantation is performed, ion implantation is performed on respective corresponding active structures of the MZM type photoelectric modulator 1022, the visible light detector 1023, and the infrared light detector 1024 below the ion implantation window K, so as to implement doping of the corresponding active structures.

In the technical scheme of the application, the first polysilicon layer 106 can be reused as an etching barrier layer of the etching barrier layer insulating layer when the ion implantation window K is formed, and the etching quality is ensured. The oxide layer and the polysilicon can form a high etching selection ratio, and the oxide layer and the window sacrificial layer 1061 above the window sacrificial layer 1061 are removed by dry ion etching in sequence, so that the etching stop position can be accurately controlled, and the etching quality is ensured.

Based on the ion implantation window K, after ion implantation is completed, the manufacturing method further includes: an epitaxially grown layer of the infrared light detector 1024 is formed. Specifically, as shown in fig. 23, the doped active structure of the infrared light detector 1024 is patterned, a groove C is formed on the doped active structure of the infrared light detector 1024, and then as shown in fig. 24, the epitaxial growth layer 114 of the infrared light detector 1024 is formed in the groove C. When the infrared light detector 1024 may be a Ge photodiode, the epitaxially grown layer is a Ge layer. Before forming the groove C, an oxide layer is deposited on the surface of the second insulating layer 103 exposed at the bottom of the ion implantation window, the thickness of the oxide layer is 10nm-300nm, the thickness of the insulating layer above the active structure of the infrared light detector 1024 is increased, and the influence of downward diffusion of the epitaxial growth layer 114 outside the groove C on the SOI waveguide structure below is avoided.

After the epitaxial growth layer 114 of the infrared light detector 1024 is formed, an oxide layer filling the ion implantation window K is formed, the oxide layer covers the insulating layer (the above oxide layer 113) outside the ion implantation window K, and then the oxide layer on the surface of the chip is planarized by a CMP process.

And after the ion implantation window K is filled and the planarization treatment is finished, forming the interconnection of the multiple metal layers of the chip. Specifically, an insulating layer is arranged on one side of the first functional layer, which is far away from the semiconductor substrate, and the second functional layer is positioned between the two insulating layers; as shown in fig. 25, the manufacturing method further includes: a first wiring layer 116 and a second wiring layer 117 are formed. The first wiring layer 116 is located between two adjacent insulating layers and includes a plurality of first signal lines; the optical detection component and the optical modulation component are respectively connected with the corresponding first signal line 116 through a through hole; the second wiring layer 117 is located on a side surface of the top insulating layer 115 facing away from the second functional layer, and includes a plurality of second signal lines; the second signal line is connected with the first signal line through a through hole, and the second signal line is used for connecting an external circuit.

The side of the first functional layer facing away from the semiconductor substrate has multiple insulating layers, and the first wiring layer 116 may be disposed between any two insulating layers according to the wiring requirement. The interconnection of the multiple metal layers of the chip can be realized through the related processes of the CMOS and the silicon optical chip, and the embodiment of the application is not repeated.

In the embodiment of the present application, as shown in fig. 25, a patterned first polysilicon layer 106 is disposed between the first functional layer and the second functional layer, where the first polysilicon layer 106 includes: a first coupling sacrificial layer 1063; a second coupling sacrificial layer is arranged on one side of the second functional layer, which is far away from the first functional layer, and the second polysilicon layer 112 comprises a second coupling sacrificial layer 1121; the second coupling sacrificial layer 1121 has a top insulating layer 115 on a side facing away from the second functional layer. Based on this, the method for coupling the light source assembly and the transmission assembly comprises the following steps:

first, as shown in fig. 26, a first groove 118 is formed based on the first coupling sacrificial layer 1063, and the first coupling sacrificial layer 1063 is removed, the first groove 118 is located above the first waveguide, and the first groove 118 is used to fix the first light source chip 119. The oxide layer above the first coupling sacrificial layer 1063 is etched by photolithography and dry etching, and then the remaining first coupling sacrificial layer 1063 is etched by dry etching using a polysilicon/oxide layer high selectivity ratio, and the process of forming the first trench 118 is the same as the process of forming the ion implantation window K, and is not described herein again. After the first trench 118 is formed, a first light source chip 119 is bonded in the first trench 118 by using a die-to-wafer bonding (die-to-wafer bonding) process and fixed in the first trench 118, thereby coupling the light source chip with the waveguide. For example, after a visible light source chip is fixed in the second trench 120 opened on the SOI wafer through an inter-wafer bonding process, the visible light source enters the SiN waveguide through butt-Coupling end-face Coupling or evanescent-wave Coupling (evanescent-field Coupling), and is transmitted to the optical modulation component in the chip through the SiN waveguide to be processed, so as to form a light source with a required characteristic wavelength, and then is transmitted to the light outlet structure through the SiN edge coupler to be led out. The SOI waveguide structure under the first polysilicon layer 106 may play a role in heat dissipation, enhancing the thermal reliability of the visible light source chip.

As shown in fig. 27 again, a second trench 120 is formed based on the second coupling sacrificial layer 1121, and the second coupling sacrificial layer 1121 is removed, where the second trench 120 is located above the second waveguide and is used for fixing the second light source chip 121. The process is the same as the principle of forming the first trench 118, and the description of the embodiment of the present application is omitted.

Also, the second light source chip 121 is bonded and fixed in the second groove 120 in an integrated manner of an inter-wafer bonding process, and the light source chip is coupled with the waveguide. For example, after an InP infrared chip or a GaSb mid-infrared light source chip is fixed in the second trench structure 120 formed in the SOI wafer by an inter-wafer bonding process, infrared light is coupled into an SiN waveguide or an SOI waveguide through end-to-end coupling or evanescent coupling of a butt joint, and a required characteristic wavelength light source is formed through processing of optical components such as the SiN waveguide, the SOI waveguide, a modulator and the like; specifically, for example, an optical frequency comb signal with a characteristic wavelength is formed, and then is guided out from the optical port structure through the SiN edge coupler, and then is irradiated into a biological sample or human skin through an optical element such as an external optical microlens. The infrared light source chips are integrated by the same scheme so as to enhance the spectrum detection performance of a specific wave band. The light modulation component converts the emergent light of the light source chip into a light frequency comb signal with characteristic wavelength, and the required biological parameters are determined based on the absorption spectrum of the target to the characteristic wave band.

The first light source chip 119 and the second light source chip 120 have different light emission bands. The first light source chip 119 is provided as an infrared light source chip in view of the first waveguide of single crystal silicon being capable of transmitting infrared light, and the second light source chip 121 is provided as a visible light source chip in view of the second waveguide of silicon nitride being capable of transmitting visible light as well as infrared light. The visible light source chip includes a visible light LD and/or a VCSEL chip. The infrared light source chip comprises a III-V group or GaSb detector chip.

In the embodiment of the application, the visible light source chip can emit visible light with a full spectrum so as to realize biological parameter detection under the full spectrum of the visible light. The infrared light emitted by the infrared light source chip comprises one or more of far infrared band, near infrared band and intermediate infrared band, so as to realize biological parameter detection of the infrared band. The integrated chip in the embodiment of the present application is not limited to blood glucose parameter detection, and may also determine the ratio of biological components, such as fat, protein, and other substance components, based on spectral analysis of the detected light, such as absorption of characteristic waves.

As shown in fig. 27, the first functional layer further comprises a grating 1025; the side of the second functional layer facing away from the second functional layer has a top insulating layer 115; the area of the surface of the top insulating layer 115 opposite to the grating 1025 can be provided with an extended light source component, so that the extension of the subsequent detection light wave band of the integrated chip can be realized.

Based on the foregoing embodiment, another embodiment of the present application further provides an integrated chip for noninvasive blood glucose monitoring, which can be manufactured by the manufacturing method of the foregoing embodiment, as shown in fig. 28, where fig. 28 is a schematic structural diagram of an integrated chip for noninvasive blood glucose monitoring provided by the present application embodiment, and the integrated chip includes:

a semiconductor substrate 100;

a first insulating layer 101 on the surface of the semiconductor substrate 100;

a first functional layer located on a surface of the first insulating layer 101 facing away from the semiconductor substrate 100, the first functional layer including: the optical modulation component, the first waveguide and the optical detection component; the first functional layer may be prepared based on the first film layer 102 as described above;

a second functional layer located on a side of the first functional layer facing away from the semiconductor substrate 100, the second functional layer comprising: a second waveguide; as described above, the second functional layer may be prepared based on the second film layer 110;

a light source assembly coupled to the light transmitting assembly;

the optical modulation component and the optical detection component both comprise doped active structures; the light source assembly includes: a plurality of light source chips having different light emission bands; the light detection assembly includes: a plurality of detectors for detecting different wavelength bands; the semiconductor substrate has a light exit structure 122 for exiting the detection light and collecting the reflected detection light. The light exit structure 122 may be provided based on the layout of the light transmission components to the transmission light path in the chip, so that the light exit structure 122 is not limited to the layout position shown in fig. 28.

Optionally, the light source assembly comprises: a visible light source chip and an infrared light source chip; the light detection assembly includes: the integrated chip can realize biological parameter detection of visible light wave band and biological parameter detection of infrared light wave band.

Optionally, the light modulation component includes: a MOS capacitance type photoelectric modulator 1021; a first polysilicon layer 106 is arranged between the first functional layer and the second functional layer, and the first polysilicon layer 106 comprises a grid 1062 of the MOS capacitance type photoelectric modulator. Also as described in the above embodiments, the first polysilicon layer 106 is also used to form an ion implantation window for the active structure in the first functional layer.

In the integrated chip, the light modulation assembly further includes: MZM type electro-optical modulator 1022. Therefore, the integrated chip can selectively perform characteristic wave modulation through one or more of the MOS capacitance type optical modulator 1021 and the MZM type optical modulator 1022.

In the integrated chip, the first functional layer is a monocrystalline silicon layer, and the first waveguide is a silicon waveguide and can transmit infrared light; the second functional layer is a silicon nitride layer, and the second waveguide is a silicon nitride waveguide capable of transmitting infrared light and visible light.

In the embodiment of the present application, a side of the second functional layer facing away from the first functional layer is provided with a top insulating layer 115, and a surface of the top insulating layer 115 is provided with a first trench 118 and a second trench 120; the first trench 118 is used for fixing a first light source chip 119, and the first light source chip 119 is coupled with the first waveguide below the first trench 118; the second groove 120 is used to fix the second light source chip 121, and the second light source chip 121 is coupled to the second waveguide under the second groove 120.

In the embodiment of the present application, the first functional layer further includes a grating 1025; the side of the second functional layer facing away from the first functional layer has a top insulating layer 115; the area of the surface of the top insulating layer 115 opposite to the grating 1025 can be provided with an extended light source component, so that the subsequent detection optical band extension of the integrated chip can be realized.

In the integrated chip, one side of the first functional layer, which is far away from the semiconductor substrate, is provided with a plurality of insulating layers, and the second functional layer is positioned between two insulating layers;

the integrated chip further comprises a first wiring layer 116 and a second wiring layer 117; the first wiring layer 116 is located between two adjacent layers of the insulating layers and includes a plurality of first signal lines; the optical detection assembly and the optical modulation assembly are respectively connected with the corresponding first signal line through a through hole; the second wiring layer 117 is positioned on the surface of the outermost insulating layer on the side away from the second functional layer and comprises a plurality of second signal lines; the second signal line is connected with the first signal line through a through hole, and the second signal line is used for connecting an external circuit.

The integrated chip can cover visible light, near infrared light and intermediate infrared light, can be extended to terahertz wavelength, and can deduce biological parameters such as blood sugar level and the like based on the attenuation degree of detection light when penetrating through tissues of specific parts of a human body.

The integrated chip is a single-chip mixed integrated chip scheme, and by adopting a general CMOS process platform and a typical optical chip structure and process, visible light analysis (Vis), near infrared/infrared spectrum analysis (NIR/IR), mid-infrared (MIR) and other wave band semiconductor light-emitting chips and detection components can be integrated on the same SOI wafer, so that the SOI-SiN-InP-GaSb single-chip mixed integrated chip for non-invasive blood sugar detection is constructed.

An important application of the integrated chip is that the integrated chip can be integrated with an electric chip and various optical elements for packaging to realize the nondestructive detection of the blood sugar of a human body. The blood sugar level of the human body is stable at a specific part, the absorptivity of specific glycosylation matters to near-infrared light with specific wavelength is different, and the blood sugar level of the human body can be deduced through the spectral absorption analysis of the attenuated visible light/near-infrared light/mid-infrared light and other wide wave bands. The technical scheme of the application considers that the semiconductor light-emitting chip and the detection chip of each wave band such as visible light analysis (Vis), near infrared/infrared spectrum analysis (NIR/IR), intermediate infrared (MIR) and the like are all installed in a wearable device with limited volume, small volume and power consumption need to be kept, so that a scheme which can be really integrated by a single chip and a chip structure which is integrated by a single chip are provided, and a method for realizing the single chip mixing integration process based on an SOI wafer is realized, so that the integration of the multi-wave band spectrum analysis on the single chip is realized, the volume of the human blood sugar nondestructive detector is reduced, the cost is reduced, and the detector can be used in hospitals, communities and household environments.

Based on the integrated chip in the foregoing embodiment, another embodiment of the present application further provides a wearable device, as shown in fig. 29, fig. 29 is a schematic structural diagram of the wearable device provided in the embodiment of the present application, where the wearable device includes:

a circuit board 23, the circuit board 23 being connected with an electrical chip 22;

in the integrated chip 21 of the above embodiment, the integrated chip 21 is fixed on the circuit board 23 and connected to the electric chip 22; the integrated chip 21 and the electrical chip 22 are electrically connected by a circuit in the circuit board 23.

The electrical chip 22 is configured to determine a biometric parameter of the detection target based on a detection signal generated by the optical detection component detecting the optical signal, where the biometric parameter at least includes a blood glucose parameter. The wearable device includes, but is not limited to, a smart bracelet, a smart watch, and the like. In fig. 29, the realized arrows indicate the detection light reflected by the integrated chip 21, and the dotted arrows indicate the light collected by the integrated chip 21 and returned by the detection target.

A variety of said electric chips 22 with logic control and analysis functions can be used, said point chips comprising: TIA (transimpedance amplifier) chip, a/D (analog-to-digital) conversion chip, DSP (digital processing numerical analysis) chip, communication chip, and the like.

After the detection light emitted by the integrated chip 21 irradiates the detection target (such as human body tissue), the detection light returned by the detection target, including any one of the detection light returned by the detection target in reflection, scattering and transmission light, can be collected. Analyzing and detecting absorption spectrum in the light detection assembly through a light sensing chip, and converting the characteristic spectrum information of the collected detection light into corresponding electric signals; the TIA chip is used for amplifying the electric signals of the characteristic spectrums and filtering noise; the A/D conversion chip is used for converting the amplified electric signals into digital signals; the DSP chip is used for analyzing and processing the digital signals to obtain biological parameters; the communication chip is used for realizing the communication of wearing equipment and external equipment.

Wherein, each chip in the electric chip 22 can realize 2.5D or 3D packaging through a glass or silicon-based adapter plate, and is packaged into a small standard module together with some optical elements such as a reflector 24, a micro lens 25 and the like; thereby realize the miniaturization of equipment, keep little volume and consumption, realize the application at wearable demands such as healthy bracelet or wrist-watch.

The light returning from the detection target enters the integrated optical chip 21 through the focusing of the detection target mirror and the reflection of the reflection mirror 24, and is processed into separate signals with single wavelength through the wavelength modulation and decoupling processing in the integrated chip, such as typical components of the optical chip like Arrayed Waveguide Grating (AWG), and the like, so that the light intensity data of each wavelength is detected and analyzed by the optical detection components in the integrated chip, such as a silicon PN junction detection diode, a silicon APD diode, Ge PD, and the like, and finally, the absorption spectrum data capable of representing the required biological parameters is analyzed and obtained through the analysis of the electric chip 22.

In conventional wearable devices, light is typically directed to your skin through an LED, and the returning scattered light is monitored to measure pulse and even blood oxygen levels. However, the sensors in these wearable devices are not medical grade, and can only perform spectral analysis detection in the visible light band, and the detection accuracy is low. If with the LED and the detection chip of visible light, the transmission chip and the detection chip of infrared light, the transmission chip and the detection chip of intermediate infrared adopt independent technology to make into the chip of separation, encapsulate into independent light path respectively, though can increase detection spectral range, but chip system is complicated, and the volume is great, is difficult to realize miniaturization and wearable integration. Semiconductor light emitting chips and detection chips of various wave bands such as visible light analysis (Vis), near infrared/infrared spectrum analysis (NIR/IR), intermediate infrared (MIR) and the like are required to be arranged in a wearable bracelet or watch with limited volume, and small volume and small power consumption are also required, which is very difficult.

This application embodiment the integrated chip can regard as the optical sensor of high accuracy, can also regard as visible light and infrared spectral analysis spectrophotometer, can not have the wound and survey skin below, analyzes to compositions such as blood to more human index of monitoring, the spectral range that can supply the analysis is wide, and the detection and analysis result accuracy is high. The light source assemblies and the light detection assemblies are integrated in the same semiconductor chip, miniaturization is achieved, the light source assemblies can be integrated into a wearable bracelet and a watch, and biological characteristic data such as blood sugar can be monitored all day at any time and any place. The wearable device can achieve continuous and non-invasive monitoring of multi-mode biological parameter detection, such as lactic acid, glucose, hydration, blood pressure, core body temperature and the like.

The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other.

It should be noted that in the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only used for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be configured and operated in a specific orientation, and thus, should not be construed as limiting the present application. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (9)

1. An integrated chip for noninvasive blood glucose testing, comprising:

a semiconductor substrate;

a first insulating layer on the surface of the semiconductor substrate;

a first functional layer located on a surface of the first insulating layer on a side facing away from the semiconductor substrate, the first functional layer including: the optical modulation component, the first waveguide and the optical detection component;

a second functional layer on a side of the first functional layer facing away from the semiconductor substrate, the second functional layer comprising: a second waveguide;

a light source assembly coupled to the light transmitting assembly;

the optical modulation component and the optical detection component both comprise doped active structures; the light source assembly includes: a plurality of light source chips having different light emission bands; the light detection assembly includes: a plurality of detectors for detecting different wavelength bands; the semiconductor substrate has a light exit structure for exiting detection light and collecting reflected detection light.

2. The integrated chip of claim 1, wherein the light source assembly comprises: a visible light source chip and an infrared light source chip; the light detection assembly includes: visible light detectors and infrared light detectors.

3. The integrated chip of claim 1, wherein the light modulation component comprises: a MOS capacitive type electro-optical modulator;

a first polycrystalline silicon layer is arranged between the first functional layer and the second functional layer and comprises a grid of the MOS capacitance type photoelectric modulator;

and the first polycrystalline silicon layer is also used for forming an ion implantation window of an active structure in the first functional layer.

4. The integrated chip of claim 3, wherein the light modulation component further comprises: MZM type electro-optical modulators.

5. The integrated chip of claim 1, wherein the first functional layer is a single crystal silicon layer and the first waveguide is a silicon waveguide;

the second functional layer is a silicon nitride layer, and the second waveguide is a silicon nitride waveguide.

6. The integrated chip of claim 1, wherein a side of the second functional layer facing away from the first functional layer has a top insulating layer, a surface of the top insulating layer having a first trench and a second trench; the first groove is used for fixing a first light source chip, and the first light source chip is coupled with the first waveguide below the first groove; the second groove is used for fixing a second light source chip, and the second light source chip is coupled with the second waveguide below the second groove.

7. The integrated chip of claim 1, wherein the first functional layer further comprises a grating; the side, away from the first functional layer, of the second functional layer is provided with a top insulating layer; the light source assembly is arranged on the top insulating layer; and an extended light source component can be arranged in the region of the surface of the top insulating layer opposite to the grating.

8. The integrated chip of claim 1, wherein a side of the first functional layer facing away from the semiconductor substrate has a plurality of insulating layers, and the second functional layer is located between two of the insulating layers;

the integrated chip further comprises a first wiring layer and a second wiring layer; the first wiring layer is positioned between two adjacent layers of the insulating layers and comprises a plurality of first signal lines; the optical detection assembly and the optical modulation assembly are respectively connected with the corresponding first signal line through a through hole; the second wiring layer is positioned on the surface of one side, away from the second functional layer, of the insulating layer on the outermost layer and comprises a plurality of second signal lines; the second signal line is connected with the first signal line through a through hole, and the second signal line is used for connecting an external circuit.

9. A wearable device, comprising:

a circuit board connected with an electrical chip;

the integrated chip of any of claims 1-8, said integrated chip being secured to said circuit board in connection with said electrical chip;

the electrical chip is used for determining the biological characteristic parameters of the detection target based on the detection signals generated by the optical detection component for detecting the optical signals, and the biological characteristic parameters at least comprise blood sugar parameters.

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