CN217467494U - Anti-electromagnetic interference device of intelligent door lock - Google Patents
Anti-electromagnetic interference device of intelligent door lock Download PDFInfo
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- CN217467494U CN217467494U CN202122902647.1U CN202122902647U CN217467494U CN 217467494 U CN217467494 U CN 217467494U CN 202122902647 U CN202122902647 U CN 202122902647U CN 217467494 U CN217467494 U CN 217467494U
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Abstract
An anti-electromagnetic interference device of an intelligent door lock. The device comprises a control module and a detection module, wherein the detection module comprises an external circuit and a key circuit, and the key circuit comprises a first key circuit and a second key circuit; the first key circuit, the second key circuit and the control module are connected with an external circuit at the joint, and the external circuit comprises a first connecting circuit, a second connecting circuit, a third connecting circuit and a fourth connecting circuit. According to the invention, through the mutual cooperation of the two groups of IO ports, even under the condition of external electromagnetic interference, even if one sufficient IO port of the single chip receives a signal of level change, the other group of IO port cannot accurately receive the level change, the single chip can identify that the key is not really pressed down, the locking or unlocking operation cannot be carried out, the unlocking or locking condition beyond the intention of a user cannot occur, and the system is practical and reliable.
Description
Technical Field
The utility model belongs to the technical field of the technique of intelligence lock and specifically relates to an anti-electromagnetic interference's of intelligence lock device.
Background
With the development of science and technology and the development of times, the traditional door opening mode is gradually replaced by a more convenient intelligent door lock.
The indoor door opening and closing circuit principle of the common intelligent door lock in the market is door opening and closing keys, and each path is connected with an IO (input/output) interface of a single chip microcomputer. When the low level or the high level exists, the singlechip is awakened in an interrupt mode. The single chip microcomputer judges which function is realized by interrupting response, and respective functions are realized. However, if the detection is performed by using one IO interface in a location with large interference, it is easy to cause misdetection, and there is a high possibility that unlocking or locking is performed beyond the will of the user, which results in a potential safety hazard.
In view of these problems, it is a technical problem to be solved by those skilled in the art to provide an intelligent door lock that can be used in a place with high interference and does not cause any misdetection or the like.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model provides an anti-electromagnetic interference's of intelligence lock device and device thereof.
According to a first aspect of the embodiments of the present invention, there is provided an anti-electromagnetic interference device for an intelligent door lock, comprising a control module and a detection module, wherein the control module is a single chip microcomputer, the detection module comprises an external circuit and a key circuit, the key circuit comprises a first key circuit and a second key circuit, the first key circuit comprises a first key and a first resistor, one end of the first key is connected to a first port of the single chip microcomputer, the other end of the first key is connected to one end of the first resistor and connected to a second port of the single chip microcomputer, and the other end of the first resistor is grounded;
the second key circuit comprises a second key and a second resistor, one end of the second key is connected to the third port of the single chip microcomputer, the other end of the second key is connected to one end of the second resistor and connected with the fourth port of the single chip microcomputer, and the other end of the second resistor is grounded;
the connection parts of the first key circuit and the second key circuit and the control module are connected with an external circuit, the external circuit comprises a first connecting circuit, a second connecting circuit, a third connecting circuit and a fourth connecting circuit, wherein,
the first connecting circuit comprises a third resistor and a first capacitor, one end of the third resistor is connected to a 3.3V power supply, the other end of the third resistor is connected to one end of the first capacitor, the other end of the first capacitor is grounded, and the joint of the third resistor and the first capacitor extends to be connected to a first port of the single chip microcomputer;
the second connecting circuit comprises a fourth resistor and a second capacitor, one end of the fourth resistor is connected to the 3.3V power supply, the other end of the fourth resistor is connected to one end of the second capacitor, the other end of the second capacitor is grounded, and the joint of the fourth resistor and the second capacitor extends to be connected to a third port of the single chip microcomputer;
the third connecting circuit comprises a fifth resistor and a third capacitor, one end of the fifth resistor is connected to the 3.3V power supply, the other end of the fifth resistor is connected to one end of the third capacitor, the other end of the third capacitor is grounded, and the joint of the fifth resistor and the third capacitor extends to be connected to a second port of the single chip microcomputer;
the fourth connecting circuit comprises a sixth resistor and a fourth capacitor, one end of the sixth resistor is connected to the 3.3V power supply, the other end of the sixth resistor is connected to one end of the fourth capacitor, the other end of the fourth capacitor is grounded, and the joint of the sixth resistor and the fourth capacitor is connected to a fourth port of the single chip microcomputer in an extending manner;
optionally, an oscillation circuit is further connected to the single chip microcomputer, the oscillation circuit includes a crystal oscillator, a third capacitor and a fourth capacitor, two ends of the crystal oscillator are respectively connected to the single chip microcomputer, one end of the crystal oscillator is connected to one end of the fifth capacitor, the other end of the fifth capacitor is grounded, the other end of the crystal oscillator is connected to one end of a sixth capacitor, and the other end of the sixth capacitor is grounded.
Optionally, the resistances of the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor are all 10K.
Optionally, the resistance values of the first resistor and the second resistor are both 1K.
Optionally, the capacitance values of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are all 0.1 UF.
Optionally, the capacitance value of the capacitor C6 and the sixth capacitor is 12F.
The embodiment of the utility model provides a technical scheme can include following beneficial effect:
the utility model discloses an among the technical scheme that discloses, use through mutually supporting of two sets of IO ports, even under external electromagnetic interference's the condition, even when the signal that the level changed is received to one of them sufficient IO port of singlechip, the change of level can not accurately be received to a set of IO port in addition, the singlechip also can be discerned for this button not really pressed down, can not lock or the unblock operation, the unblock or the situation of locking that can not appear outside the user will take place, and is practical reliable.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
Fig. 1 is a wire frame diagram illustrating an apparatus for preventing electromagnetic interference of an intelligent door lock according to an exemplary embodiment;
fig. 2 is a circuit diagram illustrating an apparatus for preventing electromagnetic interference of an intelligent door lock according to an exemplary embodiment.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below do not represent all implementations consistent with the present disclosure. Rather, they are merely examples of devices consistent with certain aspects of the present disclosure, as detailed in the appended claims.
Fig. 1 is a wire frame diagram of an apparatus for preventing electromagnetic interference of an intelligent door lock according to an exemplary embodiment, as shown in fig. 1, the apparatus includes a control module 10 and a detection module, the control module 10 is a single chip microcomputer, the detection module includes an external circuit and a key circuit, the key circuit includes a first key circuit and a second key circuit, the first key circuit includes a first key 101 and a first resistor 201, one end of the first key 101 is connected to a first port of the single chip microcomputer, the other end of the first key 101 is connected to one end of the first resistor 201 and connected to a second port of the single chip microcomputer, and the other end of the first resistor 201 is grounded;
the second key circuit comprises a second key 102 and a second resistor 202, one end of the second key 102 is connected to the third port of the single chip microcomputer, the other end of the second key 102 is connected to one end of the second resistor 202 and is connected with the fourth port of the single chip microcomputer, and the other end of the second resistor 202 is grounded;
the joints of the first key circuit and the second key circuit with the control module 10 are connected with an external circuit, the external circuit comprises a first connecting circuit, a second connecting circuit, a third connecting circuit and a fourth connecting circuit, wherein,
the first connecting circuit comprises a third resistor 203 and a first capacitor 301, one end of the third resistor 203 is connected to a 3.3V power supply, the other end of the third resistor 203 is connected to one end of the first capacitor 301, the other end of the first capacitor 301 is grounded, and the joint of the third resistor 203 and the first capacitor 301 extends to be connected to a first port of the single chip microcomputer;
the second connecting circuit comprises a fourth resistor 204 and a second capacitor 302, one end of the fourth resistor 204 is connected to a 3.3V power supply, the other end of the fourth resistor 204 is connected to one end of the second capacitor 302, the other end of the second capacitor 302 is grounded, and the connection part of the fourth resistor 204 and the second capacitor 302 extends to be connected to a third port of the single chip microcomputer;
the third connecting circuit comprises a fifth resistor 205 and a third capacitor 303, one end of the fifth resistor 205 is connected to a 3.3V power supply, the other end of the fifth resistor 205 is connected to one end of the third capacitor 303, the other end of the third capacitor 303 is grounded, and the connection between the fifth resistor 205 and the third capacitor 303 extends to be connected to the second port of the single chip microcomputer;
the fourth connecting circuit comprises a sixth resistor 206 and a fourth capacitor 304, one end of the sixth resistor 206 is connected to a 3.3V power supply, the other end of the sixth resistor 206 is connected to one end of the fourth capacitor 304, the other end of the fourth capacitor 304 is grounded, and the connection between the sixth resistor 206 and the fourth capacitor 304 extends to be connected to a fourth port of the single chip microcomputer;
the single chip microcomputer is further connected with an oscillating circuit, the oscillating circuit comprises a crystal oscillator 40, a third capacitor 303 and a fourth capacitor 304, two ends of the crystal oscillator 40 are respectively connected to the single chip microcomputer, one end of the crystal oscillator 40 is connected with one end of a fifth capacitor 305, the other end of the fifth capacitor 305 is grounded, the other end of the crystal oscillator 40 is connected with one end of a sixth capacitor 306, and the other end of the sixth capacitor 306 is grounded.
The third resistor 203, the fourth resistor 204, the fifth resistor 205 and the sixth resistor 206 all have a resistance of 10K.
The resistance values of the first resistor 201 and the second resistor 202 are both 1K.
The capacitance values of the first capacitor 301, the second capacitor 302, the third capacitor 303 and the fourth capacitor 304 are all 0.1 UF.
The capacitance value of the capacitor C6 and the sixth capacitor 306 is 12F.
Specifically, fig. 2 is a circuit diagram of an apparatus for preventing electromagnetic interference of an intelligent door lock according to an exemplary embodiment, in which a control module is a single chip microcomputer U1, a first port is an open 1 port, a second port is an open 2 port, a third port is a close 1 port, a fourth port is a close 2 port, a first key is a key K1, a second key is a key K2, a first resistor is a resistor R4, a second resistor is a resistor R5, a third resistor is a resistor R1, a fourth resistor is a resistor R2, a fifth resistor is a resistor NC/R1, a sixth resistor is a resistor NC/R2, a first capacitor is a capacitor C2, a second capacitor is a capacitor C3, a third capacitor is a capacitor C4, a fourth capacitor is a capacitor C5, a fifth capacitor C7, a sixth capacitor is a capacitor C9, and a crystal oscillator is a crystal Y1.
The detection module comprises an external circuit and a key circuit, the key circuit comprises a first key circuit and a second key circuit, the first key circuit comprises a key K1 and a resistor R4, one end of the key K1 is connected to an open 1 port of the single chip microcomputer U1, the other end of the key K1 is connected to one end of a resistor R4 and connected with an open 2 port of the single chip microcomputer, and the other end of the resistor R4 is grounded GND;
the second key circuit comprises a key K2 and a resistor R5, one end of the key K2 is connected to a close 1 port of the single chip microcomputer U1, the other end of the key K2 is connected to one end of a resistor R5 and is connected with a close 2 port of the single chip microcomputer, and the other end of the resistor R5 is grounded GND;
the connection parts of the first key circuit and the second key circuit and the control module are connected with an external circuit, the external circuit comprises a first connecting circuit, a second connecting circuit, a third connecting circuit and a fourth connecting circuit, wherein,
the first connecting circuit comprises a resistor R1 and a capacitor C2, one end of the resistor R1 is connected to a 3.3V power supply, the other end of the resistor R1 is connected to one end of the capacitor C2, the other end of the capacitor C2 is grounded GND, and the joint of the resistor R1 and the capacitor C2 extends to be connected to an open 1 port of the singlechip U1;
the second connecting circuit comprises a resistor R2 and a capacitor C3, one end of the resistor R2 is connected to a 3.3V power supply, the other end of the resistor R2 is connected to one end of a capacitor C3, the other end of the capacitor C3 is grounded GND, and the joint of the resistor R2 and the capacitor C3 extends to be connected to a close 1 port of the singlechip U1;
the third connecting circuit comprises a resistor NC/R1 and a capacitor C4, one end of the resistor NC/R1 is connected with a 3.3V power supply, the other end of the resistor NC/R1 is connected with one end of the capacitor C4, the other end of the capacitor C4 is grounded GND, and the joint of the resistor NC/R1 and the capacitor C4 is connected with an open 2 port of the single chip U1 in an extending mode;
the fourth connecting circuit comprises a resistor NC/R2 and a capacitor C5, one end of the resistor NC/R2 is connected with a 3.3V power supply, the other end of the resistor NC/R2 is connected with one end of a capacitor C5, the other end of the capacitor C5 is grounded GND, and the joint of the resistor NC/R2 and the capacitor C5 extends to be connected with a close 2 port of the singlechip U1;
still be connected with oscillating circuit on the singlechip U1, oscillating circuit includes crystal oscillator Y1, electric capacity C4 and electric capacity C5, crystal oscillator Y1's both ends connect respectively in singlechip U1, crystal oscillator Y1's one end is connected with electric capacity C7's one end, electric capacity C7's other end ground connection GND, crystal oscillator Y1's the other end is connected with electric capacity C9's one end, electric capacity C9's the other end ground connection GND.
The resistance values of the resistor R1, the resistor R2, the resistor NC/R1 and the resistor NC/R2 are all 10K.
The resistance values of the resistor R4 and the resistor R5 are both 1K.
The capacitance C2, the capacitance C3, the capacitance C4 and the capacitance C5 all have a capacitance value of 0.1 UF.
The capacitance value of the capacitor C6 and the capacitance value of the capacitor C9 are 12F.
Specifically, in an initial state, the key K1 and the key K2 are not pressed, the single chip microcomputer U1 sets an open 1 port pin to be connected with the pull-up resistor R1, and a close 1 port pin to be connected with the pull-up resistor R2, the initial state is a high level state, at this time, the resistor R1 and the resistor R2 are both external pull-up resistors of the key K1 and the key K2, and a pull-up current is increased, so that the effect of stabilizing the levels of the open 1 port and the close 1 port is achieved.
When the key K1 is pressed, the single chip microcomputer U1 converts a high level signal into a low level signal and knows that the key K1 is pressed, the single chip microcomputer U1 changes the level of an open 2 port after delaying for 30ms, so that the open 1 port outputs a specified level sequence, and the open 1 port reads level information at the same time.
If the key K1 is pressed by a person, the open 1 port and the open 2 port are in a conducting state, so that a signal of level change sent from the open 2 port can be accurately received by the open 1 port, and the single chip microcomputer U1 receives the signal from the open 2 port through the open 1 port and judges that the key K1 is pressed. When the judgment is finished, the level of the open 2 port can restore to the original level.
When the key K2 is pressed by a person, the close 1 port and the close 2 port are in a conducting state, so that a level-changed signal sent from the close 2 port can be accurately received by the close 1 port, and the single chip microcomputer U1 judges that the key K2 is pressed when receiving the signal from the close 2 port through the close 1 port. When the judgment is finished, the level of the close 2 port is restored to the original level.
In the circuit of the key K1, the resistor R1 and the resistor R4 play a role of stabilizing the level when the key K1 is pressed, when the key K1 is pressed, the open 2 port can output high and low levels by adjusting different resistance ratios through a voltage division circuit formed by the resistor R1 and the resistor R4,
when the open 2 port outputs a high level, the pull-up capability is enhanced due to the effect of the pull-up resistor of the resistor R1, so that the open 2 port outputs a high level, and when the open 2 port outputs a low level, the pull-down capability is enhanced due to the pull-down resistor of the resistor R4, so that the open 2 port outputs a low level.
In the circuit of the key K2, the resistor R2 and the resistor R5 play a role of stabilizing the level when the key K2 is pressed, when the key K2 is pressed, the voltage dividing circuit formed by the resistor R2 and the resistor R5 can adjust different resistance proportions to enable the close 2 port to output high and low levels,
when the close 2 port outputs high level, the pull-up capability is enhanced due to the action of the pull-up resistor of the resistor R2, so that the close 2 port outputs high level, and when the close 2 port outputs low level, the pull-down capability is enhanced due to the pull-down resistor of the resistor R5, so that the close 2 port outputs low level.
Taking the key K1 as an example, when external electromagnetic interference occurs to the circuit, the open 1 port is pulled low, and at this time, because the open 2 port and the open 1 port are not actually turned on, the open 1 port can only receive low level, but cannot receive the level changed from the open 2 port, so the single chip U1 recognizes that the key K2 is not pressed. Through the use of mutually supporting of two sets of IO ports, even under external electromagnetic interference's the condition, even when one of them sufficient IO port of singlechip received the signal that the level changed, the change of level can not accurately received to a set of IO port in addition, and the singlechip also can be discerned that this button is not really pressed down, can not lock or the unblock operation, and the unblock or the situation of locking that can not appear outside the user's will take place, and is practical reliable.
The above-mentioned embodiments are merely preferred embodiments of the present invention, and should not be considered as limitations of the present invention, and the protection scope of the present invention should be defined by the technical solutions described in the claims, and includes equivalent alternatives of technical features in the technical solutions described in the claims. Namely, equivalent alterations and modifications within the scope of the invention are also within the scope of the invention.
Claims (7)
1. The utility model provides an anti-electromagnetic interference's of intelligence lock device which characterized in that: the detection module comprises an external circuit and a key circuit, the key circuit comprises a first key circuit and a second key circuit, the first key circuit comprises a first key and a first resistor, one end of the first key is connected to a first port of the control module, the other end of the first key is connected to one end of the first resistor and connected with a second port of the control module, and the other end of the first resistor is grounded;
the second key circuit comprises a second key and a second resistor, one end of the second key is connected to the third port of the control module, the other end of the second key is connected to one end of the second resistor and is connected with the fourth port of the control module, and the other end of the second resistor is grounded;
the connection parts of the first key circuit and the second key circuit and the control module are connected with an external circuit, the external circuit comprises a first connecting circuit, a second connecting circuit, a third connecting circuit and a fourth connecting circuit, wherein,
the first connecting circuit comprises a third resistor and a first capacitor, one end of the third resistor is connected to a 3.3V power supply, the other end of the third resistor is connected to one end of the first capacitor, the other end of the first capacitor is grounded, and the joint of the third resistor and the first capacitor extends and is connected to a first port of the control module;
the second connecting circuit comprises a fourth resistor and a second capacitor, one end of the fourth resistor is connected to the 3.3V power supply, the other end of the fourth resistor is connected to one end of the second capacitor, the other end of the second capacitor is grounded, and the connection position of the fourth resistor and the second capacitor extends and is connected to a third port of the control module;
the third connecting circuit comprises a fifth resistor and a third capacitor, one end of the fifth resistor is connected to the 3.3V power supply, the other end of the fifth resistor is connected to one end of the third capacitor, the other end of the third capacitor is grounded, and the connection position of the fifth resistor and the third capacitor extends to be connected to the second port of the control module;
the fourth connecting circuit comprises a sixth resistor and a fourth capacitor, one end of the sixth resistor is connected to the 3.3V power supply, the other end of the sixth resistor is connected to one end of the fourth capacitor, the other end of the fourth capacitor is grounded, and the connection position of the sixth resistor and the fourth capacitor is connected to the fourth port of the control module in an extending mode.
2. The anti-electromagnetic interference device of the intelligent door lock according to claim 1, wherein: the control module is a single chip microcomputer.
3. The anti-electromagnetic interference device of the intelligent door lock according to claim 2, wherein: the single-chip microcomputer is further connected with an oscillating circuit, the oscillating circuit comprises a crystal oscillator, a fifth capacitor and a sixth capacitor, two ends of the crystal oscillator are respectively connected to the single-chip microcomputer, one end of the crystal oscillator is connected with one end of the fifth capacitor, the other end of the fifth capacitor is grounded, the other end of the crystal oscillator is connected with one end of the sixth capacitor, and the other end of the sixth capacitor is grounded.
4. The anti-electromagnetic interference device of the intelligent door lock according to any one of claims 1 to 3, wherein: the resistance values of the third resistor, the fourth resistor, the fifth resistor and the sixth resistor are all 10K.
5. The anti-electromagnetic interference device of the intelligent door lock according to any one of claims 1 to 3, wherein: the resistance values of the first resistor and the second resistor are both 1K.
6. The anti-electromagnetic interference device of the intelligent door lock according to any one of claims 1 to 3, wherein: the capacitance values of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are all 0.1 UF.
7. The anti-electromagnetic interference device of the intelligent door lock according to claim 3, wherein: the capacitance value of the fifth capacitor and the sixth capacitor is 12F.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202122902647.1U CN217467494U (en) | 2021-11-19 | 2021-11-19 | Anti-electromagnetic interference device of intelligent door lock |
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| CN202122902647.1U CN217467494U (en) | 2021-11-19 | 2021-11-19 | Anti-electromagnetic interference device of intelligent door lock |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114047723A (en) * | 2021-11-19 | 2022-02-15 | 广州保仕盾智能科技有限公司 | Anti-electromagnetic interference device of intelligent door lock |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114047723A (en) * | 2021-11-19 | 2022-02-15 | 广州保仕盾智能科技有限公司 | Anti-electromagnetic interference device of intelligent door lock |
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