CN217426760U - Semiconductor structure - Google Patents

Abstract

An embodiment of the utility model provides a semiconductor structure, include: a carrier plate; a first semiconductor die disposed on the carrier plate with an active surface of the first semiconductor die facing the carrier plate; and a molding compound encapsulating the carrier plate and the first semiconductor die, a passive side of the first semiconductor die being exposed with respect to the molding compound, the passive side being for ambient signals to pass through. An object of the utility model is to provide a semiconductor structure to reduce the environmental signal loss.

Description

Semiconductor structure

Technical Field

Embodiments of the present invention relate to semiconductor structures.

Background

Referring to fig. 1, currently, the filter of an Infrared (IR) sensor is mostly disposed on glass, a cover (lid)12 or a molding compound to prevent environmental noise, such as glass 16 disposed on an infrared Photodiode (PD)14 or glass 19 disposed on the cover 12 and adjacent to a light-receiving area of a light-receiving element (PD 14) to facilitate filtering out light in an infrared band. However, the infrared coated glass has high cost and large thickness, which is not beneficial to product miniaturization, and in addition, the cover 12 is not beneficial to product miniaturization. The dashed line A/A shows the Field of view (FOV) of the PD 14, which is smaller because the PD 14 is farther from the glass 19.

Referring to fig. 2, there is also a solution of a mold-sealed proximity sensor, which eliminates a cover and an infrared coated glass, and directly coats or attaches a filter 22 on a transparent adhesive 20, thereby facilitating the miniaturization of the product. However, light still needs to penetrate through multiple layers of different media, and includes the problem of mismatch of thermal expansion coefficients, and in addition, the lead 26 on the infrared photodiode 24 is not favorable for product miniaturization.

Current coatings or filters have achieved a degree of penetration of 95% or more for infrared radiation, for example, having a wavelength of 1100nm or more, but the infrared radiation passes through the following items with a loss of penetration: glass (e.g., glass 16 and glass 19 shown in fig. 1), light-transmissive glue (e.g., light-transmissive glue 20 shown in fig. 2, such as epoxy). If more coatings are added to improve the penetration, the miniaturization of the product is not facilitated and the cost is higher; if the thickness of the glass is reduced, miniaturization of products is facilitated, but glass of a smaller thickness (for example, 100 μm or less) has a reliability risk.

SUMMERY OF THE UTILITY MODEL

To solve the problems in the related art, an object of the present invention is to provide a semiconductor structure to reduce the environmental signal loss.

To achieve the above object, an embodiment of the present invention provides a semiconductor structure, including: a carrier plate; a first semiconductor die disposed on the carrier plate with an active surface of the first semiconductor die facing the carrier plate; and a molding compound encapsulating the carrier plate and the first semiconductor die, a passive side of the first semiconductor die being exposed with respect to the molding compound, the passive side being for ambient signals to pass through.

In some embodiments, the semiconductor structure further comprises: and the filtering piece is arranged on the passive surface and is used for filtering the environmental signal.

In some embodiments, at least a portion of the filter element is embedded in the molding compound.

In some embodiments, the filter completely covers the passive face.

In some embodiments, the first semiconductor die is an optical receiver die, the environmental signal is an optical signal, and the filter is a filter.

In some embodiments, the first semiconductor die is an optical sensor.

In some embodiments, the semiconductor structure further comprises: and the second semiconductor die is arranged on the carrier plate and used for controlling the first semiconductor die.

In some embodiments, the first semiconductor die and the second semiconductor die are disposed side-by-side.

In some embodiments, the first semiconductor die is electrically connected to the second semiconductor die through a carrier plate.

In some embodiments, the second semiconductor die is located between the carrier plate and the first semiconductor die.

In some embodiments, the first semiconductor die is directly electrically connected to the second semiconductor die.

In some embodiments, the second semiconductor die is electrically connected to the carrier plate by a wire, and the first semiconductor die is a flip chip.

In some embodiments, one end of the lead is connected to the upper surface of the second semiconductor die and the other end is connected to the carrier plate.

In some embodiments, the molding compound also encapsulates the second semiconductor die.

In some embodiments, the second semiconductor die is completely surrounded by the carrier plate, the molding compound.

In some embodiments, the second semiconductor die is an Application Specific Integrated Circuit (ASIC) die.

In some embodiments, the molding compound is not conductive to environmental signals.

In some embodiments, the passive facet is used to pass ambient signals to a sensing region of the first semiconductor die located at the active facet.

In some embodiments, the top surface of the molding compound is not lower than the inactive side of the first semiconductor die.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 and 2 show schematic structural diagrams of a conventional semiconductor structure.

Fig. 3-5 and 6-8 illustrate formation processes of semiconductor structures according to various embodiments.

Fig. 9 illustrates a semiconductor structure according to another embodiment of the present application.

Detailed Description

In order to better understand the spirit of the embodiments of the present application, the following further description is given in conjunction with some preferred embodiments of the present application.

Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.

As used herein, the terms "substantially", "substantially" and "about" are used to describe and illustrate minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the terms can refer to a range of variation of less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" identical if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.

In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. The foregoing description is to be understood as not limited to the specific embodiments shown, but is to be understood as encompassing all individual values or sub-ranges encompassed within that range as if each value and sub-range is explicitly recited.

Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

Fig. 3-5 illustrate a process of forming a semiconductor structure according to some embodiments of the present application, with reference to fig. 3, a first semiconductor die 32 and a second semiconductor die 34 disposed on a carrier plate 30. In some embodiments, the active face of the first semiconductor die 32 is toward the carrier plate 30 and the passive face of the first semiconductor die 32 is away from the carrier plate 30. In some embodiments, the sensing region 52 of the first semiconductor die 32 is located at the active face of the first semiconductor die 32, i.e., the sensing region 52 is facing the carrier plate 30. In some embodiments, the second semiconductor die 34 is an Application Specific Integrated Circuit (ASIC) for controlling the first semiconductor die 32. Carrier plate 30 may be a semiconductor substrate, any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and/or one or more dies on a wafer, and any other type of semiconductor and/or epitaxial layers associated therewith. A filter element 31 is arranged on the passive side of the first semiconductor die 32, the filter element 31 being used to filter the ambient signal to filter out ambient noise. In some embodiments, the filter 31 completely covers the passive side of the first semiconductor die 32. In some embodiments, the first semiconductor die 32 is an optical receiver die, the ambient signal is an optical signal, and the filter 31 is a filter. In some embodiments, the first semiconductor die 32 is an optical sensor. In some embodiments, the first semiconductor die 32 and the second semiconductor die 34 are disposed side-by-side. In some embodiments, the first semiconductor die 32 is electrically connected to the second semiconductor die 34 through the carrier plate 30.

Referring to fig. 4, in some embodiments, the second semiconductor die 34 is electrically connected to the carrier plate 30 by leads 36. In some embodiments, the first semiconductor die 32 is a flip chip, and the first semiconductor die 32 includes a Ball Grid Array (BGA) 38 connected to the carrier board 30. In some embodiments, one end of the leads 36 is connected to the upper surface of the second semiconductor die 34 and the other end is connected to the carrier plate 30.

Referring to fig. 5, a molding compound 50 encapsulates the carrier plate 30 and the first and second semiconductor dies 32, 34, and the passive side of the first semiconductor die 32, the filter 31, is exposed relative to the molding compound 50 for the passage of environmental signals. In some embodiments, the molding compound 50 is unable to conduct environmental signals (e.g., light), such as resins including carbon black or pigments to absorb or reflect visible light, graphene, etc., avoiding loss of the environmental signals through the molding compound 50. In some embodiments, the molding compound 50 may be formed to completely cover the first semiconductor die 32, the second semiconductor die 34, the filter 31, and then the molding compound 50 may be etched back to expose the filter 31, for example, by an etching process. In some embodiments, the molding compound 50 may be flush with the top surface of the first semiconductor die 32 or may be higher than the top surface of the first semiconductor die 32, e.g., at least a portion of the filter 31 is embedded in the molding compound 50. In some embodiments, the microlens array is not present on the first semiconductor die 32 to avoid damage to the microlens array when the molding compound 50 is etched. In some embodiments, the passive side of the first semiconductor die 32 is used to pass ambient signals, enabling the ambient signals to pass to the sensing region 52 of the first semiconductor die 32 at the active side. Since it is known that, for example, infrared rays with a wavelength of over 1100nm can penetrate through a silicon material, and the loss of infrared rays is lower when the infrared rays penetrate through the silicon material than when the infrared rays penetrate through a glass material, the embodiment of the present application uses the aforementioned characteristics to dispose the passive side of the first semiconductor die 32 upward, i.e., dispose the sensing region 52 of the first semiconductor die 32 downward, so that the sensing region 52 can be directly protected by the silicon material of the first semiconductor die 32 without additionally disposing a cover, glass, or transparent glue, and the environmental signal can reach the sensing region 52 through the silicon material of the first semiconductor die 32 in a low loss state. Therefore, compared with the prior art, the medium such as glass or transparent glue which the environmental signal needs to pass through can be effectively reduced, and the structure can be miniaturized. In some embodiments, the top surface of the molding compound 50 is not lower than the inactive surface of the first semiconductor die 32 to achieve good protection of the first semiconductor die 32. In some embodiments, the top surface of the molding compound 50 is not higher than the filter 31 to avoid the molding compound 50 that cannot conduct the environmental signal from blocking the environmental signal on the path through which the environmental signal passes, and affecting the visible angle range shown by the dashed line BB. In some embodiments, the second semiconductor die 34 is completely surrounded by the carrier plate 30, the molding compound 50.

Fig. 6-8 illustrate formation processes of semiconductor structures according to further embodiments of the present application. Referring to fig. 6, a first semiconductor die 32 and a second semiconductor die 34 are disposed on a carrier plate 30. In some embodiments, the active face of the first semiconductor die 32 faces the carrier plate 30. In some embodiments, the second semiconductor die 34 is an Application Specific Integrated Circuit (ASIC) for controlling the first semiconductor die 32. Carrier plate 30 may be a semiconductor substrate, any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and/or one or more dies on a wafer, and any other type of semiconductor and/or epitaxial layers associated therewith. A filter element 31 is arranged on the passive side of the first semiconductor die 32, the filter element 31 being used for filtering ambient signals. In some embodiments, the filter 31 completely covers the passive side of the first semiconductor die 32. In some embodiments, the first semiconductor die 32 is an optical receiver die, the ambient signal is an optical signal, and the filter 31 is a filter. In some embodiments, the first semiconductor die 32 is an optical sensor. In some embodiments, the second semiconductor die 34 is located between the carrier plate 30 and the first semiconductor die 32. In some embodiments, the first semiconductor die 32 is directly electrically connected with the second semiconductor die 34.

Referring to fig. 7, in some embodiments, a second semiconductor die 34 is electrically connected to the carrier plate 30 by wires 36. In some embodiments, the first semiconductor die 32 is a flip chip, the first semiconductor die 32 including a Ball Grid Array (BGA) 38 to which the second semiconductor die 34 is connected. In some embodiments, one end of the leads 36 is connected to the upper surface of the second semiconductor die 34 and the other end is connected to the carrier plate 30.

Referring to fig. 8, a molding compound 50 encapsulates the carrier plate 30 and the first and second semiconductor dies 32, 34, with the passive side of the first semiconductor die 32, the filter 31, exposed relative to the molding compound 50 for ambient signals to pass through. In some embodiments, the molding compound 50 is not capable of conducting ambient signals (e.g., light), such as a resin including carbon black or pigments to absorb or reflect visible light, graphene, or the like. In some embodiments, the molding compound 50 may be formed to completely cover the first semiconductor die 32, the second semiconductor die 34, the filter 31, and then the molding compound 50 may be etched back to expose the filter 31, for example, by an etching process. In some embodiments, the molding compound 50 may be flush with the top surface of the first semiconductor die 32 or may be higher than the top surface of the first semiconductor die 32, e.g., at least a portion of the filter 31 is embedded in the molding compound 50. In some embodiments, the passive side of the first semiconductor die 32 is used to pass ambient signals, enabling the ambient signals to pass to the sensing region 52 of the first semiconductor die 32 at the active side. In some embodiments, the top surface of the molding compound 50 is not lower than the inactive side of the first semiconductor die 32. In some embodiments, the top surface of the molding compound 50 is not higher than the filter 31 to avoid the molding compound 50 that cannot conduct the environmental signal from blocking the environmental signal on the path through which the environmental signal passes, and affecting the visual angle range shown by the dashed line CC.

In some embodiments, two semiconductor dies are arranged side by side as shown in fig. 3 to 5, or two semiconductor dies are arranged in a stack as shown in fig. 6 to 8, depending on the lateral size or height restrictions that are different in practical use.

Fig. 9 illustrates a semiconductor structure in accordance with various embodiments of the present application, wherein the first semiconductor die 32 is a micro-electromechanical sensor that includes a cover (cap)92 enclosing the sensing region 52 in a cavity 90, in some embodiments, the first semiconductor die 32 is used to sense a temperature signal of the environment. In some embodiments, the embodiment shown in fig. 9 may also stack the first semiconductor die 32 on the second semiconductor die 34 as shown in fig. 6-8.

An embodiment of the utility model provides a semiconductor structure, include: a carrier plate 30; a first semiconductor die 32 disposed on the carrier plate 30, an active surface of the first semiconductor die 32 facing the carrier plate 30; a mold compound 50 encasing the carrier plate 30 and the first semiconductor die 32, a passive side of the first semiconductor die 32 being exposed with respect to the mold compound 50, the passive side being for ambient signals (e.g., optical signals, temperature signals) to pass through.

In some embodiments, the semiconductor structure further comprises: and a filter element 31 disposed on the passive surface, the filter element 31 being for filtering the environmental signal.

In some embodiments, at least a portion of the filter element 31 is embedded in the molding compound 50.

In some embodiments, the filter 31 completely covers the passive face.

In some embodiments, the first semiconductor die 32 is an optical receiver die, the ambient signal is an optical signal, and the filter 31 is a filter.

In some embodiments, the semiconductor structure further comprises: a second semiconductor die 34 disposed on the carrier plate 30, the second semiconductor die 34 for controlling the first semiconductor die 32.

In some embodiments, the first semiconductor die 32 and the second semiconductor die 34 are disposed side-by-side.

In some embodiments, the second semiconductor die 34 is located between the carrier plate 30 and the first semiconductor die 32.

In some embodiments, the second semiconductor die 34 is electrically connected to the carrier plate 30 by leads 36, and the first semiconductor die 32 is a flip chip.

In some embodiments, one end of the leads 36 is connected to the upper surface of the second semiconductor die 34 and the other end is connected to the carrier plate 30.

In some embodiments, the molding compound 50 is not conductive to environmental signals.

The embodiment of the present application exposes the passive side of the first semiconductor die 32, and the viewing angle range is determined by the lateral dimension and thickness of the first semiconductor die 32, thereby enlarging the viewing angle range and effectively improving the light sensing capability compared with the prior art. The embodiment of the application does not need to cover glass or transparent adhesive, is beneficial to the miniaturization of the structure and reduces the manufacturing cost, and the environmental signal does not need to pass through a plurality of layers of media to reach the first semiconductor die 32, thereby reducing the loss of the environmental signal.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A semiconductor structure, comprising:

a carrier plate;

a first semiconductor die disposed on the carrier plate, an active surface of the first semiconductor die facing the carrier plate;

a molding compound encapsulating the carrier plate and the first semiconductor die, a passive side of the first semiconductor die being exposed with respect to the molding compound, the passive side for ambient signals to pass through.

2. The semiconductor structure of claim 1, further comprising:

a filter element disposed on the passive face, the filter element for filtering the environmental signal.

3. The semiconductor structure of claim 2, wherein at least a portion of the filter element is embedded in the mold compound.

4. The semiconductor structure of claim 2, wherein the filter completely covers the passive face.

5. The semiconductor structure of claim 2, wherein the first semiconductor die is an optical receiver die, the environmental signal is an optical signal, and the filter is a filter.

6. The semiconductor structure of claim 1, further comprising:

a second semiconductor die disposed on the carrier plate, the second semiconductor die for controlling the first semiconductor die.

7. The semiconductor structure of claim 6, wherein the first semiconductor die and the second semiconductor die are disposed side-by-side.

8. The semiconductor structure of claim 6, wherein the second semiconductor die is located between the carrier plate and the first semiconductor die.

9. The semiconductor structure of claim 6, wherein the second semiconductor die is electrically connected to the carrier board by a wire, and the first semiconductor die is a flip chip.

10. The semiconductor structure of claim 1, wherein the mold compound is not capable of conducting the environmental signal.

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