CN217426742U - Electronic device - Google Patents

Abstract

The utility model relates to an electronic device. The electronic device includes: a first chip; a second chip adjacent to the first chip in a lateral direction; the first circuit layer is positioned below the first chip and the second chip and comprises a first circuit for connecting the first chip and the second chip and a second circuit for connecting the first chip and the second chip, and the line width/line distance of the first circuit is different from the line width/line distance of the second circuit. The technical scheme can at least reduce high signal transmission loss and high power consumption caused by interconnection between chips.

Description

Electronic device

Technical Field

The utility model relates to the field of semiconductor technology, more specifically relates to an electronic device.

Background

In view of the increasing functional requirements of chips, the manufacturing cost of System on Chip (SoC) is higher and higher. To solve this problem, the conventional method employs a modular chip (chiplet) concept to manufacture different functional dies (die), such as processor die, I/O die, and SerDes die, in different (high, low) level processes. And then the functional dies are interconnected through a packaging process adopting thin lines or bridge dies (bridge die).

However, in consideration of signal transmission speed and impedance matching, if the interconnections between the dies are through thin wires or bridge dies, some signals (such as SerDes signals) are severely lost due to impedance problems, which may increase power consumption or affect the demodulation of the signals.

SUMMERY OF THE UTILITY MODEL

To the above-mentioned problem in the correlation technique, the utility model provides an electronic device can reduce high signal transmission loss and the high power consumption that interconnection caused between the chip at least.

According to the utility model discloses an embodiment provides an electronic device, include: a first chip; a second chip adjacent to the first chip in a lateral direction; the first circuit layer is positioned below the first chip and the second chip and comprises a first circuit for connecting the first chip and the second chip and a second circuit for connecting the first chip and the second chip, and the line width/line distance of the first circuit is different from the line width/line distance of the second circuit.

In some embodiments, the first wire is closer to a gap between the first chip and the second chip than the second wire.

In some embodiments, the path length of the first line is less than the path length of the second line.

In some embodiments, the line width/pitch of the first line is smaller than the line width/pitch of the second line, and the first line is located at a higher level than the second line in the first line layer.

In some embodiments, the first circuit layer further includes a bridge die located below the first chip and the second chip, the bridge die being located below the first circuit layer, wherein the bridge die is located on the first circuit, and a line width/line distance of the first circuit is smaller than a line width/line distance of the second circuit.

In some embodiments, the electronic device further includes a second wire layer located below the bridge die and electrically connected to the bridge die.

In some embodiments, the electronic device further includes a passive component located between the first and second circuit layers and electrically connected to the first or second chip.

In some embodiments, in a top view, the first line overlaps both the first chip and the second chip, and the first line is disposed along a first axis extending in the transverse plane and the second line is disposed along a second axis extending in the transverse plane.

In some embodiments, the first axis is different from the second axis.

In some embodiments, the first chip is connected to the two second chips by different second lines, and the second axes of the different second lines intersect in the top view.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A is a schematic diagram of an electronic device according to an embodiment of the invention.

Fig. 1B is a partially enlarged schematic view of the electronic device in fig. 1A.

Fig. 2A is a schematic diagram of an electronic device according to another embodiment of the present invention.

Fig. 2B is a schematic diagram of an electronic device according to another embodiment of the present invention.

Fig. 3 is a schematic diagram of an electronic device according to another embodiment of the invention.

Fig. 4 is a schematic diagram of an electronic device according to another embodiment of the invention.

Fig. 5A-5C respectively show schematic top views of electronic devices according to various embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

According to an embodiment of the present invention, there is provided an electronic device including a first chip and a second chip interconnected to each other. Fig. 1A is a schematic diagram of an electronic device 100 according to an embodiment of the invention. Referring to fig. 1A, the electronic device 100 includes a first chip 111 and a second chip 112, the second chip 112 being disposed adjacent to the first chip 111 in the lateral direction X. The first chip 111 and the second chip 112 have a gap therebetween. Each of the first chip 111 and the second chip 112 may be an Application Specific Integrated Circuit (ASIC) chip, respectively. In some embodiments, each of first chip 111 and second chip 112 may be a processor chip, an I/O chip, or a SerDes chip.

The first chip 111 and the second chip 112 are located above the first wiring layer 120. The first chip 111 and the second chip 112 may be surrounded by a molding layer 115 on the first wiring layer 120. The molding layer 115 may be located in a gap between the first and second chips 111 and 112, and may be filled between the first and second chips 111 and 112 and the first wiring layer 120. In some embodiments, the first line layer 120 may be RDL (redistribution layer). In some embodiments, the first line level 120 is a fanout (fanout) RDL. In some embodiments, the first circuit layer 120 may also be a substrate. For example, the first circuit layer 120 may be a thinned substrate (thin substrate).

Fig. 1B is a partially enlarged schematic view of the electronic device 100 in fig. 1A. As shown in fig. 1A and 1B, the first circuit layer 120 includes a dielectric layer 122, and the first circuit layer 120 further includes a first circuit 131 formed in the dielectric layer 122 and interconnecting the first chip 111 and the second chip 112. The first line 131 extends laterally under the second chip 112 across the gap between the first chip 111 and the second chip 112. The first chip 111 and the second chip 112 may be connected to the first wiring 131 in the first wiring layer 120, for example, by respective bump connections 181, thereby forming a first path P1 interconnecting the first chip 111 and the second chip 112 through the first wiring 131. In fig. 1A and 1B, the first path P1 is indicated by a solid line with an arrow. One first path P1 is shown in fig. 1A and 1B, but the number of the first paths P1 may be plural.

The first wiring layer 120 further includes a second wiring 132 formed in the dielectric layer 122 and interconnecting the first chip 111 and the second chip 112. The second line 132 extends laterally across the gap between the first chip 111 and the second chip 112 to below the second chip 112. The first chip 111 and the second chip 112 may be connected to the second wiring 132 in the first wiring layer 120, for example, by respective corresponding bump connectors 181, to interconnect the first chip 111 and the second chip 112, thereby forming a second path P2 interconnecting the first chip 111 and the second chip 112 by the second wiring 132. In fig. 1A and 1B, the second path P2 is indicated by a broken line with an arrow. Two second paths P2 are shown in fig. 1A and 1B, but the number of the second paths P2 may be plural or may be one. In some embodiments, other lines besides the first line 131 and the second line 132 may also be included in the first line layer 120.

According to an embodiment of the present invention, the first line width/line distance (L/S) of the first line 131 is different from the second L/S of the second line 132. The above technical solution of the present invention splits the interconnection between the first chip 111 and the second chip 112 into at least two transmission paths, i.e. a first path P1 and a second path P2, wherein the first path P1 interconnects the first chip 111 and the second chip 112 through a first line 131 having a first L/S, and the second path P2 interconnects the first chip 111 and the second chip 112 through a second line 132 having a second L/S.

In some embodiments, the first L/S of the first line 131 is less than the second L/S of the second line 132. Accordingly, the density of the first wires 131 is greater than that of the second wires 132. In such an embodiment, the first line 131 having a smaller L/S may be referred to as a thin line. The first line 131 has a corresponding path length L1, the second line 132 has a corresponding path length L2, and the path length L1 of the first line 131 is less than the path length L2 of the second line 132. In other words, the second wire 132 laterally extends for a length greater than the first wire 131. In some embodiments, the path length L1 of the first line 131 may be less than 1 mm. The path length L2 of the second line 132 may be greater than 10 mm.

The first circuit 131 and the second circuit 132 may be used to transmit signals between the first chip 111 and the second chip 112, and the transmission speeds of the signals transmitted by the first circuit 131 and the second circuit 132 may be different. Specifically, the transmission speed of the signal transmitted through the first line 131 may be higher than the transmission speed of the signal transmitted through the second line 132. By providing at least two transmission paths P1 and P2 with different L/S between the first chip 111 and the second chip 112, wherein signals with high speed transmission requirements are transmitted by the first path P1 with a shorter path, and signals without high speed transmission requirements are transmitted by the second path P2 with a longer path, signal loss can be reduced by the second line 132 in the second path P2 with a larger L/S, thereby reducing high signal transmission loss and high power consumption caused by the existing interconnection mode between chips. In addition, since different L/ss have different requirements for process capability, the signal shunting through the first line 131 and the second line 132 with different L/ss can save the manufacturing cost.

The first and second lines 131 and 132 may be at different levels in the vertical direction Z in the first line layer 120, respectively. Specifically, the first wire 131 in the first wire layer 120 is located at a higher level than each of the second wires 132, i.e., the first wire 131 is located at a higher level than the second wires 132 in the first wire layer 120. The first wire 131 may be closer to a gap between the first chip 111 and the second chip 112 than each of the second wires 132. In the vertical direction Z, the first line 131 is located between the second line 132 and the first chip 111 and the second chip 112. In addition, as shown in fig. 1B, the second lines 132 in the different second paths P2 may also be located at different high and low levels, but all lower than the first lines 131 in the first path P1.

According to the embodiment of the present invention, a first path P1 with a shorter path and a second path P2 with a longer path are simultaneously formed by using the first line layer 120 (e.g., RDL), wherein the first line 131 with a smaller L/S (i.e., a thin line width) is used for the first path P1 with a shorter path, and the second line 132 with a larger L/S (i.e., a thick line width) is used for the second path P2 with a longer path. The RDL is used to manufacture lines with different L/S in different layers of the first line layer 120, so that the requirement of long and short paths can be satisfied in the first line layer 120 at one time. By utilizing the characteristics of long and short paths, the communication between the first chip 111 and the second chip 112 can be performed in long and short distances at the same time, so as to achieve the best processing efficiency. Also, by additionally employing the second line 132 having a thick line width to interconnect the chips, the second line 132 may also reduce the need for the L/S technology, as compared to conventional technologies, all of which employ a thin line to interconnect the chips.

Referring back to fig. 1A, the electronic device 100 further includes a second line layer 140 located below the first line layer 120. The second circuit layer 140 may be, for example, a substrate. The first circuit layer 120 may be connected to the second circuit layer 140, for example, by bump connectors 182. The electronic device 100 may further include a passive element 150, and the passive element 150 is located between the first and second wiring layers 120 and 140 and electrically connected to the corresponding first or second chip 111 or 112. The first chip 111 or the second chip 112 may be connected to the wires in the first wire layer 120 through bump connections 181 to be connected to the passive elements 150. The passive element 150 may be various electronic elements such as a capacitor and a resistor. The capacitor may be, for example, a deep trench capacitor (deep trench capacitor) having voltage stabilization and filtering functions.

Fig. 2A is a schematic diagram of an electronic device 200a according to another embodiment of the invention. Elements of the electronic device 200a shown in fig. 2A that are similar to elements of the electronic device 100 shown in fig. 1A and 1B are given the same reference numerals. The embodiment shown in fig. 2A differs from that of fig. 1A and 1B in that the first line layer 120 further comprises a bridge die 160 located below and between the first chip 111 and the second chip 112. In this embodiment, the bridge die 160 is located on the first line 131. The first path P1 also includes therein a wire extending in the vertical direction Z to be connected to the first wire 131. The first line 131 extends laterally from below the first chip 111 to below the second chip 112 across the gap between the first chip 111 and the second chip 112. Thus, a first path P1 interconnecting the first chip 111 and the second chip 112 is formed by bridging the die 160. In such embodiments, the L/S of the first line 131 at the bridge die 160 is less than the L/S of the second line 132 in the dielectric layer 122. In the present embodiment, the first line 131 has a corresponding path length L3, and in some embodiments, the path length L3 may be in a range of 90 μm to 110 μm. Note that the path length L3 is the total length including the distance that the first line 131 extends in the lateral direction X and the vertical direction Z.

In the present embodiment, the first line 131 in the first path P1 is formed by the bridge die 160, the first path P1 and the second path P2 formed by the second line 132 in the first line layer 120 above the bridge die 160 commonly perform the interconnection shunting of the first chip 111 and the second chip 112, and in the present embodiment, the bridge die 160 is a silicon bridge (silicon bridge), which can improve the performance and reduce the high signal transmission loss and the high power consumption caused by the interconnection between the chips. In addition, the bridging die 160 is used to realize the fine line requirement of the first line 131, and the bridging die 160 can be used to realize a short path connection of the wide IO (an IO standard) of the first chip 111 and/or the second chip 112, so that the wide IO requirement can be effectively achieved. Considering that different L/ss have different requirements for process capability, the signal shunting through the first line 131 and the second line 132 with different L/ss can save the manufacturing cost.

Further, similar to the embodiment shown in fig. 1A and 1B, electronic device 200a in fig. 2A also includes a second wiring layer 140 located below bridge die 160 and electrically connected to bridge die 160. The first circuit layer 120 may be connected to the second circuit layer 140, for example, by bump connectors 182. A passive element 150 (e.g., a capacitor) is located between the first wiring layer 120 and the second wiring layer 140, and is electrically connected to the first chip 111 or the second chip 112.

Fig. 2B is a schematic diagram of an electronic device 200B according to another embodiment of the present invention. Elements of the electronic device 200B shown in fig. 2B that are similar to the electronic device 200a shown in fig. 2A are given the same reference numerals. The embodiment shown in fig. 2B is different from that shown in fig. 2A in that a third circuit layer 170 may be disposed above the first chip 111 and the second chip 112. The third circuit layer 170 may be connected to the first circuit layer 120 through the conductive posts 188 around the first chip 111 and the second chip 112. In this way, the second chip 112 may form the third path P3 via the wiring in the first wiring layer 120, the conductive pillar 188, and the wiring in the third wiring layer 170, and the second chip 112 may be connected to an external circuit above the third wiring layer 170 through the third path P3. Similarly, although not shown in fig. 2B, the first chip 111 may also be connected to an external circuit through a path similar to the third path P3. In the present embodiment, an electronic element such as a memory (memory) may be stacked above the third circuit layer 170, and the third path P3 may be connected to such an electronic element. In addition, in some embodiments, the first circuit layer 120 may be electrically connected to a PCB located below the first circuit layer 120 through bump connectors 182.

Fig. 3 is a schematic diagram of an electronic device 300 according to another embodiment of the invention. Elements of the electronic device 300 shown in fig. 3 that are similar to the electronic device 200a shown in fig. 2A have been given the same reference numerals. The embodiment shown in fig. 3 differs from that of fig. 2A in that the electronic device 300 further comprises a protective layer 158, the protective layer 158 encapsulating the bridge die 160. The protective layer 158 may be a molding compound (molding compound), and the protective layer 158 may protect the bridge die 160 and the passive component 150 and may prevent the bridge die 160 and the passive component 150 from being damaged due to external impacts. The passive element 150 connected to the first chip 111 or the second chip 112 is also covered with the protective layer 158. The bridge die 160 and the passive components 150 may be electrically connected with the second circuit layer 140, for example, by bump connections 182. The first circuit layer 120 may be connected to the second circuit layer 140 by the conductive pillars 183 penetrating the protection layer 158 and the bump connectors 182.

Fig. 4 is a schematic diagram of an electronic device 400 according to another embodiment of the invention. Elements of the electronic device 400 shown in fig. 4 that are similar to elements of the electronic device 200a shown in fig. 2A have been given the same reference numerals. In the embodiment shown in fig. 4, the electronic device 400 includes the first chip 111 and the second chip 112 spaced apart in the lateral direction X, and the electronic device 400 further includes the bridge die 160 located below the first chip 111 and the second chip 112. The bridge die 160 is covered by a protective layer 158. The second line layer 140 underlies the bridge die 160 and the protective layer 158. The first chip 111 and the second chip 112 may be connected to the second circuit layer 140 through the conductive pillars 183 penetrating the protection layer 158 and the bump connectors 182. In this embodiment, the protective layer 158 encasing the bridge die 160 is in direct contact with the mold layer 115 encasing the first chip 111 and the second chip 112, thereby omitting the portion of the first wiring layer 120 (e.g., RDL) between the protective layer 158 and the mold layer 115 as compared to the embodiment shown in fig. 3. When the I/O density of the first chip 111 and the second chip 112 is the same as the density of the bump connectors 182, the RDL may be omitted by the structure of this embodiment.

In the present embodiment, the bridge die 160 is located on the first line 131 in the first path P1 interconnecting the first chip 111 and the second chip 112. In addition, since a portion of the first wiring layer 120 between the protective layer 158 and the molding layer 115 is omitted, the second path P2 is formed via the second wiring layer 140, and the second wiring layer 140 includes therein the second wiring 132 for forming the second path P2 to interconnect the first chip 111 and the second chip 112. Thus, the second path P2 interconnecting the first chip 111 and the second chip 112 is formed by the conductive posts 183 passing through the protective layer 158 and the second wire 132 provided in the second wire layer 140. In the present embodiment, the L/S of the first line 131 is smaller than that of the second line 132.

In addition, a passive component 150 (e.g., a capacitor) is located between the first chip 111 and/or the second chip 112 and the second circuit layer 140, and the passive component 150 is covered by the protective layer 158. The passive element 150 is electrically connected to the first chip 111 or the second chip 112, and the passive element 150 is also electrically connected to the second circuit layer 140. The bridge die 160 and the passive components 150 may be electrically connected with the second circuit layer 140, for example, by bump connections 182.

Fig. 5A-5C respectively show schematic top views of electronic devices according to various embodiments. Wherein the plane shown in the top view is a transverse plane defined by a transverse direction X and a direction Y. In the top view as shown in fig. 5A, the first chip 111 and the second chip 112 are adjacently spaced in the lateral direction X. Also, the first line 131 overlaps the first chip 111 and also overlaps the second chip 112. The second line 132 overlaps the first chip 111 and also overlaps the second chip 112. The first line 131 is arranged along a first axis X1 extending in the lateral direction X in the plane of the top view, and the second line 132 is arranged along a second axis X2 extending in the lateral direction X. The first axis X1 is different from the second axis X2. In fig. 5A, the first axis X1 and the second axis X2 are spaced from and parallel to each other, that is, the first line 131 and the second line 132 do not overlap with each other in a plan view.

As shown in fig. 5B, the two second chips 112a, 112B are disposed on the same side of the first chip 111. The first chip 111 and each of the second chips 112a, 112b are adjacently disposed at intervals in the lateral direction X. The two second chips 112a, 112b are disposed adjacent to each other at an interval in the Y-axis direction. The first chip 111 and the second chip 112a, the first chip 111 and the second chip 112b are interconnected by first lines 131a, 131b extending in the lateral direction X. The second chip 112a and the second chip 112b are interconnected by a first line 131c extending in the direction Y. The first chip 111 may be connected to one second chip 112a through a second wire 132a and connected to another second chip 112b through a different second wire 132 b. In a plan view, the second axes X2a, X2b corresponding to the two second lines 132a, 132b intersect with each other. Each of the second lines 132a, 132b is not parallel to the lateral direction X or the direction Y. In fig. 5B, the second lines 132a, 132B are shown as oblique straight lines extending along the second axes X2a, X2B, but in practice, in some embodiments, there may be portions of each second line 132a, 132B extending along the transverse direction X, the direction Y, and the second axes X2a, X2B. That is, at least a portion of the second lines 132a, 132b may extend in a direction different from that of the first lines 131a, 131b, or 131 c. In a preferred embodiment, the second lines 132a, 132b extend directly along the second axes X2a, X2b of the diagonal straight lines, which may provide the shortest transmission path.

As shown in fig. 5C, the two second chips 112a and 112b are correspondingly disposed on the same side of the two first chips 111a and 111 b. Each second chip 112a, 112b is disposed adjacent to and spaced apart from the corresponding first chip 111a, 111b in the lateral direction X. The two first chips 111a, 111b are disposed at an adjacent interval in the direction Y, and the two second chips 112a, 112b are disposed at an adjacent interval in the direction Y. The first chip 111a may be connected to one second chip 112b not directly adjacent thereto through a second wire 132a, and the other first chip 111b may be connected to the other second chip 112a not directly adjacent thereto through another second wire 132 b. Similar to fig. 5B, the axes of the two second lines 132a, 132B intersect. The adjacent first chips 111a, 111b may be interconnected by a first line 131a and a second line 132c extending in the direction Y. The adjacent second chips 112a, 112b may be interconnected by a first line 131b extending in the direction Y and a second line 132 d. The adjacent first and second chips 111a and 112a are interconnected by a first line 131c extending in the lateral direction X, and the adjacent first and second chips 111b and 112b are interconnected by a first line 131d extending in the lateral direction X.

It should be understood that the top views of the first and second wire 131 and 132 layouts shown in fig. 5A to 5C are merely examples, and any number of first and second chips 111 and 112 may be interconnected by any suitable combination of the plurality of first and second wires 131 and 132.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. An electronic device, comprising:

a first chip;

a second chip adjacent to the first chip in a lateral direction;

the first circuit layer is located below the first chip and the second chip and comprises a first circuit and a second circuit, the first circuit is connected with the first chip and the second chip, the second circuit is connected with the first chip and the second chip, and the line width/line distance of the first circuit is different from the line width/line distance of the second circuit.

2. The electronic device according to claim 1, wherein the first wiring is closer to a gap between the first chip and the second chip than the second wiring.

3. The electronic device of claim 1, wherein a path length of the first line is less than a path length of the second line.

4. The electronic device according to claim 1, wherein a line width/pitch of the first wiring is smaller than a line width/pitch of the second wiring, and wherein the first wiring is located at a higher level than the second wiring in the first wiring layer.

5. The electronic device of claim 1, wherein the first line layer further comprises a bridge die located below and between the first chip and the second chip, wherein the bridge die is located on the first line, and wherein a line width/line spacing of the first line is smaller than a line width/line spacing of the second line.

6. The electronic device of claim 5, further comprising:

a second line layer located below the bridge die and electrically connected to the bridge die.

7. The electronic device of claim 6, further comprising:

a passive element located between the first and second circuit layers and electrically connected to the first or second chip.

8. The electronic device of claim 1,

in a top view, the first line overlaps both the first chip and the second chip, and the first line is arranged along a first axis extending in a transverse plane, and the second line is arranged along a second axis extending in the transverse plane.

9. The electronic device of claim 8, wherein the first axis is different from the second axis.

10. The electronic device of claim 8,

the first chip is connected to the two second chips through different second lines, and the second axes corresponding to the different second lines intersect in a top view.

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