CN217335431U - Large-current low-voltage drop controllable circuit - Google Patents
Large-current low-voltage drop controllable circuit Download PDFInfo
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- CN217335431U CN217335431U CN202220166532.2U CN202220166532U CN217335431U CN 217335431 U CN217335431 U CN 217335431U CN 202220166532 U CN202220166532 U CN 202220166532U CN 217335431 U CN217335431 U CN 217335431U
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Abstract
The utility model discloses a heavy current low pressure drop controllable circuit, including first control module, first PMOS pipe, second control module and second PMOS pipe. The first control module and the second control module respectively and correspondingly control the on-off states of the first PMOS tube and the second PMOS tube, so that the connection path between the input and output ends of the first circuit and the input and output ends of the second circuit is controlled to be switched on or switched off, and the flow direction of the switched-on current is controlled. The drain electrodes of the two PMOS tubes are connected by utilizing the characteristic that current can flow from the drain electrode to the source electrode when the PMOS tubes are cut off, only one of the PMOS tubes needs to be switched on, the current can also flow from the source electrode electric connection end of the PMOS tube in the switching-on state to the source electrode load end of the PMOS tube in the cutting-off state even if the other PMOS tube is in the cutting-off state, and the source electrodes of the two PMOS tubes can be used as electric connection ends or load ends, so that the bidirectional controllability of current transmission under any scene is realized; under the low-voltage large-current scene, the circuit efficiency and the current load are improved, and the circuit heating is reduced.
Description
Technical Field
The utility model relates to a control circuit technical field especially relates to a heavy current low pressure drop controllable circuit.
Background
In circuit development, a diode is often used to protect an upper-level circuit and output energy to a lower-level circuit, and the application of the existing diode in a low-voltage high-current circuit has the following problems:
1. the larger the current is, the larger the required diode volume is, the inflexible whole circuit scheme is caused, and the circuit is limited by space;
2. the larger the current is, the larger the conduction voltage drop is, so that the efficiency of the whole circuit is reduced, and the heat is serious;
3. the diode can only conduct in one direction, and the direction cannot be controlled.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a controllable circuit of heavy current low pressure drop aims at solving prior art, and the diode can only unidirectional conduction leads to the direction can not controlled scheduling problem.
An embodiment of the utility model provides a large current low pressure drop controllable circuit, including first control module, first PMOS pipe, second control module, second PMOS pipe, first circuit input/output end, second circuit input/output end, first resistance and second resistance.
The control end of the first PMOS tube is connected with the signal output end of the first control module;
the control end of the second PMOS tube is connected with the signal output end of the second control module;
the drain electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube, the source electrode of the first PMOS tube is respectively connected with the input and output end of the first circuit and one end of a first resistor, and the other end of the first resistor is grounded; the source electrode of the second PMOS tube is respectively connected with the input and output end of the second circuit and one end of a second resistor, and the other end of the second resistor is grounded;
the first control module and the second control module respectively and correspondingly control the on-off states of the first PMOS tube and the second PMOS tube, so that the connection path between the input and output ends of the first circuit and the input and output ends of the second circuit is controlled to be switched on or switched off, and the flow direction of the switched-on current is controlled.
The embodiment of the utility model discloses utilize PMOS pipe when ending, the characteristic that the electric current can flow to the source electrode from the drain electrode is continuous with the drain electrode of two PMOS pipes, only need switch on one of them PMOS pipe this moment, even another is at the off-state, the electric current also can connect the source electrode electricity end of the PMOS pipe of on-state to the source electrode load end of the PMOS pipe of off-state from the source electrode electricity of the PMOS pipe of on-state, the source electrode of two PMOS pipes all can regard as to connect the electricity end or load end, realize under any scene that the two-way of current transmission is controllable; under the low-voltage large-current scene, the circuit efficiency and the current load are improved, and the circuit heating is reduced.
Drawings
In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a circuit diagram of a large-current low-voltage drop controllable circuit provided by an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
Referring to fig. 1, a large current low dropout controllable circuit includes a first control module, a first PMOS transistor P1, a second control module, a second PMOS transistor P2, a first circuit input/output terminal, a second circuit input/output terminal, a first resistor R1, and a second resistor R2.
The control end of the first PMOS pipe P1 is connected with the signal output end of the first control module;
the control end of the second PMOS pipe P2 is connected with the signal output end of the second control module;
the drain of the first PMOS transistor P1 is connected to the drain of the second PMOS transistor P2, the source of the first PMOS transistor P1 is connected to the input/output end of the first circuit and one end of the first resistor R1, and the other end of the first resistor R1 is grounded; the source electrode of the second PMOS tube P2 is respectively connected with the input and output end of a second circuit and one end of a second resistor R2, and the other end of the second resistor R2 is grounded;
the first control module and the second control module respectively and correspondingly control the on-off states of the first PMOS tube P1 and the second PMOS tube P2, so that the on-off of a connecting path between the input and output ends of the first circuit and the second circuit is controlled, and the flow direction of on-current is controlled.
In the embodiment, by utilizing the characteristic that when the PMOS tubes are cut off, current can flow from the drain electrodes to the source electrodes, the drain electrodes of the two PMOS tubes are connected, only one of the PMOS tubes needs to be switched on at the moment, the other PMOS tube is in a cut-off state, the current can also flow from the source electrode power connection end of the PMOS tube in the switching-on state to the source electrode load end of the PMOS tube in the cutting-off state, and the source electrodes of the two PMOS tubes can be used as power connection ends or load ends, so that the bidirectional controllability of current transmission under any scenes is realized; under the low-voltage large-current scene, the circuit efficiency and the current load are improved, and the circuit heating is reduced.
Specifically, the first resistor R1 is to keep the voltage potential at the source terminal of the first PMOS transistor P1 stable, so as to avoid short circuit caused by direct grounding when the first PMOS transistor P1 and the second PMOS transistor P2 are fully turned on.
Specifically, the second resistor R2 keeps the voltage potential at the source terminal of the second PMOS transistor P2 stable, and prevents the first PMOS transistor P1 and the second PMOS transistor P2 from being directly grounded to cause short circuit when they are fully turned on.
Specifically, the first control module and the second control module may be control chips or may be another control circuit.
VCC and VDD are input and output, i.e., may be a load or a power supply, and are respectively an input and output terminal of the first circuit and an input and output terminal of the second circuit, and GND is a negative electrode or a ground signal.
In an embodiment, the first control module includes a first high level input port V1, a first control port CTRL _1, and a first NMOS transistor N1, a control end of the first NMOS transistor N1 is connected to the first control port CTRL _1, a source of the first NMOS transistor N1 is grounded, and a drain of the first NMOS transistor N1 is connected to the control end of the first PMOS transistor P1 and the first high level input port V1, respectively.
The port at which the drain of the first NMOS transistor N1 is connected to the control end of the first PMOS transistor is the signal output end of the first control module.
In this embodiment, the level of the control terminal of the first PMOS transistor P1 is controlled by the first NMOS transistor N1, that is, when the first NMOS transistor N1 is turned on, the control terminal of the first PMOS transistor P1 is grounded, the first PMOS transistor P1 is turned on, and current can pass through the first PMOS transistor P1 and be transmitted to the source terminal of the second PMOS transistor P2 in a state that the second PMOS transistor P2 is turned off, so as to supply power to the load.
Specifically, the first high output terminal maintains the control terminal of the first PMOS transistor P1 in a high state when the first NMOS transistor N1 is turned off, i.e., maintains the turn-off state of the first PMOS transistor P1.
Specifically, the first control port CTRL _1 is connected to a control chip, and when outputting a high level, the first NMOS transistor N1 can be controlled to be turned on.
In an embodiment, the first control module further includes a third resistor R3, the first high-level input port V1 is connected to one end of the third resistor R3, and the drain of the first NMOS transistor N1 is connected to the other end of the third resistor R3.
In this embodiment, in order to avoid short circuit or overload caused by direct grounding of the first high-level input port V1 when the first NMOS transistor N1 is turned on, a third resistor R3 is disposed between the first NMOS transistor N1 and the first high-level input port V1.
In an embodiment, the first control module further includes a second high level input port V2, a first diode D1 and a second diode D2, one end of the third resistor R3 is connected to the anode of the first diode D1 and the anode of the second diode D2, respectively, the cathode of the first diode D1 is connected to the first high level input port V1, and the cathode of the second diode D2 is connected to the second high level input port V2.
In this embodiment, in order to ensure that the circuit can still work normally when the first high-level input port V1 fails, the second high-level input port V2 is provided, and the second high-level input port V2 and the first high-level input port V1 are provided in parallel.
In order to avoid the backflow between the second high-level input port V2 and the first high-level input port V1, the first diode D1 and the second diode D2 are provided for isolation, i.e., backflow protection.
In an embodiment, the second control module includes a third high-level input port V3, a second control port CTRL _2, and a second NMOS transistor N2, a control end of the second NMOS transistor N2 is connected to the second control port CTRL _2, a source of the second NMOS transistor N2 is grounded, and a drain of the second NMOS transistor N2 is connected to a control end of the second PMOS transistor P2 and the third high-level input port V3, respectively.
The port at which the drain of the second NMOS transistor N2 is connected to the control end of the second PMOS transistor is the signal output end of the second control module.
In this embodiment, the level of the control terminal of the second PMOS transistor P2 is controlled by the second NMOS transistor N2, that is, when the second NMOS transistor N2 is turned on, the control terminal of the second PMOS transistor P2 is grounded, the second PMOS transistor P2 is turned on, and current can be transmitted to the source terminal of the first PMOS transistor P1 through the second PMOS transistor P2 and in a state that the first PMOS transistor P1 is turned off, so as to supply power to the load.
Specifically, the third high output terminal maintains the control terminal of the second PMOS transistor P2 in a high state when the second NMOS transistor N2 is turned off, i.e., maintains the turn-off state of the second PMOS transistor P2.
Specifically, the second control port CTRL _2 is connected to a control chip, and when outputting a high level, the second NMOS transistor N2 can be controlled to be turned on.
In an embodiment, the second control module further includes a fourth resistor R4, the third high-level input port V3 is connected to one end of the fourth resistor R4, and the drain of the second NMOS transistor N2 is connected to the other end of the fourth resistor R4.
In this embodiment, in order to avoid a short circuit or an overload caused by the direct grounding of the third high-level input port V3 when the second NMOS transistor N2 is turned on, a fourth resistor R4 is disposed between the second NMOS transistor N2 and the third high-level input port V3.
In an embodiment, the second control module further includes a fourth high level input port V4, a third diode D3, and a fourth diode D4, wherein one end of the fourth resistor R4 is connected to the anode of the third diode D3 and the anode of the fourth diode D4, respectively, the cathode of the third diode D3 is connected to the third high level input port V3, and the cathode of the fourth diode D4 is connected to the fourth high level input port V4.
In the present embodiment, in order to ensure that the circuit can still work normally when the third high input port V3 fails, the fourth high input port V4 is provided, and the fourth high input port V4 and the third high input port V3 are provided in parallel.
To avoid a backflow between the fourth high-level input port V4 and the third high-level input port V3, the third diode D3 and the fourth diode D4 are provided for isolation, i.e., a backflow protection.
The specific principle is as follows: the first control port CTRL _1 outputs a high level to control the conduction of the first NMOS transistor N1, the control terminal of the first PMOS transistor P1 is grounded and is at a low level, the first PMOS transistor P1 is conducted, a current can flow from one end of the source of the first PMOS transistor P1 to one end of the source of the second PMOS transistor P2, that is, two ends of the two PMOS transistors departing from each other are conducted, a power supply is provided at one end of the source of the first PMOS transistor P1, and a load is provided at one end of the source of the second PMOS transistor P2, so that power supply can be realized; this is also a control mode in which the first control port CTRL _1 outputs a high level when the two terminals are connected to the power supply and the load, respectively, and the second control port CTRL _2 can output a high level at this time, and can also maintain an initial state.
The second control port CTRL _2 outputs a high level to control the conduction of the second NMOS transistor N2, the control terminal of the second PMOS transistor P2 is grounded and is at a low level, the second PMOS transistor P2 is conducted, a current can flow from one end of the source of the second PMOS transistor P2 to one end of the source of the first PMOS transistor P1, that is, two ends of the two PMOS transistors departing from each other are conducted, a power supply is provided at one end of the source of the second PMOS transistor P2, and a load is provided at one end of the source of the first PMOS transistor P1, so that power supply can be realized; this is also a control mode in which the second control port CTRL _2 outputs a high level when the two ends are connected to the power supply and the load, respectively, and the first control port CTRL _1 may output a high level at this time, or may keep an initial state.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope of the present invention, and these modifications or replacements should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (7)
1. A large current low drop-out controllable circuit, comprising:
a first control module;
the control end of the first PMOS tube is connected with the signal output end of the first control module;
a second control module;
the control end of the second PMOS tube is connected with the signal output end of the second control module;
a first circuit input/output terminal and a second circuit input/output terminal;
a first resistor and a second resistor;
the drain electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube, the source electrode of the first PMOS tube is respectively connected with the input and output end of the first circuit and one end of the first resistor, and the other end of the first resistor is grounded; the source electrode of the second PMOS tube is respectively connected with the input and output ends of the second circuit and one end of the second resistor, and the other end of the second resistor is grounded;
the first control module and the second control module respectively and correspondingly control the on-off states of the first PMOS tube and the second PMOS tube, so that the connection path between the input and output ends of the first circuit and the input and output ends of the second circuit is controlled to be switched on or switched off, and the flow direction of the switched-on current is controlled.
2. A high current low drop controllable circuit according to claim 1, wherein: the first control module comprises a first high-level input port, a first control port and a first NMOS (N-channel metal oxide semiconductor) tube, the control end of the first NMOS tube is connected with the first control port, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is respectively connected with the control end of the first PMOS tube and the first high-level input port.
3. A high current low drop controllable circuit according to claim 2, wherein: the first control module further comprises a third resistor, the first high-level input port is connected with one end of the third resistor, and the drain electrode of the first NMOS tube is connected with the other end of the third resistor.
4. A high current low drop controllable circuit according to claim 3, wherein: the first control module further comprises a second high-level input port, a first diode and a second diode, one end of the third resistor is connected with the anode of the first diode and the anode of the second diode respectively, the cathode of the first diode is connected with the first high-level input port, and the cathode of the second diode is connected with the second high-level input port.
5. A high current low drop controllable circuit according to claim 1, wherein: the second control module comprises a third high-level input port, a second control port and a second NMOS tube, wherein the control end of the second NMOS tube is connected with the second control port, the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is respectively connected with the control end of the second PMOS tube and the third high-level input port.
6. A high current low drop controllable circuit according to claim 5, wherein: the second control module further comprises a fourth resistor, the third high-level input port is connected with one end of the fourth resistor, and the drain electrode of the second NMOS tube is connected with the other end of the fourth resistor.
7. A high current low drop controllable circuit according to claim 6, wherein: the second control module further comprises a fourth high-level input port, a third diode and a fourth diode, one end of the fourth resistor is connected with the anode of the third diode and the anode of the fourth diode respectively, the cathode of the third diode is connected with the third high-level input port, and the cathode of the fourth diode is connected with the fourth high-level input port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220166532.2U CN217335431U (en) | 2022-01-21 | 2022-01-21 | Large-current low-voltage drop controllable circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220166532.2U CN217335431U (en) | 2022-01-21 | 2022-01-21 | Large-current low-voltage drop controllable circuit |
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| Publication Number | Publication Date |
|---|---|
| CN217335431U true CN217335431U (en) | 2022-08-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220166532.2U Active CN217335431U (en) | 2022-01-21 | 2022-01-21 | Large-current low-voltage drop controllable circuit |
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| CN (1) | CN217335431U (en) |
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- 2022-01-21 CN CN202220166532.2U patent/CN217335431U/en active Active
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