CN217334084U - Electrostatic protection device and electronic equipment - Google Patents
Electrostatic protection device and electronic equipment Download PDFInfo
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- CN217334084U CN217334084U CN202221037653.3U CN202221037653U CN217334084U CN 217334084 U CN217334084 U CN 217334084U CN 202221037653 U CN202221037653 U CN 202221037653U CN 217334084 U CN217334084 U CN 217334084U
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Abstract
The application provides an electrostatic protection device and electronic equipment, and relates to the technical field of semiconductors. The low-capacitance electrostatic protection device comprises a semiconductor substrate of a first doping type; a buried layer located at one side of the substrate and having a second doping type; the epitaxial layer is positioned on one side of the substrate and the buried layer and has a second doping type; the doping concentration of the buried layer is greater than that of the epitaxial layer; the first doping area is positioned in the epitaxial layer and has a second doping type; a second doped region located in the epitaxial layer and having a second doping type; wherein the second doped region is isolated from the first doped region; a third doped region located in the first doped region and having the first doping type; the third doped region, the first doped region, the epitaxial layer, the buried layer and the substrate form a triode structure. The electrostatic protection device and the electronic equipment have the advantages of low device capacitance and low residual voltage.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to an electrostatic protection device and electronic equipment.
Background
With the rapid development of electronic products, electrostatic discharge protection (ESD) devices are increasingly applied to various electronic products to overcome static electricity generated during the manufacturing, packaging, testing and transportation of the products. As the critical dimension of devices in IC circuits is smaller and smaller, among many factors causing IC function failure, ESD device failure has become one of the main factors, so in circuit design, an independent ESD protection device is often added in the peripheral design of the circuit to protect sensitive devices.
With the development of high-speed data transmission interfaces, in order to meet the requirements of medium and high-speed interfaces, such as keys, USB2.0, USB3.0, VGA, HDMI, network interface, and the like, the ESD device also needs to reduce the capacitance to protect the integrity of information transmission. Generally, in order to ensure that signal transmission is not affected, the capacitance of the ESD device needs to be less than 1pF, and the applications of USB3.0, USB3.1 and HDMI2.0 cannot exceed 0.5 pF. However, in the prior art, the capacitance of the electrostatic protection device is high.
In summary, the capacitance of the electrostatic protection device is high in the prior art.
SUMMERY OF THE UTILITY MODEL
An object of the present application is to provide an electrostatic protection device and an electronic apparatus, so as to solve the problem that the capacitance of the electrostatic protection device is high in the prior art.
In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:
in a first aspect, an embodiment of the present application provides an electrostatic protection device, where the electrostatic protection device includes:
a semiconductor substrate of a first doping type;
a buried layer located at one side of the substrate and having a second doping type;
the epitaxial layer is located on one side of the substrate and the buried layer and is provided with a second doping type;
a first doped region located within the epitaxial layer and having a second doping type;
a second doped region located within the epitaxial layer and having a second doping type; wherein the second doped region is isolated from the first doped region;
a third doped region located within the first doped region and having a first doping type; wherein the content of the first and second substances,
the third doped region, the first doped region, the epitaxial layer, the buried layer and the substrate form a triode structure.
Optionally, the electrostatic protection device further comprises:
a conductive trench penetrating to the substrate along the surface of the epitaxial layer; the inner wall of the conductive groove positioned in the epitaxial layer is provided with an insulating layer, and the insulating layer is not arranged on part or all of the inner wall of the conductive groove positioned in the substrate;
a conductive medium located within the conductive trench;
a first electrode connected to the third doped region;
a second electrode connected to the second doped region;
a third electrode connected to the conductive medium; wherein the first electrode, the second electrode and the third electrode are located on the same side of the epitaxial layer.
Optionally, the depth of the conductive trench is greater than the width of a depletion layer when a diode formed by the epitaxial layer and the substrate is in reverse breakdown.
Optionally, the electrostatic protection device further comprises:
an isolation trench penetrating to the substrate along the surface of the epitaxial layer; the isolation trench is used for isolating the first electrode, the second electrode and the third electrode;
an insulating dielectric located within the isolation trench.
Optionally, the depth of the isolation trench is greater than the width of a depletion layer when a diode formed by the epitaxial layer and the substrate breaks down in the reverse direction.
Optionally, the insulating medium comprises undoped polysilicon; the conductive medium includes polysilicon having a first doping type.
Optionally, the insulating layer comprises a single layer of oxide or a plurality of layers of insulating dielectric.
Optionally, the substrate is heavily doped, the epitaxial layer is lightly doped, and the first doped region, the second doped region, and the second doped region are heavily doped.
Optionally, the first doping type is P-type, and the second doping type is N-type; or the like, or, alternatively,
the first doping type is N type, and the second doping type is P type.
On the other hand, the embodiment of the application also provides electronic equipment, and the electronic equipment comprises the electrostatic protection device.
Compared with the prior art, the method has the following beneficial effects:
the embodiment of the application provides an electrostatic protection device and electronic equipment, wherein the low-capacitance electrostatic protection device comprises a semiconductor substrate of a first doping type; a buried layer located at one side of the substrate and having a second doping type; the epitaxial layer is positioned on one side of the substrate and the buried layer and has a second doping type; the doping concentration of the buried layer is greater than that of the epitaxial layer; the first doping area is positioned in the epitaxial layer and has a second doping type; a second doped region located in the epitaxial layer and having a second doping type; wherein the second doped region is isolated from the first doped region; a third doped region located in the first doped region and having the first doping type; the third doped region, the first doped region, the epitaxial layer, the buried layer and the substrate form a triode structure. Because the triode structure is formed by the third doped region, the first doped region, the epitaxial layer, the buried layer and the substrate in the electrostatic protection device provided by the application, and the triode structure has a sweeping function, the capacitance of the device is lower, the effect of low capacitance is realized, and the residual voltage of the electrostatic protection device is lower.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a circuit diagram of an electrostatic protection device provided in the prior art.
Fig. 2 is a schematic cross-sectional view of an electrostatic protection device provided in the prior art.
Fig. 3 is a schematic cross-sectional view of an electrostatic protection device according to an embodiment of the present application.
Fig. 4 is a schematic cross-sectional view illustrating a first process of manufacturing an electrostatic protection device according to an embodiment of the present disclosure.
Fig. 5 is a schematic cross-sectional view illustrating a second process of manufacturing an electrostatic protection device according to an embodiment of the present disclosure.
Fig. 6 is a schematic cross-sectional view illustrating a third process of manufacturing an electrostatic protection device according to an embodiment of the present disclosure.
Fig. 7 is a schematic cross-sectional view illustrating a fourth exemplary embodiment of a process for manufacturing an electrostatic protection device according to the present disclosure.
Fig. 8 is a schematic cross-sectional view illustrating a fifth exemplary embodiment of a process for manufacturing an electrostatic protection device according to the present disclosure.
Fig. 9 is a schematic cross-sectional view illustrating a sixth exemplary embodiment of a process for manufacturing an electrostatic protection device according to the present disclosure.
In the figure: 100-a substrate; 101-buried layer; 102-an epitaxial layer; 103-a first doped region; 104-a second doped region; 105-a third doped region; 106-isolation trenches; 107-conductive trenches; 108-a conductive medium; 109-a second electrode; 110-a first electrode; 111-third electrode.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments and features of the embodiments described below can be combined with each other without conflict.
As described in the background art, the electrostatic protection device in the related art has a problem of high capacitance.
For example, fig. 1 shows a unidirectional low-capacitance ESD circuit structure, the device achieves the purpose of reducing capacitance by serially connecting the capacitance reducing tubes D1 and Dz, and the overall capacitance of the device is determined by the capacitance reducing tube D1 and the capacitance reducing tube D2. FIG. 2 shows a cross-sectional structure of a conventional ESD with low capacitance, wherein a P-sub substrate and an N-epi high resistance epitaxial layer are formed as D2; forming D1 by the SP injection region and the N-epi high-resistance epitaxial layer; dz is formed by the P-Sub substrate and the NBL buried layer, the resistivity and the thickness of an n-epi epitaxial region need to be improved when the capacitance of D1 and D2 is reduced, the VBR (breakdown voltage) of the device is formed by D1 forward voltage drop and Dz breakdown voltage, and due to the fact that the common working voltage is 3.3V or 5V, the doping concentration of the NBL buried layer and the two sides of the P-Sub substrate need to be improved, and the lower VBR can be obtained.
However, after the ESD product shown in fig. 2 is subjected to ESD shock or surge shock, since the back substrate is GND, both forward surge and reverse surge channels need to flow out or in through the substrate, the series resistance of the ESD product is high, Dz is a diode structure, and low-capacitance products D1 and D2 need to pass through a high-resistance layer, so that the residual voltage of the whole device is high, and the capacitance of the device is high.
In view of this, the present disclosure provides an electrostatic protection device, which achieves the purpose of reducing the capacitance and residual voltage of the device by forming a triode inside the device.
The following is an exemplary description of the electrostatic protection device provided in the present application:
as an alternative implementation, the electrostatic protection device comprises:
referring to fig. 3, a semiconductor substrate 100 of a first doping type, a buried layer 101 located at one side of the substrate 100 and having a second doping type, an epitaxial layer 102 located at one side of the substrate 100 and the buried layer 101 and having the second doping type, a first doping region 103 located in the epitaxial layer 102 and having the second doping type, and a second doping region 104 located in the epitaxial layer 102 and having the second doping type; wherein, the second doped region 104 is isolated from the first doped region 103, located in the first doped region 103 and has a third doped region 105 of the first doping type; the third doped region 105, the first doped region 103, the epitaxial layer 102, the buried layer 101 and the substrate 100 form a triode structure.
In the electrostatic protection device provided by the application, the third doped region 105, the first doped region 103, the epitaxial layer 102, the buried layer 101 and the substrate 100 form a low-capacitance triode junction with a sweeping-back characteristic, so that the capacitance of the device is lower, the effect of low capacitance is realized, and the residual voltage of the electrostatic protection device is lower.
In order to further improve the performance of the esd protection device, please continue to refer to fig. 1, the esd protection device further includes:
a conductive trench 107 penetrating to the substrate 100 along the surface of the epitaxial layer 102; wherein, the inner wall of the conductive trench 107 located in the epitaxial layer 102 is provided with an insulating layer, and the inner wall portion or all of the conductive trench 107 located in the substrate 100 is not provided with an insulating layer; a conductive medium 108 located within the conductive trench 107; a first electrode 110 connected to the third doped region 105; a second electrode 109 connected to the second doped region 104; a third electrode 111 connected to the conductive medium 108; the first electrode 110, the second electrode 109, and the third electrode 111 are located on the same side of the epitaxial layer 102.
By this implementation, so that the third electrode 111 can be reached through the conductive trench 107, the third electrode 111 is no longer located on the substrate 100, and the series resistance can be significantly reduced. The surge capacity and the clamping capacity of the device can be obviously improved, and the device structure and the process method can meet the ESD protection requirement of a high-speed signal port. Therefore, the back substrate 100 can be subjected to insulation treatment, and the special conductive trench 107 is formed on the surface of the chip through deep trench etching and deposition processes to lead out the third electrode 111, so that the on-resistance of the device in the ESD protection process is reduced, and the residual voltage of the device is reduced.
The insulating layer includes a single-layer oxide layer or a multi-layer insulating dielectric, for example, the insulating layer is an oxide layer or a multi-layer dielectric of an oxide layer and silicon nitride.
It is understood that the depth of the conductive trench 107 is greater than the width of the depletion layer when the diode formed by the epitaxial layer 102 and the substrate 100 is reverse-broken down.
In addition, the electrostatic protection device further includes an isolation trench 106 penetrating to the substrate 100 along the surface of the epitaxial layer 102 and an insulating medium located in the isolation trench 106. The isolation trench 106 is used to isolate the first electrode 110, the second electrode 109, and the third electrode 111.
For isolation purposes, the depth of the isolation trench 106 is greater than the depletion layer width at reverse breakdown of the diode formed by the epitaxial layer 102 and the substrate 100. Moreover, insulating layer dielectrics are required to be isolated from the epitaxial layer 102 on both sides of the trench, and doped polysilicon is used in the contact region between the bottom of the trench and the substrate 100. Wherein the insulating medium comprises undoped polysilicon or Tetraethylorthosilicate (TEOS); the conductive medium 108 comprises polysilicon having a first doping type.
Based on the electrostatic protection device provided by the present application, as an implementation manner, the substrate 100 is heavily doped, the epitaxial layer 102 is lightly doped, and the first doped region 103, the second doped region 104, and the second doped region 104 are heavily doped.
Also, the doping type is not limited in this application, for example, when the first doping type is P type, the second doping type is N type. When the first doping type is N type, the second doping type is P type.
Based on the above embodiment, the present application also provides an electronic apparatus including the above electrostatic protection device.
Based on the implementation manner, the embodiment of the application also provides a method for manufacturing the electrostatic protection device.
Referring to fig. 4, a buried layer having a second doping type is formed on a semiconductor substrate having a first doping type, and an epitaxial layer having the second doping type is formed on the surface of the substrate and the buried layer. Wherein the substrate resistivity is selected to be 0.01-0.001 omega cm, the buried layer implantation dosage is 1E14-1E16, and the implantation energy is 20-80 KeV; the resistivity of the epitaxial layer is 50-1000 omega cm, and the thickness is 8-20 μm. And the implantation dosage of the first doping region is 1E14-5E15, and the implantation energy is 50-120 KeV. The implantation dosage of the second and third doping regions is 1E15-5E15, and the implantation energy is 30-80 KeV.
Referring to fig. 5, an oxide layer is formed on the surface of the epitaxial layer, and then a first doped region having a second doping type is formed in the epitaxial layer through photolithography and ion implantation processes.
Referring to fig. 6, a second doping region having a second doping type is formed in the epitaxial layer by photolithography and ion implantation processes;
referring to fig. 7, the third doped region with the first doping is formed in the first doped region by photolithography and ion implantation processes.
Referring to fig. 8, isolation trenches are formed in the second doped region and the epitaxial layer by photolithography and dry etching, and simultaneously, isolation trenches are also formed in the first doped region, the third doped region and the epitaxial layer.
Meanwhile, a conduction groove is formed in the epitaxial layer through photoetching and dry etching processes.
Then, referring to fig. 9, a dielectric isolation layer is formed in the isolation trench, and at the same time, a dielectric isolation layer is formed in the conductive trench through a deposition process, and then the bottom of the conductive trench is etched away through a dry etching process in this region, and then polysilicon with a first doping type doped in a conduction type is deposited through the deposition process, so that the conductive trench is ensured to be directly communicated with the substrate and insulated from the epitaxial layer.
Thereafter, as shown in fig. 3, a passivation layer is formed on the surface of the epitaxial layer through a chemical vapor deposition process, a contact hole region is formed on the surface of the passivation layer through a photolithography and wet etching process, and then a first electrode is formed above the contact hole of the second doping region through an evaporation or sputtering process; forming a second electrode above the third doped region contact hole; a third electrode is formed over the conductive trench contact hole.
And then thinning the substrate to form the back of the chip, and optionally, carrying out insulation treatment on the back of the chip in the packaging process.
In summary, the embodiments of the present application provide an electrostatic protection device and an electronic apparatus, where the low-capacitance electrostatic protection device includes a semiconductor substrate of a first doping type; a buried layer located at one side of the substrate and having a second doping type; the epitaxial layer is positioned on one side of the substrate and the buried layer and has a second doping type; the doping concentration of the buried layer is greater than that of the epitaxial layer; the first doping area is positioned in the epitaxial layer and has a second doping type; a second doped region located in the epitaxial layer and having a second doping type; wherein the second doped region is isolated from the first doped region; a third doped region located in the first doped region and having the first doping type; the third doped region, the first doped region, the epitaxial layer, the buried layer and the substrate form a triode structure. Because the triode structure is formed by the third doped region, the first doped region, the epitaxial layer, the buried layer and the substrate in the electrostatic protection device provided by the application, and the triode structure has a sweeping function, the capacitance of the device is lower, the effect of low capacitance is realized, and the residual voltage of the electrostatic protection device is lower.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
It will be evident to those skilled in the art that the application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
1. An electrostatic protection device, comprising:
a semiconductor substrate of a first doping type;
a buried layer located at one side of the substrate and having a second doping type;
the epitaxial layer is located on one side of the substrate and the buried layer and is provided with a second doping type;
a first doped region located within the epitaxial layer and having a second doping type;
a second doped region located within the epitaxial layer and having a second doping type; wherein the second doped region is isolated from the first doped region;
a third doped region located within the first doped region and having a first doping type; wherein the content of the first and second substances,
the third doped region, the first doped region, the epitaxial layer, the buried layer and the substrate form a triode structure.
2. The electrostatic protection device of claim 1, further comprising:
a conductive trench penetrating to the substrate along the surface of the epitaxial layer; the inner wall of the conductive groove positioned in the epitaxial layer is provided with an insulating layer, and the insulating layer is not arranged on part or all of the inner wall of the conductive groove positioned in the substrate;
a conductive medium located within the conductive trench;
the first electrode is connected with the third doped region;
a second electrode connected to the second doped region;
a third electrode connected to the conductive medium; wherein the first electrode, the second electrode and the third electrode are located on the same side of the epitaxial layer.
3. The electrostatic protection device of claim 2, wherein a depth of the conductive trench is greater than a depletion layer width at reverse breakdown of a diode formed by the epitaxial layer and the substrate.
4. The electrostatic protection device of claim 2, further comprising:
an isolation trench penetrating to the substrate along the surface of the epitaxial layer; the isolation trench is used for isolating the first electrode, the second electrode and the third electrode;
an insulating dielectric located within the isolation trench.
5. The electrostatic protection device according to claim 4, wherein a depth of the isolation trench is larger than a depletion layer width at a reverse breakdown of a diode formed by the epitaxial layer and the substrate.
6. The electrostatic protection device of claim 4, wherein said insulating dielectric comprises undoped polysilicon; the conductive medium includes polysilicon having a first doping type.
7. The electrostatic protection device of claim 2, wherein the insulating layer comprises a single layer of oxide or a multilayer insulating medium.
8. The electrostatic protection device of claim 1, wherein the substrate is heavily doped, the epitaxial layer is lightly doped, and the first doped region, the second doped region, and the second doped region are heavily doped.
9. The electrostatic protection device of claim 1, wherein the first doping type is P-type and the second doping type is N-type; or the like, or, alternatively,
the first doping type is N type, and the second doping type is P type.
10. An electronic apparatus characterized in that it comprises an electrostatic protection device according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202221037653.3U CN217334084U (en) | 2022-04-29 | 2022-04-29 | Electrostatic protection device and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202221037653.3U CN217334084U (en) | 2022-04-29 | 2022-04-29 | Electrostatic protection device and electronic equipment |
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| CN217334084U true CN217334084U (en) | 2022-08-30 |
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| CN202221037653.3U Active CN217334084U (en) | 2022-04-29 | 2022-04-29 | Electrostatic protection device and electronic equipment |
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