CN217333605U - Display panel compatible interface circuit - Google Patents
Display panel compatible interface circuit Download PDFInfo
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- CN217333605U CN217333605U CN202122343933.9U CN202122343933U CN217333605U CN 217333605 U CN217333605 U CN 217333605U CN 202122343933 U CN202122343933 U CN 202122343933U CN 217333605 U CN217333605 U CN 217333605U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides a compatible interface circuit of display panel, compatible interface circuit includes: the signal processing board, the first interface board, one end of the said first interface board is electrically connected with said signal processing board; one end of the second interface board is electrically connected with the signal processing board, and the other end of the first interface board and the other end of the second interface board comprise interfaces capable of being connected with different display panels. According to the display panel, the first interface board and the second interface board can be connected with different display panels, and compared with the situation that the interface type in the prior art can only correspond to one display panel, the display panel can be connected through the first interface board and the second interface board, the problem that the matching of a plurality of display panels cannot be realized through some interface types is solved, and the cost is saved.
Description
Technical Field
The application relates to the technical field of display devices, in particular to a display panel compatible interface circuit.
Background
Thin Film Transistor Liquid Crystal displays (TFT-LCDs) are one of the major types of flat panel displays, and have become an important Display platform in modern IT and video products. With the pursuit of low cost, the TCONless architecture is becoming the mainstream, and each display panel factory has its own XRboard and XLboard interface definitions. However, the existing interface type can only correspond to one display panel basically, and can not realize the adaptation of multiple display panels, which causes the waste of cost.
Disclosure of Invention
The embodiment of the application provides a display panel compatible interface circuit, which solves the problem that the existing interface type can not realize the adaptation of a plurality of display panels.
The embodiment of the application provides a compatible interface circuit of display panel, compatible interface circuit includes:
a signal processing board;
one end of the first interface board is electrically connected with the signal processing board; and
one end of the second interface board is electrically connected with the signal processing board, and the other end of the first interface board and the other end of the second interface board comprise interfaces capable of being connected with different display panels.
Optionally, the interfaces include a first type interface and a second type interface, the first type interface fixedly outputs a first signal, and the second type interface can selectively output a second signal or a third signal.
Optionally, the second type of interface includes a first interface, the first interface outputs an XON signal or an AVCM signal,
when the first interface is connected with an external first display panel, the output of the first interface is an XON signal which is used for providing a shutdown discharge signal for the external first display panel;
when the first interface is connected with an external second display panel, the output of the first interface is an AVCOM signal for providing an array substrate side reference voltage for the external second display panel.
Optionally, the second type of interface further includes a second interface, and when the second interface is connected to an external first display panel, the second interface outputs a RESRT signal, which is used to selectively output a clear signal or a signal for resetting a current in the COA circuit to the external first display panel.
Optionally, the second type of interface includes a third interface, and when the third interface is connected to an external third display panel, an output of the third interface is an LC1 signal, which is used to provide a switching signal of a GOA circuit for the external third display panel.
Optionally, the second type of interface includes a fourth interface, when the fourth interface is connected to the external second display panel, the fourth interface outputs an LC2 signal for providing a switching signal of the GOA circuit to the external second display panel, and the LC1 interface and the LC2 interface perform current switching within a preset time.
Optionally, the second type of interface further includes a fifth interface, and when the fifth interface is connected to an external fourth display panel, the fifth interface outputs a VGH signal, which is used to provide a GOA power supply voltage for the external fourth display panel.
Optionally, the second type of interface further includes a sixth interface, and when the sixth interface is connected to an external fifth display panel, an output of the sixth interface is an SVCM signal, which is used to provide a reference voltage on a color film side for the external fifth display panel.
Optionally, the first type of interface includes a seventh interface, an eighth interface to a twenty-first interface, and a twenty-second interface, where an output of the seventh interface is a VAA signal, outputs of the eighth interface to the twenty-first interface are GM1 to GM14 whose voltage values decrease in sequence, outputs of the GM1 to the GM14 are reference voltages, and an output of the twenty-second interface is a VDD1V8 signal;
the voltage value output by the VAA interface is greater than that output by the GM1, and the voltage value output by the GM1 is greater than that output by the VDD1V8 interface.
Optionally, the first type of interface further includes a twenty-third interface, an output of the twenty-third interface is a VSS1 signal, the second type of interface further includes a twenty-fourth interface, an output of the twenty-fourth interface is a VSS2 signal, and a voltage value of the VSS1 signal is greater than or equal to a voltage value of the VSS2 signal.
Optionally, the first type of interface further includes a twenty-fifth interface, where an output of the twenty-fifth interface is a LOCK signal, and is used for providing a control signal fed back by the driver IC.
Optionally, the second interface board further includes a twenty-sixth interface, where an output of the twenty-sixth interface is an SPI signal, and is used for connecting Flash with the SOC.
The beneficial effect of this application lies in: the embodiment of the application provides a display panel compatible interface circuit, which comprises a first interface board and a second interface board, wherein different display panels can be connected through the first interface board and the second interface board, and compared with the prior art that the interface type can only correspond to one display panel, the display panel compatible interface circuit can realize the connection of a plurality of display panels through the first interface board and the second interface board, thereby solving the problem that some interface types can not realize the adaptation of a plurality of types of display panels and saving the cost.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the application, and that other drawings can be derived from these drawings by a person skilled in the art without inventive effort.
For a more complete understanding of the present application and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings. Wherein like reference numerals refer to like parts in the following description.
Fig. 1 is a schematic diagram of a first structure of a display panel compatible interface circuit provided in this embodiment;
fig. 2 is a schematic diagram of a second structure of the display panel compatible interface circuit provided in this embodiment;
fig. 3 is an input interface definition table of the first interface board in the display panel compatible interface circuit shown in fig. 1;
fig. 4 is an input interface definition table of the second interface board in the display panel compatible interface circuit shown in fig. 1.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Referring to fig. 1 to fig. 2, fig. 1 is a first structural schematic diagram of a display panel compatible interface circuit provided in this embodiment, and fig. 2 is a second structural schematic diagram of the display panel compatible interface circuit provided in this embodiment. The embodiment of the present application provides a display panel compatible interface circuit 100, which includes a first interface board 110, a second interface board 120 and a signal processing board 130. One end of the first interface board 110 is connected to the signal processing board 130, and the other end of the first interface board 110 is connected to the display panel. One end of the second interface board 120 is connected to the signal processing board 130, and the other end of the second interface board 120 is connected to the display panel. The other end of the first interface board 110 and the other end of the second interface board 120 include interfaces capable of connecting different display panels, so that the other end of the first interface board 110 and the other end of the second interface board 120 can connect different display panels. Different display panels are connected through the first interface board 110 and the second interface board 120, and then the first interface board 110 and the second interface board 120 are used for realizing the adaptation of a plurality of display panels, compared with the prior art, hardware modification for adapting a plurality of types of display screens is not needed, only the signal processing board 130 is needed to adjust software according to the specifications of the display screens, the resource waste is reduced, and the cost is saved.
The interface comprises a first type interface and a second type interface, the first type interface fixedly outputs a first signal, and the second type interface can selectively output a second signal or a third signal. It can be understood that, when the first interface board 110 is connected to a display panel different from the outside, the first type of interface is used to fix the definition corresponding to the output interface, and the second type of interface outputs different signals, i.e., the second signal or the third signal, according to the display panel different from the outside. It will be appreciated that the second signal may be a circuit signal defined by the interface, or may be a corresponding null signal output.
The second type of interface includes a first interface, which outputs an XON signal or an AVCM signal that can be selectively output, for example, when the first interface board 110 is connected to the external first display panel, the first interface outputs the XON signal to provide the shutdown discharge signal to the external first display panel 210. When the first interface is connected to the external second display panel 220, the first interface outputs an AVCOM signal for supplying an array substrate-side reference voltage to the external second display panel 220. The first interface can select to output different signals according to different display panels connected with the outside, one interface is used for realizing two functions, and the first interface is connected with a plurality of different display panels through a compatible interface circuit, so that the cost is saved.
It can be understood that the first interface may be disposed at the twelfth interface, the thirteenth interface, or any interface of the first interface board 110, and only needs to implement the function, and the specific setting condition is set according to actual needs, and is not limited specifically herein.
The second type of interface includes a second interface, and when the second interface is connected to the external first display panel 210, the second interface outputs a RESRT signal, which is used to selectively output a clear signal or a signal for resetting a current in the COA circuit to the external first display panel 210. It should be noted that in some embodiments, the first interface and the second interface are disposed adjacent to each other. Illustratively, the first interface is disposed at the twelfth interface of the first interface board 110, and the second interface is disposed at the thirteenth interface of the first interface board 110. It is to be understood that the position setting of the second interface may be set according to practical situations, and is not particularly limited herein.
The second type of interface comprises a third interface, and when the third interface is connected with an external third display panel, the output of the third interface is an LC1 signal for providing a switching signal of a GOA circuit for the external third display panel;
the second type of interface includes a fourth interface, and when the fourth interface is connected to the external second display panel 220, the fourth interface outputs an LC2 signal for providing a switching signal of the GOA circuit to the external second display panel 220.
The LC1 interface and the LC2 interface switch wheel flows within preset time. It is understood that when the output of the LC1 interface is high, the output of the LC2 interface is low, and when the output of the LC1 interface is low, the output of the LC2 interface is high. By switching within a preset time, the situation that the GOA circuit works continuously to generate drift can be avoided.
The second type of interface comprises a fifth interface, and when the fifth interface is connected with an external fourth display panel, the fifth interface outputs a VGH signal for providing a GOA power supply voltage for the external fourth display panel.
The second type of interface further comprises a sixth interface, and when the sixth interface is connected with an external fifth display panel, the output of the sixth interface is an SVCM signal, and the sixth interface is used for providing a reference voltage on a color film side for the external fifth display panel.
The first interface comprises a seventh interface to a twenty-second interface, the output of the seventh interface is VAA signals, the output of the eighth interface to the twenty-first interface is GM1 to GM14 with the voltage values decreasing in sequence, the output of the GM1 to GM14 are reference voltages, and the output of the twenty-second interface is VDD1V8 signals. In some embodiments, the voltage values of GM1 to GM14 are related as follows: GM1> GM2> GM3> GM4> GM5> GM6> GM7> HVAA +0.2V > HVAA-0.2V > GM8> GM9> GM10> GM11> GM12> GM13> GM14> 0.2V.
The voltage value output by the VAA interface is greater than that output by the GM1, and the voltage value output by the GM1 is greater than that output by the VDD1V8 interface. In some embodiments, VAA-0.2V > GM 1.
In some embodiments, the GM1 is disposed adjacent to the VAA interface, the VAA interface is disposed on a side of the GM1 away from the GM2, the GM14 is disposed adjacent to the VDD1V8 interface, and the VDD1V8 interface is disposed on a side of the GM14 away from the GM13, a voltage value output by the VAA interface is greater than a voltage value output by the GM1, and a voltage value output by the GM14 interface is greater than a voltage value output by the VDD1V8, so that a situation of burnout caused by a high voltage input to a low voltage interface during oblique insertion can be avoided.
The first type interface further comprises a twenty-third interface, the twenty-third interface outputs a VSS1 signal, the second type interface further comprises a twenty-fourth interface, the twenty-fourth interface outputs a VSS2 signal, and the voltage value of the VSS1 signal is larger than or equal to the voltage value of the VSS2 signal. By setting the relationship between the voltage value of the VSS1 signal and the voltage value of the VSS1 signal, the order of the interfaces of the first interface board 110 can be set, and erroneous insertion can be avoided.
The first type of interface further comprises a twenty-fifth interface, wherein the output of the twenty-fifth interface is a LOCK signal and is used for controlling signals fed back by the driving IC.
The first type of interface also comprises Data (1+) to Data (12-) which are P2P protocol Data differential signals connected between the SOC and the driving IC.
The first interface board 110 includes sixty interfaces, and the second interface board 120 includes sixty interfaces, it should be noted that in some embodiments, the interface corresponding to the first interface board 110 is identical to the interface corresponding to the second interface board 120, and in other embodiments, the interface corresponding to the first interface board is not identical to the interface corresponding to the second interface board 120. Illustratively, in some embodiments, the second interface board 120 includes twenty-six interfaces for SPI signals connected between Flash and SOC: SPI _ MDI _ SDO, SPI _ CS, SPI _ SCK, SPI _ MDO _ SDI.
Referring to fig. 3 and fig. 4, fig. 3 is an input interface definition table of the first interface board 110 in the display panel compatible interface circuit 100 shown in fig. 1, and fig. 4 is an input interface definition table of the second interface board 120 in the display panel compatible interface circuit 100 shown in fig. 1. The sixty interfaces of the first interface board 110 in the display panel compatible interface circuit 100 provided in the embodiment of the present application are defined as shown in fig. 3, and the sixty interfaces of the second interface board 120 in the display panel compatible interface circuit 100 provided in the embodiment of the present application are defined as shown in fig. 4, it is understood that the arrangement order of all the interfaces of the first interface board 110 may be the same as or different from the order of the interfaces in fig. 3 and 4, and the specific arrangement is set according to the actual situation, and is not specifically limited herein.
A display panel compatible interface circuit provided in the embodiments of the present application is described in detail above. The principles and embodiments of the present application have been described herein using specific guidelines, the above examples being provided only to aid in the understanding of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (12)
1. A display panel compatible interface circuit, the compatible interface circuit comprising:
a signal processing board;
one end of the first interface board is electrically connected with the signal processing board; and
one end of the second interface board is electrically connected with the signal processing board, and the other end of the first interface board and the other end of the second interface board comprise interfaces capable of being connected with different display panels.
2. The compatible interface circuit of claim 1, wherein the interface comprises a first type interface and a second type interface, the first type interface fixedly outputs a first signal, and the second type interface can selectively output a second signal or a third signal.
3. The compatible interface circuit of claim 2 wherein the second type of interface comprises a first interface, the first interface output being either an XON signal or an AVCM signal,
when the first interface is connected with an external first display panel, the output of the first interface is an XON signal which is used for providing a shutdown discharge signal for the external first display panel;
when the first interface is connected with an external second display panel, the output of the first interface is an AVCOM signal for providing an array substrate side reference voltage for the external second display panel.
4. The compatible interface circuit of claim 2, wherein the second type of interface further includes a second interface, and when the second interface is connected to the external first display panel, the second interface outputs a rest signal for selectively outputting a signal for clearing or a signal for resetting a current in the COA circuit to the external first display panel.
5. The compatible interface circuit of claim 2,
the second type of interface further includes a third interface, and when the third interface is connected to an external third display panel, the third interface outputs an LC1 signal for providing a switching signal of a GOA circuit for the external third display panel.
6. The compatible interface circuit of claim 5, wherein the second type of interface further comprises a fourth interface, and when the fourth interface is connected to an external second display panel, the fourth interface outputs an LC2 signal for providing a GOA circuit switching signal to the external second display panel;
the LC1 interface and the LC2 interface switch wheel flows within a preset time.
7. The compatible interface circuit of claim 2, wherein the second type of interface further comprises a fifth interface, and when the fifth interface is connected to an external fourth display panel, the fifth interface outputs a VGH signal for providing a GOA supply voltage to the external fourth display panel.
8. The compatible interface circuit of claim 2, wherein the second type of interface further includes a sixth interface, and when the sixth interface is connected to an external fifth display panel, an output of the sixth interface is an SVCM signal, which is used to provide a reference voltage on a color filter side for the external fifth display panel.
9. The compatible interface circuit of claim 2, wherein the first class of interfaces includes a seventh interface, an eighth interface to a twenty-first interface and a twenty-second interface, the seventh interface output is a VAA signal, the eighth interface to the twenty-first interface output is GM1 to GM14 with sequentially decreasing voltage values, the GM1 to GM14 are reference voltages, and the twenty-second interface output is a VDD1V8 signal;
the voltage value output by the VAA interface is greater than that output by the GM1, and the voltage value output by the GM1 is greater than that output by the VDD1V8 interface.
10. The compatible interface circuit of claim 2 wherein the first type of interface further comprises a twenty-third interface outputting a VSS1 signal, the second type of interface further comprises a twenty-fourth interface outputting a VSS2 signal, the VSS1 signal having a voltage greater than or equal to the voltage of the VSS2 signal.
11. The compatible interface circuit of claim 2, wherein the first type of interface further comprises a twenty-fifth interface, and the output of the twenty-fifth interface is a LOCK signal for providing a control signal fed back by the driver IC.
12. The compatible interface circuit of claim 1, wherein the second interface board further comprises a twenty-sixth interface, and the output of the twenty-sixth interface is an SPI signal for connecting Flash with the SOC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122343933.9U CN217333605U (en) | 2021-09-26 | 2021-09-26 | Display panel compatible interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122343933.9U CN217333605U (en) | 2021-09-26 | 2021-09-26 | Display panel compatible interface circuit |
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| CN217333605U true CN217333605U (en) | 2022-08-30 |
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| CN202122343933.9U Active CN217333605U (en) | 2021-09-26 | 2021-09-26 | Display panel compatible interface circuit |
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| CN (1) | CN217333605U (en) |
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- 2021-09-26 CN CN202122343933.9U patent/CN217333605U/en active Active
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