CN217333156U - Constant power control circuit - Google Patents
Constant power control circuit Download PDFInfo
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- CN217333156U CN217333156U CN202221399929.2U CN202221399929U CN217333156U CN 217333156 U CN217333156 U CN 217333156U CN 202221399929 U CN202221399929 U CN 202221399929U CN 217333156 U CN217333156 U CN 217333156U
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Abstract
The utility model discloses a constant power control circuit, including analog-to-digital converter ADC, central processing chip MCU, digital analog converter DAC and power control ring, analog-to-digital converter ADC's first input and second input are connected respectively and are taked care of voltage and take care of the electric current, and analog-to-digital converter DAC is connected through central processing chip MCU to analog-to-digital converter ADC's output, and digital analog converter DAC is connected with the power control ring, and the power control ring is through duty ratio generating circuit connection drive circuit. The utility model discloses utilize the central processing chip MCU of digital operation to replace analog multiplier and potentiometre, utilize analog-to-digital conversion and digital-to-analog conversion, obtain sampling operation and multiplication through digital computation's mode, to power control ring output feedback signal and reference signal to obtain more accurate constant circuit control signal, digital operation can also eliminate in the circuit zero electricity regulation, gain control production error, accomplish constant power's control.
Description
Technical Field
The utility model relates to the technical field of circuits, more specifically say, relate to a constant power control circuit.
Background
The traditional constant power control circuit adopts an analog multiplier to obtain initial power, but the deviation of the output value of the analog multiplier is large, so that the deviation of the output power and the initial power is large, and the power control deviation exists. Secondly, the signal input into the analog multiplier needs to be subjected to zero-level adjustment, gain adjustment and the like through a potentiometer, but the accuracy of the potentiometer itself is greatly influenced by the environment, so that the final output power control deviation is further increased.
Disclosure of Invention
In order to overcome current constant power circuit because of adopting analog multiplier and potentiometre to lead to the constant power control not enough that the deviation appears, the utility model provides a constant power control circuit abandons analog multiplier and potentiometre, reaches the effect of application digital operation chip through analog-to-digital conversion and digital-to-analog conversion to accomplish the constant control to power.
The utility model discloses technical scheme as follows:
the utility model provides a constant power control circuit, includes analog-to-digital converter ADC, central processing chip MCU, digital-to-analog converter DAC and power control loop, the first input of analog-to-digital converter ADC is connected with the second input and is taked care of voltage and current respectively, analog-to-digital converter ADC's output warp central processing chip MCU connects digital-to-analog converter DAC, digital-to-analog converter DAC with the power control loop is connected, the power control loop is through duty cycle generating circuit connection drive circuit.
In the above constant power control circuit, a conditioning circuit Is disposed at the front end of the analog-to-digital converter ADC, an input end of the conditioning circuit Is connected to the input voltage Vs and the input current Is, respectively, and an output end of the conditioning circuit Is connected to the analog-to-digital converter ADC.
Further, the conditioning circuit comprises a first operational amplifier K1 and a second operational amplifier K2, a non-inverting input terminal of the first operational amplifier K1 Is connected to the input current Is, an inverting input terminal of the first operational amplifier K1 Is connected to ground, and an output terminal of the first operational amplifier K1 Is connected to a second input terminal of the analog-to-digital converter ADC; the non-inverting input terminal of the second operational amplifier K2 is connected to the input voltage Vs, the inverting input terminal of the second operational amplifier K2 is grounded, and the output terminal of the second operational amplifier K2 is connected to the first input terminal of the analog-to-digital converter ADC.
The non-inverting input end of the first operational amplifier K1 is connected to the other end of the second resistor R2 and one end of the third resistor R3, the inverting input end of the first operational amplifier K1 is connected to the other end of the first resistor R1 and one end of the fourth resistor R4, and the output end of the first operational amplifier K1 is connected to the second input end of the analog-to-digital converter ADC and the other end of the fourth resistor R4;
a non-inverting input terminal of the second operational amplifier K2 is connected to the other terminal of the fifth resistor R5 and one terminal of the sixth resistor R6, an inverting input terminal of the second operational amplifier K2 is connected to the other terminal of the seventh resistor R7 and one terminal of the eighth resistor R8, and an output terminal of the second operational amplifier K2 is connected to the first input terminal of the analog-to-digital converter ADC and the other terminal of the eighth resistor R8;
one end of the first resistor R1 is grounded, and the other end of the first resistor R1 is respectively connected with one end of the fourth resistor R4 and the inverting input end of the first operational amplifier K1;
one end of the second resistor R2 Is connected with an input current Is, and the other end of the second resistor R2 Is respectively connected with one end of the third resistor R3 and the non-inverting input end of the first operational amplifier K1;
one end of the third resistor R3 is connected to the other end of the second resistor R2 and the non-inverting input terminal of the first operational amplifier K1, respectively, and the other end of the third resistor R3 is grounded;
one end of the fourth resistor R4 is connected to the other end of the first resistor R1 and the inverting input terminal of the first operational amplifier K1, and the other end of the fourth resistor R4 is connected to the output terminal of the first operational amplifier K1 and the second input terminal of the analog-to-digital converter ADC;
one end of the fifth resistor R5 is connected to the input voltage Vs, and the other end of the fifth resistor R5 is connected to one end of the sixth resistor R6 and the non-inverting input terminal of the second operational amplifier K2;
one end of the sixth resistor R6 is connected to the other end of the fifth resistor R5 and the non-inverting input terminal of the second operational amplifier K2, respectively;
one end of the seventh resistor R7 is grounded, and the other end of the seventh resistor R7 is connected to one end of the eighth resistor R8 and the inverting input terminal of the second operational amplifier K2;
one end of the eighth resistor R8 is connected to the other end of the seventh resistor R7 and the inverting input terminal of the second operational amplifier K2, and the other end of the eighth resistor R8 is connected to the output terminal of the second operational amplifier K2 and the first input terminal of the analog-to-digital converter ADC.
Furthermore, the driving circuit is connected with a power circuit, and the power circuit is also connected with the conditioning circuit.
Still further, the output current of the power circuit is connected to one end of the second resistor R2, and the output voltage of the power circuit is connected to one end of the fifth resistor R5.
In the constant power control circuit, the power control loop includes a third operational amplifier K3 and a fourth operational amplifier K4,
a non-inverting input terminal of the third operational amplifier K3 is connected to the other terminal of a ninth resistor R9, an inverting input terminal of the third operational amplifier K3 is connected to one terminal of a tenth resistor R10, and output terminals of the third operational amplifier K3 are connected to the other terminal of the tenth resistor R10 and one terminal of an eleventh resistor R11, respectively;
a non-inverting input terminal of the fourth operational amplifier K4 is connected to the other terminal of the twelfth resistor R12, an inverting input terminal of the fourth operational amplifier K4 is connected to the other terminal of the eleventh resistor R11 and one terminal of the first capacitor C1, respectively, and an output terminal of the fourth operational amplifier K4 is connected to the other terminal of the first capacitor C1 and an inverting input terminal of the fifth operational amplifier K5, respectively;
one end of the ninth resistor R9 is connected to the first output end of the digital-to-analog converter DAC, and the other end of the ninth resistor R9 is connected to the non-inverting input end of the third operational amplifier K3;
one end of the tenth resistor R10 is connected to the inverting input terminal of the third operational amplifier K3, and the other end of the tenth resistor R10 is connected to the output terminal of the third operational amplifier K3 and one end of the eleventh resistor R11, respectively;
one end of the eleventh resistor R11 is connected to the other end of the tenth resistor R10 and the output end of the third operational amplifier K3, and the other end of the eleventh resistor R11 is connected to the inverting input end of the fourth operational amplifier K4 and one end of the first capacitor C1;
one end of the twelfth resistor R12 is connected to the second output terminal of the digital-to-analog converter DAC, and the other end of the twelfth resistor R12 is connected to the non-inverting input terminal of the fourth operational amplifier K4.
In the constant power control circuit, the duty ratio generation circuit comprises a fifth operational amplifier K5,
the positive phase input end of the fifth operational amplifier K5 is connected with the sawtooth wave generator, the negative phase input end of the fifth operational amplifier K5 is connected with the output end of the fourth operational amplifier K4 and the other end of the first capacitor C1, and the output end of the fifth operational amplifier K5 is connected with the driving circuit.
According to the above scheme the utility model discloses, its beneficial effect lies in, the utility model discloses utilize digital operation's central processing chip MCU to replace analog multiplier and potentiometre, utilize analog-to-digital conversion and digital-to-analog conversion, obtain sampling operation and multiplication operation through digital computation's mode, to power control ring output power repayment signal Perror and reference signal Pvref, thereby obtain more accurate constant circuit control signal, zero electricity regulation in the digital operation can also the cancelling circuit simultaneously, gain control produces the error, thereby accomplish constant power's control.
The acquisition of the power sampling value is changed from an original multiplier to an analog-to-digital converter (ADC) and a central processing chip (MCU) to complete, the power calibration of the potentiometer is also changed to the digital calibration of the MCU, the signal is not only slightly influenced by the environment, but also the power calibration is convenient under the control of high-precision analog-to-digital conversion/digital-to-analog conversion and the MCU, and meanwhile, the precision is also obviously improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic diagram of the circuit structure of the present invention.
Fig. 2 is a schematic diagram of a conditioning circuit.
Fig. 3 is a schematic structural diagram of a power control loop and a duty cycle generating circuit.
Detailed Description
In order to make the technical problem, technical solution and beneficial effects to be solved by the present invention more clearly understood, the following description is made in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.
A constant power control circuit comprises an analog-to-digital converter (ADC), a central processing chip (MCU), a digital-to-analog converter (DAC) and a power control loop, wherein a first input end and a second input end of the ADC are respectively connected with a conditioning voltage and a conditioning current, an output end of the ADC is connected with the DAC through the MCU, the DAC is connected with the power control loop, and the power control loop is connected with a driving circuit through a duty ratio generating circuit.
As shown in fig. 1, 2 and 3, the specific circuit is as follows.
The front end of the analog-to-digital converter ADC Is provided with a conditioning circuit, the input end of the conditioning circuit Is respectively connected with an input voltage Vs and an input current Is, and the output end of the conditioning circuit Is connected with the analog-to-digital converter ADC.
The conditioning circuit comprises a first operational amplifier K1 and a second operational amplifier K2, wherein a non-inverting input terminal of the first operational amplifier K1 is respectively connected with the other end of the second resistor R2 and one end of the third resistor R3, an inverting input terminal of the first operational amplifier K1 is respectively connected with the other end of the first resistor R1 and one end of the fourth resistor R4, and an output terminal of the first operational amplifier K1 is respectively connected with a second input terminal of the analog-to-digital converter ADC and the other end of the fourth resistor R4.
The non-inverting input terminal of the second operational amplifier K2 is connected to the other terminal of the fifth resistor R5 and one terminal of the sixth resistor R6, the inverting input terminal of the second operational amplifier K2 is connected to the other terminal of the seventh resistor R7 and one terminal of the eighth resistor R8, and the output terminal of the second operational amplifier K2 is connected to the first input terminal of the analog-to-digital converter ADC and the other terminal of the eighth resistor R8.
One end of the first resistor R1 is grounded, and the other end of the first resistor R1 is connected to one end of the fourth resistor R4 and the inverting input terminal of the first operational amplifier K1, respectively.
One end of the second resistor R2 Is connected to the input current Is, and the other end of the second resistor R2 Is connected to one end of the third resistor R3 and the non-inverting input terminal of the first operational amplifier K1.
One end of the third resistor R3 is connected to the other end of the second resistor R2 and the non-inverting input terminal of the first operational amplifier K1, and the other end of the third resistor R3 is grounded.
One end of the fourth resistor R4 is connected to the other end of the first resistor R1 and the inverting input terminal of the first operational amplifier K1, and the other end of the fourth resistor R4 is connected to the output terminal of the first operational amplifier K1 and the second input terminal of the analog-to-digital converter ADC.
One end of the fifth resistor R5 is connected to the input voltage Vs, and the other end of the fifth resistor R5 is connected to one end of the sixth resistor R6 and the non-inverting input terminal of the second operational amplifier K2.
One end of the sixth resistor R6 is connected to the other end of the fifth resistor R5 and the non-inverting input terminal of the second operational amplifier K2, respectively.
One end of the seventh resistor R7 is grounded, and the other end of the seventh resistor R7 is connected to one end of the eighth resistor R8 and the inverting input terminal of the second operational amplifier K2, respectively.
One end of the eighth resistor R8 is connected to the other end of the seventh resistor R7 and the inverting input terminal of the second operational amplifier K2, and the other end of the eighth resistor R8 is connected to the output terminal of the second operational amplifier K2 and the first input terminal of the analog-to-digital converter ADC.
The driving circuit is connected with the power circuit, and the power circuit is respectively connected with the conditioning circuit.
The output current of the power circuit is connected with one end of the second resistor R2, and the output voltage of the power circuit is connected with one end of the fifth resistor R5.
The power control loop includes a third operational amplifier K3 and a fourth operational amplifier K4,
the non-inverting input terminal of the third operational amplifier K3 is connected to the other terminal of the ninth resistor R9, the inverting input terminal of the third operational amplifier K3 is connected to one terminal of the tenth resistor R10, and the output terminal of the third operational amplifier K3 is connected to the other terminal of the tenth resistor R10 and one terminal of the eleventh resistor R11, respectively.
The non-inverting input terminal of the fourth operational amplifier K4 is connected to the other terminal of the twelfth resistor R12, the inverting input terminal of the fourth operational amplifier K4 is connected to the other terminal of the eleventh resistor R11 and one terminal of the first capacitor C1, respectively, and the output terminal of the fourth operational amplifier K4 is connected to the other terminal of the first capacitor C1 and the inverting input terminal of the fifth operational amplifier K5, respectively.
One end of the ninth resistor R9 is connected to the first output terminal of the digital-to-analog converter DAC, and the other end of the ninth resistor R9 is connected to the non-inverting input terminal of the third operational amplifier K3.
One end of the tenth resistor R10 is connected to the inverting input terminal of the third operational amplifier K3, and the other end of the tenth resistor R10 is connected to the output terminal of the third operational amplifier K3 and one end of the eleventh resistor R11, respectively.
One end of the eleventh resistor R11 is connected to the other end of the tenth resistor R10 and the output end of the third operational amplifier K3, and the other end of the eleventh resistor R11 is connected to the inverting input end of the fourth operational amplifier K4 and one end of the first capacitor C1.
One end of the twelfth resistor R12 is connected to the second output terminal of the digital-to-analog converter DAC, and the other end of the twelfth resistor R12 is connected to the non-inverting input terminal of the fourth operational amplifier K4.
The duty ratio generating circuit comprises a fifth operational amplifier K5, wherein the non-inverting input end of the fifth operational amplifier K5 is connected with the sawtooth generator, the inverting input end of the fifth operational amplifier K5 is connected with the output end of the fourth operational amplifier K4 and the other end of the first capacitor C1, and the output end of the fifth operational amplifier K5 is connected with the driving circuit.
The utility model discloses in, from input voltage Vs and input current Is that the output of power circuit gathered, the signal of input voltage Vs and input current Is recuperates through the conditioning circuit (difference circuit) that first operational amplifier K1 and second operational amplifier K2 are constituteed. The conditioned voltage and the conditioned current are respectively input to a first input end and a second input end of the analog-to-digital converter ADC.
The central processing chip MCU adopts a high-speed serial port communication port to obtain a value of conditioning voltage and a value of conditioning current from the analog-to-digital converter ADC, and a power sampling value is obtained through multiplication. And after the central processing chip MCU acquires a power sampling value, the power sampling value is sent to the digital-to-analog converter DAC through the high-speed serial port communication port, the digital-to-analog converter DAC outputs an analog signal Ps of the power sampling value from the first output end, and outputs a reference signal Pvref from the second output end.
The analog signal Ps of the power sampling value passes through the third operational amplifier K3 to obtain a power feedback signal Perror, which is used as the feedback of the power control loop. The reference signal Pvref of the power control loop is controlled by the central processing chip MCU via the second output terminal of the digital-to-analog converter DAC. The power feedback signal Perror and the reference signal Pvref are loop-modulated by the fourth operational amplifier K4 to generate a power control error signal.
After the power control error signal is input into the fifth operational amplifier K5, a duty ratio signal capable of controlling the output power is generated by comparing with a sawtooth wave signal output by the sawtooth wave generator, and the duty ratio signal passes through a driving circuit and a power circuit comprising a power device so as to realize the high-precision control of the output power.
In this embodiment, the central processing chip MCU obtains the value of the conditioning voltage and the value of the conditioning current from the analog-to-digital converter ADC, and the two are digitally calibrated through the central processing chip MCU, so as to eliminate the error caused by zero adjustment and gain adjustment on the circuit, and meanwhile, obtain an accurate control signal through multiplication, so that the subsequent power control loop can obtain an accurate power feedback signal Perror.
In addition, the reference signal Pvref of the input power control loop eliminates errors and the like caused by zero point adjustment and gain adjustment on a circuit by a digital calibration mode of the central processing chip MCU, so as to improve the control precision of the output constant power.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. The constant-power control circuit is characterized by comprising an analog-to-digital converter (ADC), a central processing chip (MCU), a digital-to-analog converter (DAC) and a power control loop, wherein a first input end and a second input end of the ADC are respectively connected with conditioning voltage and conditioning current, an output end of the ADC is connected with the DAC through the MCU, the DAC is connected with the power control loop, and the power control loop is connected with a driving circuit through a duty ratio generating circuit.
2. The constant-power control circuit according to claim 1, wherein a conditioning circuit Is disposed at a front end of the analog-to-digital converter ADC, an input end of the conditioning circuit Is connected to the input voltage Vs and the input current Is, respectively, and an output end of the conditioning circuit Is connected to the analog-to-digital converter ADC.
3. The constant power control circuit as claimed in claim 2, wherein the conditioning circuit comprises a first operational amplifier K1 and a second operational amplifier K2,
a non-inverting input terminal of the first operational amplifier K1 Is connected to the input current Is, an inverting input terminal of the first operational amplifier K1 Is connected to the ground, and an output terminal of the first operational amplifier K1 Is connected to a second input terminal of the analog-to-digital converter ADC;
the non-inverting input terminal of the second operational amplifier K2 is connected to the input voltage Vs, the inverting input terminal of the second operational amplifier K2 is connected to the ground, and the output terminal of the second operational amplifier K2 is connected to the first input terminal of the analog-to-digital converter ADC.
4. A constant power control circuit according to claim 2, wherein the driver circuit is connected to a power circuit, and the power circuit is further connected to the conditioning circuit.
5. A constant power control circuit as claimed in claim 1, wherein the power control loop comprises a third operational amplifier K3 and a fourth operational amplifier K4,
a non-inverting input terminal of the third operational amplifier K3 is connected to the first output terminal of the digital-to-analog converter DAC, an inverting input terminal of the third operational amplifier K3 is connected to the output terminal of the third operational amplifier K3 and the inverting input terminal of the fourth operational amplifier K4, and an output terminal of the third operational amplifier K3 is connected to the inverting input terminal of the third operational amplifier K3 and the inverting input terminal of the fourth operational amplifier K4, respectively;
the non-inverting input terminal of the fourth operational amplifier K4 is connected to the second output terminal of the digital-to-analog converter DAC, the inverting input terminal of the fourth operational amplifier K4 is connected to the output terminal of the third operational amplifier K3 and the inverting input terminal of the third operational amplifier K3, and the output terminal of the fourth operational amplifier K4 is connected to the duty ratio generating circuit.
6. The constant power control circuit according to claim 5, wherein the central processing chip MCU sends the analog signal Ps of the power sampling value to the third operational amplifier K3 through the first output terminal of the DAC, and the central processing chip MCU sends the reference signal Pvref to the fourth operational amplifier K4 through the second output terminal of the DAC.
7. The constant power control circuit as claimed in claim 5, wherein the inverting input terminal of the fourth operational amplifier K4 and the output terminal of the fourth operational amplifier K4 are connected to two terminals of the first capacitor C1, respectively.
8. A constant power control circuit as claimed in claim 1, wherein the duty cycle generating circuit comprises a fifth operational amplifier K5,
the positive phase input end of the fifth operational amplifier K5 is connected to a sawtooth wave generator, the positive phase input end of the fifth operational amplifier K5 is connected to the sawtooth wave generator, the negative phase input end of the fifth operational amplifier K5 is connected to the output end of the fourth operational amplifier K4, and the output end of the fifth operational amplifier K5 is connected to the driving circuit.
9. The constant power control circuit as claimed in claim 8, wherein the fourth operational amplifier K4 sends a power feedback signal Perror to the inverting input of the fifth operational amplifier K5, and the sawtooth generator sends a sawtooth signal to the non-inverting input of the fifth operational amplifier K5.
10. The constant-power control circuit as claimed in claim 1, wherein the central processing chip MCU is connected to the digital-to-analog converter DAC and the analog-to-digital converter ADC respectively via high-speed serial communication ports.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221399929.2U CN217333156U (en) | 2022-06-07 | 2022-06-07 | Constant power control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221399929.2U CN217333156U (en) | 2022-06-07 | 2022-06-07 | Constant power control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217333156U true CN217333156U (en) | 2022-08-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221399929.2U Active CN217333156U (en) | 2022-06-07 | 2022-06-07 | Constant power control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217333156U (en) |
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2022
- 2022-06-07 CN CN202221399929.2U patent/CN217333156U/en active Active
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