CN217307648U

CN217307648U - Variable gain amplifier circuit and receiver

Info

Publication number: CN217307648U
Application number: CN202220156973.4U
Authority: CN
Inventors: 钱晓辉; 李鑫尧
Original assignee: Star Core Suzhou Semiconductor Technology Co Ltd
Current assignee: Star Core Suzhou Semiconductor Technology Co Ltd
Priority date: 2022-01-20
Filing date: 2022-01-20
Publication date: 2022-08-26
Anticipated expiration: 2032-01-20

Abstract

The utility model provides a variable gain amplifier circuit and receiver, variable gain amplifier circuit is including enlargiing main circuit, bias circuit and regulating circuit. The bias circuit is arranged on the input side of the main amplification circuit. The adjusting circuit is electrically connected to the signal input end of the main amplifying circuit and is an input signal adjusting branch with variable impedance; based on the change of the input signal amplitude, the impedance of the adjusting circuit is changed to change the input signal component flowing through the adjusting circuit, and the signal amplitude input to the amplifying main circuit is adjusted to realize gain adjustment.

Description

Variable gain amplifier circuit and receiver

Technical Field

The utility model relates to a wireless communication field, and in particular to variable gain amplifier circuit and receiver.

Background

With the development of communication technology, application technical schemes of high frequency, broadband and high dynamic range become more and more important, and broadband communication modes such as WIFI6, 5G communication and UWB have entered the lives of people. However, as communication systems are diversified, the influence between the systems is increased, the requirement on communication circuits is increased, and the conventional gain adjustment technology has become unable to meet the requirement of the communication systems.

The traditional gain adjustment scheme has a large influence on the module and the system, and other performance parameters of the module and the system are synchronously changed while the gain is adjusted. The conventional scheme also has adverse effects such as increase in noise of the system and decrease in output linearity while reducing the gain. The communication system is required to meet the performance requirements of noise, out-of-band rejection, linearity and the like of the system while obtaining a high dynamic range. It is desirable to achieve good noise and out-of-band rejection without affecting the performance of the module in the highest performance mode as much as possible when adjusting the gain. The contradiction is difficult to be considered in the traditional gain adjustment technology, thereby causing great influence on the performance of the system; especially in the presence of interfering signals, the noise of the system is greatly degraded due to the very large gain reduction (usually negative gain in some cases).

SUMMERY OF THE UTILITY MODEL

The utility model discloses an overcome at least one not enough of prior art, provide a variable gain amplifier circuit that can compromise the system performance when the gain adjustment.

In order to achieve the above object, the present invention provides a variable gain amplifier circuit, which includes an amplifier main circuit, a bias circuit and an adjusting circuit. The bias circuit is arranged on the input side of the main amplification circuit. The adjusting circuit is electrically connected to the signal input end of the main amplifying circuit and is an input signal adjusting branch with variable impedance; based on the change of the input signal amplitude, the impedance of the adjusting circuit is changed to change the input signal component flowing through the adjusting circuit, and the signal amplitude loaded to the amplifying main circuit is adjusted.

According to the utility model discloses an embodiment, biasing circuit provides direct current bias current for enlargiing the main circuit, and regulating circuit includes variable impedance component and electric capacity, and variable impedance component's one end is connected in signal input part, and biasing circuit's output and the one end of electric capacity are connected respectively to its other end, and the other end short circuit of electric capacity is on the end.

According to an embodiment of the present invention, an isolation element is connected in series between the output of the bias circuit and one end of the variable impedance element, and the isolation element isolates the dc bias circuit and the ac regulation circuit.

According to an embodiment of the present invention, the variable impedance element includes a variable resistor array composed of a plurality of resistors and a plurality of switches, and the plurality of switches connect one or more resistors to the adjusting circuit to change the impedance of the adjusting circuit.

According to the utility model discloses an embodiment, among the variable resistance array, each resistance forms an impedance adjustment branch road after establishing ties with the switch that corresponds, and a plurality of impedance branch roads are parallelly connected in order to form the variable resistance array.

According to the utility model discloses an embodiment, among the variable resistance array, a plurality of resistance series connection, a plurality of switches connect in parallel in the resistance of a plurality of series connections step by step, surely go out regulating circuit with one or more resistance.

According to the utility model discloses an embodiment, variable gain amplifier circuit is still including connecting in the load circuit of amplifying the main circuit output, and load circuit is RLC adjustment array.

According to the utility model discloses an embodiment, enlarge the main circuit and be cascode amplifier circuit, it includes common source pipe and common grid pipe, the grid of signal input part access common source pipe, signal output part electric connection in the drain electrode of common grid pipe.

On the other hand, the utility model also provides a receiver, it includes above-mentioned variable gain amplifier circuit.

To sum up, the utility model provides an among variable gain amplifier circuit and the receiver, biasing circuit provides suitable operating point in order to ensure that the amplifier main circuit can be in normal amplification state and have excellent noise performance for the amplifier main circuit. When the amplitude of the input signal is larger, the impedance of the adjusting circuit is adjusted to enable the input signal to be partially shunted through the adjusting circuit, so that the signal loaded to the input end of the main amplifying circuit is effectively reduced, the amplitude of the output signal is well controlled, and the adjustment of the gain is realized. Meanwhile, the reduction of the signal input to the main amplifying circuit also effectively prevents the main amplifying circuit from entering a saturation state, the main amplifying circuit can still be in a good working state, and better linearity can still be obtained under the condition of large signal. That is, the utility model provides a variable gain amplifier circuit still can keep high linearity and noise performance when realizing gain adjustment, fine solution in the current gain adjustment technique between performance such as gain adjustment and noise, linearity.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic structural diagram of an amplifying module with adjustable gain in a conventional communication system.

Fig. 2 is a schematic block diagram of a variable gain amplifier circuit according to an embodiment of the present invention.

Fig. 3 is a schematic circuit diagram of a variable gain amplifier circuit according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of the variable impedance device of fig. 3.

Fig. 5 is a schematic diagram of a variable impedance device according to another embodiment of the present invention.

Detailed Description

Fig. 1 is a schematic structural diagram of an amplifying module with adjustable gain in a conventional communication system. The output end of the amplifier in fig. 1 is connected with a load RLC array, and the gain of the gain adjusting module is changed by adjusting the output impedance of the load RLC array; when the input signal is large, the communication system suggests a need to lower the impedance of the load RLC array, thereby lowering the gain of the module. Because the gain adjustment method directly acts on the load RLC array at the output end of the amplifier, the gain adjustment scheme can obtain better noise performance; however, at this time, the input side of the amplifying module still needs to bear a large input signal amplitude, so that the improvement of the input linearity is very limited. Further, the reduction of the load impedance also brings about a problem of deterioration of the output linearity. Some bias circuits are also available in the market to adjust the gain, that is, the gain is adjusted by changing the bias condition. In the adjusting scheme, when the bias current is larger, the amplifying module has high gain, excellent gain and noise performance can be obtained, but the linearity performance is poor. When the signal is strong, the communication system needs to perform gain control, which obtains good linearity performance by reducing the bias current, but brings a problem of reduced noise performance. That is, in the existing gain adjustment scheme, the gain adjustment always brings the influence of the system performance, and it is difficult to realize the compatibility between the two.

In view of the above, the present embodiment provides a variable gain amplifier circuit, which includes an amplifier main circuit 10, a bias circuit 20, and an adjusting circuit 30. The bias circuit 20 is provided on the input side of the amplifier main circuit 10. The adjusting circuit 30 is electrically connected to the signal input terminal of the main amplifying circuit 10, and the adjusting circuit 30 is an input signal adjusting branch with variable impedance; based on the change of the amplitude of the input signal, the impedance of the regulating circuit 30 is changed to change the component of the input signal flowing through the regulating circuit 30, and the amplitude of the signal input to the main amplification circuit 10 is adjusted to change the amplitude of the output signal, thereby achieving the adjustment of the gain of the main amplification circuit.

In the variable gain amplifier circuit of the present embodiment, the bias circuit 20 provides the main amplifier circuit 10 with a suitable operating point to be in an amplified state and to have excellent noise performance. When the input signal is large, a part of the input signal is shunted to the adjusting circuit 30 by decreasing the impedance of the adjusting circuit 30, so that the signal loaded to the amplifier tube of the main amplifier circuit 10 is decreased. The amplifier tube can not enter a saturation state due to large signal input, and can still be in a good amplification working state, so that the amplifier tube has good input linearity, the adjustment of the impedance can not cause any influence on other characteristics of the main amplifier circuit, such as noise, out-of-band rejection, output linearity and the like, and the consideration of gain adjustment and excellent system performance is realized.

In the present embodiment, the bias circuit 20 provides a bias current for the main amplifier circuit 10, and includes a current source I1 and a bias transistor M3. The current source I1 is connected to the drain of the bias transistor M3, the source of the bias transistor M3 is grounded, and the gate thereof is connected to the drain and then serves as the output of the bias circuit 20 to provide the mirror current for the amplifier main circuit 10. The adjusting circuit 30 includes a variable impedance element 31 and a capacitor C1, one end of the variable impedance element 31 is connected to the signal Input terminal, the other end thereof is connected to the output of the bias circuit 20 and one end of the capacitor C1, respectively, and the other end of the capacitor C1 is short-circuited to the bottom. The main amplifier circuit 10 is a cascode amplifier circuit, and includes a common source transistor M1 and a common gate transistor M2, the signal Input terminal is connected to the gate of the common source transistor M1, and the signal Output terminal is electrically connected to the drain of the common gate transistor M2. However, the present invention does not limit the structure of the amplifying main circuit.

In this embodiment, the variable impedance element 31 is a variable resistor array including a plurality of resistors and a plurality of switches, and the plurality of switches connect one or more resistors to the adjusting circuit to change the impedance of the variable resistor array. However, the present invention is not limited to the specific form of the variable impedance element. Other impedance adjusting components that can change the impedance of the adjusting circuit to adjust the split flow of the input signal are within the scope of the present invention, such as a digital potentiometer that can be programmed to implement the impedance change.

Specifically, as shown in fig. 3, a plurality of resistors R2_1, R2_2 … R2_ n in the variable impedance element 31 are connected in parallel, and each resistor R2_ n is connected in series with a corresponding switch SWn to form an impedance adjusting branch. The resistors R2_1 and R2_2 … R2_ n are reasonably valued according to the range of gain gears required to be obtained, and the larger the resistor is, the larger the gain obtained after the adjustment branch is connected is. In this embodiment, n is 3 as an example. However, the present invention does not make any modernization to this. In other embodiments, the number of resistors and switches may be selected according to the required gain level requirement, and the number of resistors and switches may be two or more than four.

The working principle is as follows: preset R2_1> R2_2> R2_3, when the amplification main circuit 10 needs to obtain the highest gain, the switch SW1 is closed, and the switches SW2 and SW3 are opened. Based on the high resistance value of R2_1, the input signal does not flow through the capacitor C1 to ground through the resistor R2_ 1; i.e. when the regulating circuit 30 is not active. When the amplitude of the input signal gradually increases, the main amplifier circuit 10 needs to reduce its gain. At this time, the switch SW2 or/and SW3 is/are turned on to reduce the impedance of the regulating circuit 30, so that the signal part Input from the signal Input terminal Input is short-circuited to the ground through the variable resistor array and the capacitor C1, and thus the signal applied to the gate of the common-source transistor M1, which plays a role of main amplification, is reduced, the signal magnitude of the Output terminal Output will change along with the signal magnitude applied to the gate of the common-source transistor M1, and the purpose of variable gain is achieved. In the adjustment process, the adjustment of the gain is based on the shunting of the input signal, and the parameters of the bias circuit 20 and the output load of the main amplification circuit 10 are not changed. Therefore, under different gain modes, the variable gain amplifying circuit can still be in the best working state, thereby realizing that the noise, the gain and the linearity of the variable gain amplifying circuit are in the best performance no matter the gain.

The operation principle of the power saving circuit 30 is explained by taking the gain of the main amplifier circuit 10 as an example. As the amplitude of the signal at the Input terminal Input decreases, the system will open the switches SW2 and/or SW3 to increase the impedance of the variable resistor array to increase the gain. In the present embodiment, the control of the switches SW1, SW2, SW3 is implemented by the communication system based on the configuration of the high and low levels of the register given by the amplitude of the input signal. However, the present invention is not limited to this.

In this embodiment, a plurality of resistors in the variable impedance element 31 are connected in parallel. However, the present invention is not limited to this. In other embodiments, as shown in fig. 5, in the variable resistor array, a plurality of resistors may be connected in series, and in this case, a plurality of switches may be connected in cascade to the plurality of resistors in series, so as to switch one or more resistors out of the regulating circuit. For example, when the switch SW3 'is turned off, only the resistor R _24' is connected in the variable resistor array 31; the adjustment circuit 30 will now be in the lowest gain adjustment state. When the switches SW3', SW2', and SW1' are all in the open state, the resistors R _24', R _23', R _22', and R _22' are all connected to the variable resistor array, and the adjusting circuit 30 is in the highest gain adjusting state.

As shown in fig. 3, in the present embodiment, an isolation element 50 is connected in series between the output of the bias circuit 20 and one end of the variable impedance element 31, and the isolation element 50 isolates the dc bias circuit 20 and the ac regulator circuit 30 from each other, so as to avoid the ac signal from affecting the bias circuit. Preferably, the isolation element is a resistor R1. Further, the capacitor C1 in the adjusting circuit 30 is well arranged to block the dc bias current, when the adjusting circuit 30 reduces the impedance to shunt the input signal, the dc bias current does not go through the capacitor C1 to the ground, and it can still be loaded to the gate of the common-source transistor M1 through the resistor R1 and the variable impedance element 31, so as to provide a stable and proper operating point for the common-source transistor M1.

In this embodiment, the variable gain amplifier circuit further includes a load circuit 40 connected to the output terminal of the main amplifier circuit 10. In the present embodiment, the load circuit 40 is an RLC trim array connected between the drain of the common-gate transistor M2 and the power supply. In the variable gain amplifier circuit provided in this embodiment, the setting of the adjusting circuit 30 enables the setting of the bias circuit 20 located at the input side to still provide a suitable operating point for the main amplifier circuit 10 when the variable gain amplifier circuit performs gain adjustment, so as to ensure that the main amplifier circuit 10 has excellent noise, out-of-band rejection and linearity performance; the load circuit 40 at the output end can maintain high output impedance to make the main amplifier circuit have excellent output linearity, thereby achieving the performance of the main amplifier circuit 10 at different gains.

Correspondingly, the present embodiment further provides a transceiver including the variable gain amplifier circuit provided in the present embodiment.

Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A variable gain amplification circuit, comprising:

the amplifying main circuit;

the bias circuit is arranged on the input side of the amplification main circuit;

the adjusting circuit is electrically connected to the signal input end of the main amplifying circuit and is an input signal adjusting branch with variable impedance; based on the change of the input signal amplitude, the impedance of the adjusting circuit is changed to change the input signal component flowing through the adjusting circuit, and the signal amplitude loaded to the amplifying main circuit is adjusted.

2. The variable gain amplifier circuit as claimed in claim 1, wherein the bias circuit provides a dc bias current for the main amplifier circuit, the adjusting circuit comprises a variable impedance element and a capacitor, one end of the variable impedance element is connected to the signal input terminal, the other end of the variable impedance element is connected to the output of the bias circuit and one end of the capacitor, respectively, and the other end of the capacitor is short-circuited to ground.

3. The variable gain amplifier circuit according to claim 2, wherein an isolation element is connected in series between an output of the bias circuit and one end of the variable impedance element, and the isolation element isolates the dc bias circuit from the ac regulator circuit.

4. The variable gain amplifier circuit of claim 2 wherein the variable impedance element comprises a variable resistor array comprising a plurality of resistors and a plurality of switches, the plurality of switches connecting one or more of the resistors to the regulating circuit to vary the impedance of the regulating circuit.

5. The variable gain amplifier circuit as claimed in claim 4, wherein each resistor in the variable resistor array is connected in series with a corresponding switch to form an impedance adjusting branch, and a plurality of impedance branches are connected in parallel to form the variable resistor array.

6. The variable gain amplifier circuit of claim 4, wherein the variable resistor array comprises a plurality of resistors connected in series, and a plurality of switches connected in series with the plurality of resistors in series to switch one or more resistors out of the tuning circuit.

7. The variable gain amplifier circuit of claim 1 further comprising a load circuit coupled to the output of the main amplifier circuit, the load circuit being an RLC trim array.

8. The variable gain amplifier circuit according to claim 1, wherein the main amplifier circuit is a cascode amplifier circuit, which includes a common source transistor and a common gate transistor, the signal input terminal is connected to the gate of the common source transistor, and the signal output terminal is electrically connected to the drain of the common gate transistor.

9. A receiver comprising the variable gain amplification circuit according to any one of claims 1 to 8.