CN217214705U

CN217214705U - MOSFET packaging structure with improved packaging thermal resistance and die head

Info

Publication number: CN217214705U
Application number: CN202221101056.2U
Authority: CN
Inventors: 徐银森; 林毛毛; 廖波
Original assignee: Sichuan Suining Lipuxin Microelectronic Co ltd
Current assignee: Sichuan Suining Lipuxin Microelectronic Co ltd
Priority date: 2022-05-09
Filing date: 2022-05-09
Publication date: 2022-08-16
Anticipated expiration: 2032-05-09

Abstract

The application discloses improve MOSFET packaging structure and moulding-die head of encapsulation thermal resistance belongs to semiconductor technical field, and packaging structure includes lead frame, casing, transistor, adhesive linkage, first pin, second pin, first lead group and second lead group. The casing lid connects and forms the installation cavity in the lead frame top, and adhesive linkage and transistor set gradually along the direction of lead frame towards the casing, and a plurality of first pins and a plurality of second pin set up respectively in the both sides of casing, and the transistor forms through first lead group and second lead group and first pin and second pin respectively and is connected to dispel the heat through the pin. The utility model discloses a transistor packaging structure can be fine through setting up of first pin and second pin dispels the heat fast to the transistor to guarantee that the transistor is all the time worked in certain temperature range, and then guarantee the work efficiency of transistor, the transistor can also effectual extension its life in lower temperature work.

Description

MOSFET packaging structure with improved packaging thermal resistance and die head

Technical Field

The utility model relates to the field of semiconductor technology, particularly, relate to a MOSFET packaging structure and die head of thermal resistance are packaged in improvement.

Background

Currently, most high voltage switching circuits are designed using silicon-based transistors such as SiMOSFETs or IGBTs.

The transistor can generate a large amount of heat during operation, and the existing packaging structure can not well dissipate the heat of the transistor, so that the service life of the transistor is short, and the efficiency begins to be reduced after the transistor works for a period of time.

SUMMERY OF THE UTILITY MODEL

The utility model discloses a MOSFET packaging structure and moulding-die head of thermal resistance are packaged in improvement to improve foretell problem.

The utility model provides a technical scheme that above-mentioned technical problem adopted is:

based on foretell purpose, the utility model discloses an improve MOSFET packaging structure who encapsulates thermal resistance, include:

a lead frame;

a housing covering the lead frame, and forming a mounting cavity between the housing and the lead frame;

a transistor mounted to the leadframe and located within the mounting cavity;

an adhesive layer between the transistor and the lead frame;

the first pin extends outwards from the mounting cavity, and the second pin extends outwards from the mounting cavity; and

the transistor is connected with the first pin and the lead frame through the first lead group, and the second pin is connected with the transistor and the lead frame through the second lead group.

Optionally: the first lead group comprises a first lead and a second lead, two ends of the first lead are respectively connected with the transistor and the first pin, and two ends of the second lead are respectively connected with the transistor and the lead frame; the second lead group comprises a third lead and a fourth lead, two ends of the third lead are respectively connected with the transistor and the second pin, and two ends of the fourth lead are respectively connected with the second pin and the lead frame.

Optionally: the lead frame is provided with a positioning block, the shell is provided with a positioning groove, and the positioning groove is in clamping fit with the positioning block.

Optionally: the shell is provided with a through hole, the through hole is formed in the side wall of the shell and communicated with the installation cavity, the positioning groove is located in the top wall of the shell and communicated with the installation cavity, and the first pin and the second pin are installed in the through hole in a relative mode respectively.

Optionally: the through holes are arranged in a plurality and are respectively arranged on two opposite side walls of the shell, and the through holes are arranged in one-to-one correspondence with the first pins and the second pins;

the locating piece includes joint and a plurality of connector, the joint with the constant head tank joint cooperation, it is a plurality of the connector is followed the length direction interval of joint sets up, the both ends of connector respectively with the lead frame with joint connects, just the connector is located the lateral wall of casing with between the transistor.

Optionally: the first pins are arranged in a plurality of numbers, and the first pins are positioned on the same side of the lead frame; the second pins are arranged in a plurality of numbers, the second pins are positioned on the same side of the lead frame, and the second pins and the first pins are arranged oppositely;

the locating piece sets up to two, two the locating piece is located respectively the both sides of lead frame, one of them a plurality of in the locating piece the connector is followed with a plurality of first pin the length direction of joint is crisscross to be set up, another a plurality of in the locating piece the connector is followed with a plurality of the second pin the length direction of joint is crisscross to be set up.

Optionally: the first pins and the second pins comprise connecting parts, guiding parts and heat dissipation parts, the guiding parts are located between the connecting parts and the heat dissipation parts, the connecting parts and the heat dissipation parts are arranged in parallel, and the guiding parts and the connecting parts are arranged in an inclined mode, so that the heat dissipation parts are located below the shell.

Optionally: the area of the adhesive layer is smaller than or equal to the bottom area of the transistor.

In view of the above, the present embodiment also discloses a die head including a drainage groove, which is used for producing the MOSFET package structure described above.

Optionally: the external dimension of the die head is 6 x 4.5mm, and the cavity dimension of the die head is 0.01 mm.

Compared with the prior art, the utility model discloses the beneficial effect who realizes is:

the utility model discloses a MOSFET packaging structure can be fine dispel the heat fast to the transistor through the setting of first pin and second pin to guarantee that the transistor is all the time worked in certain temperature range, and then guarantee the work efficiency of transistor, the transistor can also effectual extension its life in lower temperature work.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic diagram of a MOSFET package structure according to an embodiment of the present invention;

fig. 2 shows a cross-sectional view of a MOSFET package structure disclosed in another embodiment of the invention;

fig. 3 shows a cross-sectional view of a MOSFET package structure disclosed in an embodiment of the invention at a first viewing angle;

fig. 4 shows a cross-sectional view of a MOSFET package structure disclosed in an embodiment of the invention at a second viewing angle;

fig. 5 shows a schematic diagram of a lead frame disclosed in an embodiment of the present invention;

fig. 6 shows a schematic view of a housing according to an embodiment of the present invention.

In the figure:

110-lead frame, 111-positioning block, 1111-card connector, 1112-connector, 120-shell, 121-positioning groove, 122-through hole, 130-transistor, 140-adhesive layer, 150-first pin, 160-second pin, 170-installation cavity, 180-first lead group, 181-first lead, 182-second lead, 190-second lead group, 191-third lead and 192-fourth lead.

Detailed Description

The present invention will be described in further detail below with reference to specific embodiments and with reference to the accompanying drawings.

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, as disclosed in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures.

In the description of the embodiments of the present application, it should be noted that the indication of orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship which is usually placed when the product of the application is used, or the orientation or positional relationship which is usually understood by those skilled in the art, or the orientation or positional relationship which is usually placed when the product of the application is used, and is only for the convenience of describing the application and simplifying the description, but does not indicate or imply that the indicated device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the application. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

In the description of the embodiments of the present application, it should also be noted that, unless otherwise explicitly stated or limited, the terms "disposed," "mounted," and "connected" are to be construed broadly, and may for example be fixedly connected, detachably connected, or integrally connected; may be directly connected or indirectly connected through an intermediate. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

Example (b):

referring to fig. 1-2, an embodiment of the invention discloses a MOSFET package structure with improved thermal resistance, which includes a lead frame 110, a housing 120, a transistor 130, an adhesive layer 140, a first lead 150, a second lead 160, a first lead group 180, and a second lead group 190. The housing 120 is covered on the lead frame 110 to form a mounting cavity 170, the adhesive layer 140 is located between the transistor 130 and the lead frame 110, the at least one first pin 150 and the at least one second pin 160 are respectively disposed on two sides of the housing 120, and the transistor 130 is connected to the first pin 150 and the second pin 160 through the first lead group 180 and the second lead group 190, respectively, so as to dissipate heat through the pins.

The MOSFET is a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), which is a Field-Effect Transistor (Field-Effect Transistor) that can be widely used in analog circuits and digital circuits. MOSFETs are classified into "N-type" and "P-type" types according to their "channel" (working carrier) polarities, and are also commonly referred to as NMOSFETs and PMOSFETs, and other types include NMOS and PMOS for short.

It will be appreciated that the housing 120 serves to protect the inner wafers (transistors) and, as described above, covers the lead frame 110, which may be wrapped around the lead frame 110, as shown in fig. 1. It can be encapsulated by plastic, such as epoxy resin, or ceramic.

Meanwhile, in practice, the connection method of the leads may be other forms, and is not limited to the manner of using the first lead group and the second lead group in fig. 1 to 3. The specific connection method is actually related to the design requirement.

The MOSFET package structure disclosed in this embodiment can well dissipate heat quickly to the transistor 130 through the arrangement of the first pin 150 and the second pin 160, thereby ensuring that the transistor 130 works within a certain temperature range all the time, further ensuring the working efficiency of the transistor 130, and effectively prolonging the service life of the transistor 130 when the transistor works within a lower temperature range. It should be noted that the present application is not limited to the first lead and the second lead, and actually, according to the requirement, a third lead, even a fourth lead or more leads may be included, which is substantially the same as the first lead and the second lead, but the connection manner of each lead with the transistor electrode, the frame, etc. may be different, and the connection manner is designed mainly according to the requirement. In addition, the present application specifically describes a package structure of a MOSFET, that is, the transistor 130 is a MOS, but in practice, the present application is not necessarily a MOSFET, and may be any transistor package structure. That is, the present application may be only a transistor package structure and a die head for improving the package thermal resistance, that is, the transistor 130 may be any transistor in practice, and is not limited to a MOSFET.

The cross-sectional area of the lead frame 110 is smaller than that of the housing 120, so that the lead frame 110 and the housing 120 can be better matched, on one hand, the transistor 130 is conveniently fixed and protected, and on the other hand, heat dissipation is more facilitated. As shown in fig. 2 to 4, the housing 120 may be wrapped around only the peripheral wall of the lead frame 110, and in other embodiments, the housing 120 may wrap the bottom of the lead frame 110, for example, as shown in fig. 1, the plastic-molded housing 120 wraps the lead frame 110.

In one embodiment, referring to fig. 6, the housing 120 is provided with a through hole 122 and a positioning groove 121. After the housing 120 is connected to the lead frame 110, the housing 120 and the lead frame 110 cooperate to form a mounting cavity 170. The positioning groove 121 is disposed at the top of the casing 120, and the positioning groove 121 is communicated with the installation cavity 170. The through hole 122 is disposed on a sidewall of the housing 120, and the through hole 122 is communicated with the mounting cavity 170.

Referring to fig. 3 to 5, a positioning block 111 for being engaged with a positioning groove 121 is disposed on the lead frame 110, the positioning block 111 is disposed toward the housing 120, and the positioning block 111 is engaged with the positioning groove 121 on the housing 120. Specifically, referring to fig. 4 to 5, the positioning block 111 includes a clamping head 1111 and a plurality of connectors 1112, two ends of the connectors 1112 are respectively connected to the clamping head 1111 and the lead frame 110, and the connectors 1112 are spaced along a length direction of the clamping head 1111. The positioning block 111 is located in the mounting cavity 170, and the positioning block 111 is located between the sidewall of the housing 120 and the transistor 130. When the connection heads 1112 and the through holes 122 of the housing 120 are disposed, the connection heads 1112 and the through holes 122 are disposed in a staggered manner along the length direction of the snap joint 1111.

Each of the first and

second pins

150 and 160 includes a connection portion, a guide portion, and a heat dissipation portion. The connecting portion is installed in the through hole 122, and a portion of the connecting portion extends into the installation cavity 170, and another portion of the connecting portion extends out of the housing 120. The guide portion is disposed between the connecting portion and the heat dissipating portion, and the guide portion and the connecting portion are disposed in an inclined manner (at a certain angle) so that the heat dissipating portion is located below the housing 120. The heat dissipation part is arranged in parallel with the connecting part, and the length of the heat dissipation part is larger than that of the connecting part, so that the heat dissipation efficiency is improved.

Referring to fig. 5 and 6, in the present embodiment, the first leads 150 are disposed in a plurality, and the plurality of first leads are located on the same side of the lead frame 110; the second leads 160 are disposed in plural, the second leads 160 are located on the same side of the lead frame 110, and the second leads 160 are disposed opposite to the first leads 150. The through holes 122 are disposed in plural, the through holes 122 are disposed on two opposite sidewalls of the housing 120, respectively, and the through holes 122 are disposed in one-to-one correspondence with the first pins 150 and the second pins 160. It should be noted that, here, the first lead 150 and the second lead 160 are provided in plural, and the plural leads are defined as the first lead or the second lead, and do not necessarily refer to the connection manner of the plural leads with the frame and the transistor, and as described above, the connection manner of the first lead or the second lead may be other connection manners in practice. More importantly, the plurality of pins located on the same side are first pins, and the plurality of pins located on the other side are second pins. Here, the plurality of pins may also be considered as the aforementioned third, fourth, or even more pins. I.e. the application is in fact not limited to the two pins described above, but may be a plurality of pins.

The number of the positioning blocks 111 is two, and the two positioning blocks 111 are respectively located at two sides of the lead frame 110. The positioning block 111 includes a snap-fit joint 1111 and a plurality of connectors 1112, and the snap-fit joint 1111 is snap-fit with the positioning groove 121 on the housing 120. The plurality of connectors 1112 are spaced along the length direction of the latch 1111, two ends of the connectors 1112 are connected to the lead frame 110 and the latch 1111, respectively, and the connectors 1112 are located between the side wall of the housing 120 and the transistor 130. The connectors 1112 and the first pins 150 in one of the positioning blocks 111 are staggered along the length direction of the card joint 1111, and the connectors 1112 and the second pins 160 in the other positioning block 111 are staggered along the length direction of the card joint 1111.

The connection portions of the first pin 150 and the second pin 160 extend into the mounting cavity 170 and pass through the region where the connector 1112 is located, and the connection portions and the connector 1112 are staggered along the length direction of the snap joint 1111. In order to ensure the connection stability of the housing 120 and the lead frame 110 and to improve the heat dissipation efficiency, the number of the connectors 1112 is greater than the sum of the number of the first pins 150 and the number of the second pins 160, and only one connection portion is provided between two adjacent connectors 1112.

The adhesive layer 140 and the transistor 130 are sequentially disposed along the lead frame 110 toward the housing 120, that is, the adhesive layer 140 is located on the lead frame 110, and the transistor 130 is fixed on the lead frame 110 by the adhesive layer 140. The area of the adhesive layer 140 is smaller than or equal to the bottom area of the transistor 130. The adhesive layer 140 is mainly used to fix the transistor 130 on the lead frame 110, and the adhesive layer 140 may be conductive, such as solder, or the like, and the adhesive layer 140 may also be non-conductive, such as epoxy glue or the like.

The transistor 130 is connected to the first and

second leads

150 and 160 through the first and second

lead groups

180 and 190, respectively, to dissipate heat. Specifically, the first lead group 180 includes a first lead 181 and a second lead 182, both ends of the first lead 181 are connected to the transistor 130 and the first pin 150, respectively, and both ends of the second lead 182 are connected to the transistor 130 and the lead frame 110, respectively; the ends of the first lead 181 and the second lead 182 connected to the transistor 130 may be the same electrode connected to the transistor 130, or may be different electrodes; for example, in the case of different electrodes, one end of the first lead 181 is connected to the first lead 150, the other end is connected to the first electrode of the transistor, one end of the second lead 182 is connected to the lead frame 110, and the other end is connected to the second electrode of the transistor. The second lead group 190 includes a third lead 191 and a fourth lead 192, both ends of the third lead 191 are connected to the transistor 130 and the second pin 160, respectively, and both ends of the fourth lead 192 are connected to the second pin 160 and the lead frame 110, respectively.

The embodiment of the utility model provides a still disclose a moulding-die head for producing foretell MOSFET packaging structure, this moulding-die is overhead to be provided with the drainage groove. And the external dimension of the die head is 6 x 4.5mm, and the cavity dimension of the die head is 0.01 mm.

The MOSFET package structure produced by the die disclosed in this embodiment reduces the cavity size of the die, so that solder (such as the solder on the adhesive layer 140 or other parts of the package structure) can be pressed thin and large, thereby facilitating heat dissipation. Referring to fig. 1 to 6, the MOSFET package structure produced by the die head disclosed in this embodiment can not only rapidly dissipate heat of the transistor 130 through the first pin 150 and the second pin 160, but also optimize the heat dissipation performance of the transistor and improve the package thermal resistance of the transistor through the thin and large adhesive layer 140, thereby ensuring that the transistor 130 always works within a certain temperature range, further ensuring the working efficiency of the transistor 130, and effectively prolonging the service life of the transistor 130 when the transistor 130 works within a lower temperature range.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A MOSFET package structure with improved thermal resistance, comprising:

a lead frame;

a transistor mounted to the leadframe and located within the mounting cavity;

an adhesive layer between the transistor and the lead frame;

2. The MOSFET package according to claim 1, wherein the first lead group comprises a first lead and a second lead, both ends of the first lead are connected to the transistor and the first pin, respectively, and both ends of the second lead are connected to the transistor and the lead frame, respectively; the second lead group comprises a third lead and a fourth lead, two ends of the third lead are respectively connected with the transistor and the second pin, and two ends of the fourth lead are respectively connected with the second pin and the lead frame.

3. The MOSFET package structure of any of claims 1-2, wherein a positioning block is disposed on the lead frame, and a positioning groove is disposed on the case, and the positioning groove is snap-fitted to the positioning block.

4. The MOSFET package structure of claim 3, wherein the housing is provided with a through hole, the through hole is disposed on a side wall of the housing and communicates with the mounting cavity, the positioning groove is located on a top wall of the housing and communicates with the mounting cavity, and the first pin and the second pin are respectively mounted in the through hole.

5. The MOSFET package structure of claim 4, wherein the plurality of through holes are disposed on two opposite sidewalls of the housing, respectively, and the plurality of through holes are disposed in one-to-one correspondence with the plurality of first leads and the plurality of second leads;

6. The MOSFET package structure of claim 5, wherein the first leads are disposed in plurality and are located on a same side of the leadframe; the second pins are arranged in a plurality of numbers, the second pins are positioned on the same side of the lead frame, and the second pins and the first pins are arranged oppositely;

7. The MOSFET package structure according to any of claims 1-2, wherein the first and second leads include a connection portion, a guiding portion and a heat dissipation portion, the guiding portion is located between the connection portion and the heat dissipation portion, the connection portion and the heat dissipation portion are arranged in parallel, and the guiding portion and the connection portion are arranged obliquely so that the heat dissipation portion is located below the housing.

8. The MOSFET package of any of claims 1-2, wherein the adhesive layer has an area less than or equal to a bottom area of the transistor.

9. A die head comprising a flow-diversion trench, wherein the die head is used to produce a MOSFET package structure according to any of claims 1-8.

10. The die head of claim 9, wherein the die head has an outer dimension of 6 x 4.5mm and the die head has a cavity dimension of 0.01 mm.