CN217182625U

CN217182625U - Semiconductor packaging structure

Info

Publication number: CN217182625U
Application number: CN202221172449.2U
Authority: CN
Inventors: 陈俊玮; 叶育源; 方绪南
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2022-05-16
Filing date: 2022-05-16
Publication date: 2022-08-12
Anticipated expiration: 2032-05-16

Abstract

According to the semiconductor packaging structure, the first electrode and the second electrode are respectively arranged on the two side faces of the electronic element, and the substrate and the electronic element are jointed by using a Flip Chip technology, so that the risk of dropping or damaging the electronic element can be reduced. In addition, a concave part can be designed on the substrate so that at least one part of the electronic element is embedded into the substrate, the convex area is reduced, and the risk of dropping or damaging the electronic element is further reduced.

Description

Semiconductor packaging structure

Technical Field

The application relates to the technical field of semiconductors, in particular to a semiconductor packaging structure.

Background

Silicon photonics (SiPh) technology has a good application prospect due to its advantages of high transmission speed, low power consumption, etc. The silicon photonic technology can be applied to the related field of optical communication, such as a server or a Lidar (Lidar) device.

The structure of a silicon photon photoelectric product generally has a Laser Diode (LD) crystal grain, and as the size of the Laser Diode is smaller, the reliability is also a great test in addition to the requirement of the precision of the Laser Diode. Fig. 1 is a schematic diagram illustrating that the crystal grains of the silicon photon photoelectric product in the prior art are detached by washing, the laser diode crystal grain 42 protrudes above the substrate 41 after being bonded, when facing a plurality of washing processes, the protruding crystal grain 42 forms a water resistance, and the water resistance must bear the impact of high-pressure water column (about 5 kg) in the washing process, so that the risk of line punching, crystal grain detachment, crystal grain displacement or crystal grain strength damage exists.

SUMMERY OF THE UTILITY MODEL

The application provides a semiconductor package structure, including:

a substrate having a recess;

an electronic component electrically connected to the substrate, at least a portion of the electronic component being located within the recess.

In some alternative embodiments, the electronic component has a first electrode and a second electrode, and the first electrode and the second electrode are respectively disposed on two opposite sides of the electronic component.

In some optional embodiments, the semiconductor package structure further comprises:

first and second electrical connectors electrically connecting the substrate and the electronic component.

In some alternative embodiments, the first and second electrical connectors wrap around sides of the electronic component and a lower surface of the electronic component.

In some optional embodiments, the substrate further has a support portion protruding into the recess, and the support portion is used for supporting the electronic component.

In some alternative embodiments, the first and second electrical connections are separated by the support.

In some optional embodiments, the substrate is a photonic integrated circuit PIC.

In some alternative embodiments, the electronic component is an optical device having a light emitting surface extending from the first electrode to the second electrode.

In some alternative embodiments, the light emission direction of the optical device is parallel to the PIC.

In some alternative embodiments, the PIC has a waveguide for receiving light emitted by the optical device.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 is a schematic diagram of a prior art silicon photonic optoelectronic product with crystal grains exfoliated by water washing;

FIG. 2 is a schematic structural diagram of a semiconductor package structure provided in accordance with the present application;

FIG. 3 is a schematic top view of the portion of FIG. 2 that does not include electronic components;

fig. 4 to 10 are schematic structural diagrams in a manufacturing process of a semiconductor package structure provided in the present application.

Description of the symbols:

1-substrate, 11-recess, 12-support, 13-circuit layer, 14-first dielectric material, 15-second dielectric material, 16-waveguide, 2-electronic component, 21-first electrode, 22-second electrode, 23-electronic component area, 24-light emitting surface, 31-first electric connector, 32-second electric connector, 41-substrate, 42-laser diode grain, 43-wire, 5-suction nozzle, 6-laser, 7-photoresist coating, 8-light source, 9-mask.

Detailed Description

The following description of the embodiments of the present application will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects that the present application solves and provides by the contents of the present specification. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and are not limiting of the invention. In addition, for convenience of description, only portions related to the related utility model are shown in the drawings.

It should be noted that the structures, proportions, sizes, and other elements shown in the drawings are only used for understanding and reading the contents of the specification, and are not used for limiting the conditions under which the present application can be implemented, so they do not have the technical significance, and any structural modifications, changes in proportion, or adjustments of sizes, which do not affect the efficacy and achievement of the purposes of the present application, shall still fall within the scope of the technical content disclosed in the present application. In addition, the terms "above", "first", "second" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present application, and changes or modifications of the relative relationship may be made without substantial technical changes.

It should be further noted that, in the embodiments of the present application, the corresponding longitudinal section may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.

It should be readily understood that the meaning of "in.. on," "over,", and "above" in this application should be interpreted in the broadest sense such that "in.. on" not only means "directly on something," but also means "on something" including an intermediate member or layer between the two.

Furthermore, spatially relative terms, such as "below," "lower," "over," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 or at other orientations) and the spatially relative descriptors used in this application interpreted accordingly as such.

In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Fig. 2 is a schematic structural diagram of a semiconductor package structure provided in accordance with the present application. As shown in fig. 2, the semiconductor package structure includes a substrate 1 and an electronic component 2. The electronic component 2 is electrically connected to the substrate 1.

In the present embodiment, the substrate 1 has a recess 11. The recess 11 may be used to provide a receiving space for the electronic component 2, so that at least a portion of the electronic component 2 is located in the recess 11, thereby increasing the horizontal shearing force of the electronic component 2, avoiding the formation of high water resistance in the washing process, increasing the resistance to washing pressure impact, i.e. having low water resistance, and further reducing the risk of dropping or damaging the electronic component 2. At the same time, the position where the electronic component 2 is placed is positioned by the concave portion 11 to improve the alignment accuracy of the alignment, thereby realizing high-precision alignment. In addition, by positioning at least a part of the electronic component 2 in the recess 11, the overall structure height can be reduced to reduce the overall size.

In the present embodiment, the electronic element 2 may be an active element and a passive element.

In one embodiment, the electronic component 2 may have a first electrode 21 and a second electrode 22. The first electrode 21 and the second electrode 22 may be respectively provided on opposite side surfaces of the electronic component 2. For example, the first electrode 21 and the second electrode 22 may be gold-tin (AuSn) alloy, gold (Au), or tin (Sn). Since gold-tin alloys or gold are less prone to oxidation, no flux (flux) is required when gold-tin alloys or gold are used. The first electrode 21 and the second electrode 22 are respectively disposed on two sides of the electronic component 2, so as to avoid bridging during flip chip (flip chip).

In one embodiment, the semiconductor package structure may further include a first electrical connector 31 and a second electrical connector 32 electrically connecting the substrate 1 and the electronic element 2. First electrical connectors 31 and second electrical connectors 32 may cover the sides of electronic component 2 and the lower surface of electronic component 2. For example, the first electrical connector 31 and the second electrical connector 32 may be gold-tin alloy solder.

In one embodiment, the base plate 1 may also have a support portion 12 that is convexly provided within the recess 11. The support portion 12 may be used to support the electronic component 2. The support portion 12 may also define the thickness of the electronic component 2 embedded in the recess 11. Further, first electrical connector 31 and second electrical connector 32 may be separated by support 12, which may block contact between them from bridging shorts.

In one embodiment, when the semiconductor package structure is applied to an optoelectronic product structure such as a Silicon Photonic (SIPH) structure, the substrate 1 may be a Photonic Integrated Circuit (PIC). The electronic component 2 may be an optical device for light wave introduction and extraction of an optical communication device, such as a Laser Diode (LD).

Further, the electronic component 2 may be an optical device having a light emitting surface 24. The light emission surface 24 may extend from the first electrode 21 to the second electrode 22. The light emission direction of the optical device may be parallel to the substrate 1 (PIC).

Fig. 3 is a schematic top view of the portion of fig. 2 not including the electronic component 2. As shown in fig. 3, the substrate 1(PIC) may have a waveguide 16. The waveguide 16 may be used to receive light emitted by the electronic component 2 (optical device).

In addition, the electronic element region 23 does not entirely cover the region where the first electrical connection members 31 and the second electrical connection members 32 are located, whereby the molten bonded state of the first electrical connection members 31 and the second electrical connection members 32 (e.g., solder) can be observed from a top view in the process.

As shown in fig. 2, in the semiconductor package structure provided in this embodiment, the first electrode 21 and the second electrode 22 are respectively disposed on two side surfaces of the electronic component 2, and the substrate 1 and the electronic component 2 are bonded by using a Flip Chip technology (Flip Chip), so that the risk of dropping or damaging the electronic component 2 can be reduced. In addition, the substrate 1 may be provided with the recess 11 so that at least a portion of the electronic component 2 is embedded in the substrate 1, thereby reducing the protrusion area and further reducing the risk of dropping or damaging the electronic component 2.

Compared to some silicon photonic structures (e.g., fig. 1), the laser diode die 42 is electrically connected to the substrate 41 through the conductive line 43, and the wire bonding structure occupies a space and is difficult to reduce the overall structure size. The semiconductor packaging structure provided by the embodiment does not need routing and has no risk of wire breakage, so that the reliability of the element can be effectively improved, and the size of the whole structure can be reduced. Compared with the wire bonding structure shown in fig. 1, the semiconductor package structure provided by the embodiment has a lower resistance, and has the characteristics of strong shearing force, low water resistance, low risk of no soldering, low risk of warping, high-precision alignment, no gold-tin alloy extrusion, and the like.

First, as shown in fig. 4, a substrate 1 is provided, and the substrate 1 sequentially includes a circuit layer 13, a first dielectric material 14, and a second dielectric material 15 from bottom to top. The second dielectric material 15 may be silicon oxide, for example.

In the second step, a portion of the second dielectric material 15 is removed to form the recess 11 and the support portion 12 protruding into the recess 11. A part of the wiring layer 13 is exposed from the recess 11. Specifically, fig. 5A to 5F illustrate a method of forming the concave portion 11 and the support portion 12. As shown in fig. 5A, a photoresist coating 7 is coated on the substrate 1. As shown in fig. 5B, light emitted from the light source 8 is imaged on the photoresist coating 7 through the mask 9, i.e., an exposure operation is performed. As shown in fig. 5C, a pattern is formed on the photoresist coating layer 7, i.e., a developing operation is performed. As shown in fig. 5D, an etching operation is performed to remove a portion of the second dielectric material 15 to form the recess 11. As shown in fig. 5E, a photoresist coating 7 is applied on the substrate 1. Light emitted by the light source 8 is imaged, i.e., an exposure operation, on the photoresist coating 7 through the mask 9. As shown in fig. 5F, through the developing and etching operations, a portion of the second dielectric material 15 is removed to form the supporting portion 12.

Third, the first electrical connectors 31 and the second electrical connectors 32 are formed on the wiring layer 13 exposed from the recess 11. Specifically, fig. 6A to 6E illustrate a method of forming first electrical connector 31 and second electrical connector 32. As shown in fig. 6A, a photoresist coating 7 is coated on the substrate 1. As shown in fig. 6B, light emitted from the light source 8 is imaged on the photoresist coating 7 through the mask 9, i.e., an exposure operation is performed. As shown in fig. 6C, a pattern is formed on the photoresist coating layer 7, i.e., a developing operation is performed. As shown in fig. 6D, first electrical connection members 31 and second electrical connection members 32 are formed by Physical Vapor Deposition (PVD) in the pattern of the photoresist coating 7 (concave portions 11). As shown in fig. 6E, the photoresist coating 7 in fig. 6D is removed.

In a fourth step, parts of first electrical connections 31 and second electrical connections 32 are removed. In particular, fig. 7A to 7E show a method of removing portions of first electrical connector 31 and second electrical connector 32. As shown in fig. 7A, a photoresist coating 7 is coated on the substrate 1. As shown in fig. 7B, light emitted from the light source 8 is imaged on the photoresist coating 7 through the mask 9, i.e., an exposure operation is performed. As shown in fig. 7C, a pattern is formed on the photoresist coating layer 7, i.e., a developing operation is performed. As shown in fig. 7D, an etching operation is performed to remove portions of first electrical connections 31 and second electrical connections 32. As shown in fig. 7E, the photoresist coating 7 in fig. 7D is removed.

In a fifth step, as shown in fig. 8, the electronic component 2 is picked up by the suction nozzle 5, wherein both sides of the electronic component 2 have the first electrode 21 and the second electrode 22, respectively.

In a sixth step, as shown in fig. 9, after the alignment operation, the electronic component 2 is placed in the recess 11. The first electrical connection member 31 and the second electrical connection member 32 (e.g., solder) are melted by heating with the laser 6 to be bonded to the first electrode 21 and the second electrode 22, respectively.

Further, the heating may be performed by a heating method such as reflow (reflow). The heating method is not limited here, and it is sufficient to melt first electrical connector 31 and second electrical connector 32.

Meanwhile, the molten bonded state of the first electrical connection members 31 and the second electrical connection members 32 (e.g., solder) can be observed from a top view in this process.

In the seventh step, as shown in fig. 10, the substrate 1 and the electronic component 2 are bonded by Flip Chip technology (Flip Chip) to obtain a semiconductor package structure.

For other details and technical effects of the method in this embodiment, reference may be made to the description of the semiconductor package structure in the foregoing embodiment, which is not described herein again.

While the present application has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present application. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments without departing from the true spirit and scope of the present application as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present application and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the application that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present application. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present application. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present application.

Claims

1. A semiconductor package structure, comprising:

a substrate having a recess;

2. The semiconductor package structure of claim 1, wherein the electronic component has a first electrode and a second electrode, the first electrode and the second electrode being disposed on opposite sides of the electronic component, respectively.

3. The semiconductor package structure of claim 1, further comprising:

4. The semiconductor package structure of claim 3, wherein the first and second electrical connections encapsulate sides of the electronic component and a lower surface of the electronic component.

5. The semiconductor package structure of claim 3, wherein the substrate further has a support portion protruding into the recess, the support portion being used for supporting the electronic component.

6. The semiconductor package structure of claim 5, wherein the first electrical connection and the second electrical connection are separated by the support portion.

7. The semiconductor package structure of claim 2, wherein the substrate is a Photonic Integrated Circuit (PIC).

8. The semiconductor package of claim 7, wherein the electronic component is an optical device having a light emitting surface extending from the first electrode to the second electrode.

9. The semiconductor package structure of claim 8, wherein a light emission direction of the optical device is parallel to the PIC.

10. The semiconductor package structure of claim 8, wherein the PIC has a waveguide for receiving light emitted by the optical device.