CN217113267U

CN217113267U - Circuit for remotely upgrading FPGA chip and vehicle-mounted equipment

Info

Publication number: CN217113267U
Application number: CN202220809721.7U
Authority: CN
Inventors: 张文涛; 徐林浩; 刘明良
Original assignee: BDstar Intelligent and Connected Vehicle Technology Co Ltd
Current assignee: BDstar Intelligent and Connected Vehicle Technology Co Ltd
Priority date: 2022-04-08
Filing date: 2022-04-08
Publication date: 2022-08-02
Anticipated expiration: 2032-04-08

Abstract

The utility model provides a circuit and mobile unit of long-range upgrading FPGA chip relates to upgrading circuit technical field. The circuit includes: the system comprises a remote communication module, a central processing unit, a switching unit and a memory; the central processing unit is remotely connected with the remote communication module; the switching unit comprises a switching chip, a serial interface of the central processing unit is connected with a first switching sub-end of the switching chip, a universal interface of the central processing unit is connected with a switching terminal of the switching chip, the memory is connected with a common end of the switching chip, and the FPGA chip is connected with a second switching sub-end of the switching chip; and when the first switching sub-end of the switching chip is connected with the public end of the switching chip, the memory acquires the starting code from the central processing unit, so that the FPGA chip in the vehicle-mounted equipment is remotely and automatically upgraded.

Description

Circuit for remotely upgrading FPGA chip and vehicle-mounted equipment

Technical Field

The utility model relates to an upgrading circuit technical field especially relates to a circuit and mobile unit of long-range upgrading FPGA chip.

Background

Along with diversification and intelligentization trend of vehicle-mounted equipment, an entertainment system and a control system in a vehicle are more intelligentized, the technology of a remote upgrading system is utilized, the remote upgrading system is more and more applied to electronic products and life, and great convenience is brought. However, the existing scheme cannot realize remote automatic upgrade of the FPGA chip, a user needs to upgrade the FPGA chip independently, and the user needs to upgrade the FPGA chip through a flash disk or in a PC mode after an upgrade environment is configured in a background of a host.

SUMMERY OF THE UTILITY MODEL

The utility model provides a circuit and mobile unit of long-range upgrading FPGA chip aims at solving and can't realize the problem of long-range automatic upgrading to the FPGA chip among the current mobile unit.

In order to solve the problem, the embodiment of the utility model provides a circuit of long-range upgrading FPGA chip is provided, this circuit is applied to on the mobile unit and carries out long-range upgrading in order to realize the FPGA chip on the mobile unit, the circuit of long-range upgrading FPGA chip includes: the system comprises a remote communication module, a central processing unit, a switching unit and a memory; the central processing unit is remotely connected with the remote communication module and is used for receiving and storing an upgrading program of the FPGA chip from the remote communication module; the switching unit comprises a switching chip, a serial interface of the central processing unit is connected with a first switching sub-end of the switching chip, a general interface of the central processing unit is connected with a switching terminal of the switching chip, the memory is connected with a common end of the switching chip, and the FPGA chip is connected with a second switching sub-end of the switching chip; when the first switching sub-end of the switching chip is connected with the common end of the switching chip, the starting code in the central processing unit is updated to the memory; and when the second switching sub-terminal of the switching chip is connected with the public terminal of the switching chip, the FPGA chip acquires a starting code from the memory to start.

The switching unit further comprises a first power supply and a first capacitor, wherein the first power supply is connected with a power supply terminal of the switching chip, and the first capacitor is connected between the first power supply and the ground.

The further technical scheme is that the switching device further comprises a voltage matching unit, and the serial interface of the central processing unit is connected with the first switching sub-end of the switching unit through the voltage matching unit.

The further technical scheme is that the voltage matching unit comprises a first resistor and a voltage matching chip, the first resistor is connected between an input terminal of the voltage matching chip and a serial interface of the central processing unit, and an output terminal of the voltage matching chip is connected with a first switching terminal of the switching chip.

The voltage matching unit further comprises a second power supply, a second capacitor, a third power supply and a third capacitor, wherein the second power supply is connected with a first power supply terminal of the voltage matching chip, and the second capacitor is connected between the second power supply and the ground; the third power supply is connected with a second power supply terminal of the voltage matching chip, and the third capacitor is connected between the third power supply and the ground.

The further technical scheme is that the switching circuit further comprises a second resistor, and the general interface of the central processing unit is connected with the switching terminal of the switching chip through the second resistor.

The further technical scheme is that the model of the switching chip is SN 3257.

The further technical scheme is that the model of the voltage matching chip is TXS 0104.

The further technical proposal is that the memory is a FLASH memory.

The utility model also provides an on-board equipment, on-board equipment includes as above-mentioned arbitrary the circuit of long-range upgrading FPGA chip.

The utility model provides a circuit of long-range upgrading FPGA chip, this circuit is applied to the mobile unit in order to realize carrying out long-range upgrading to the FPGA chip on the mobile unit, receive central processing unit's control signal through the switching terminal of switching the chip, control the first switching sub-end or the second switching sub-end of switching the chip are connected with its public end, when the first switching sub-end of switching the chip is connected with its public end, the start code among the central processing unit updates to the memory; therefore, the FPGA chip in the vehicle-mounted equipment can be automatically upgraded remotely; when the second switching sub-terminal of the switching chip is connected with the public terminal of the switching chip, the FPGA chip acquires a starting code from the memory to start; the cost of manpower and time is reduced in the upgrading process, and the problem that upgrading is blocked is avoided.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without any creative effort.

Fig. 1 is a schematic diagram of a circuit for remotely upgrading an FPGA chip according to an embodiment of the present invention.

Reference numerals

A switching unit 1 and a voltage matching unit 2.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, wherein like component numbers represent like components. It is obvious that the embodiments to be described below are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

It will be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the embodiments of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the invention. As used in the description of the embodiments of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Please refer to fig. 1, which shows a schematic diagram of a circuit for remotely upgrading an FPGA chip according to an embodiment of the present invention. The circuit is applied to the vehicle-mounted equipment to remotely upgrade the FPGA chip on the vehicle-mounted equipment, and the circuit for remotely upgrading the FPGA chip comprises: the system comprises a remote communication module, a Central Processing Unit (CPU), a switching unit 1 and a memory; the central processing unit CPU is remotely connected with the remote communication module and is used for receiving and storing an upgrading program of the FPGA chip from the remote communication module; the switching unit 1 comprises a switching chip U1, a serial interface SPI of a central processing unit CPU is connected with a first switching sub end A of the switching chip U1, a general interface GPIO of the central processing unit CPU is connected with a switching terminal SEL of the switching chip U1, the memory is connected with a common end D of the switching chip U1, and the FPGA chip is connected with a second switching sub end B of the switching chip U1; when the first switch sub-terminal a of the switch chip U1 is connected with the common terminal D thereof, the start code in the central processing unit CPU is updated to the memory; when the second switch sub-terminal B of the switch chip U1 is connected to the common terminal D thereof, the FPGA chip obtains a start code from the memory to start. Specifically, in an embodiment, when the control signal sent by the general purpose interface GPIO is at a high level, the first switch terminal a of the switch chip U1 is connected to its common terminal D, the start code in the central processing unit CPU is updated to the memory, when the control signal sent by the general purpose interface GPIO is at a low level, the second switch terminal B of the switch chip U1 is connected to its common terminal D, and the FPGA chip obtains the start code from the memory to start; the automatic switching of the memory between the connection with the central processing unit CPU and the PGA chip is realized by controlling the switching chip U1 through the central processing unit CPU, so that the remote automatic upgrading of the FPGA chip in the vehicle-mounted equipment is realized, the manpower and time cost is reduced, and the problem of blocked upgrading is avoided.

It should be noted that, in the power-on process of the vehicle-mounted device, the remote communication module sends the start code of the FPGA chip to the central processing unit CPU, and the central processing unit CPU receives and stores the start code of the FPGA chip. After the vehicle-mounted equipment is powered on, a general purpose interface GPIO of a Central Processing Unit (CPU) sends a high level to a switching terminal SEL of a switching chip U1, at the moment, the Central Processing Unit (CPU) establishes communication with a memory, the Central Processing Unit (CPU) reads a small section of codes (the part of the front end of the codes) in the memory and compares the small section of codes with starting codes (the part of an FPGA) stored in the Central Processing Unit (CPU), and if the codes are consistent, the starting codes stored in the memory are latest and do not need to be updated; if the codes are not consistent, the starting code in the CPU is written into the memory to cover the original code. Then, the general purpose interface GPIO of the central processing unit CPU sends a low level to the switching terminal SEL of the switching chip U1, at this time, the FPGA chip establishes communication with the memory, and the FPGA chip acquires the start code in the memory to start.

Further, the switching unit 1 further includes a first power VCC1 and a first capacitor C1, the first power VCC1 is connected to the power terminal of the switching chip U1, and the first capacitor C1 is connected between the first power VCC1 and the ground. Specifically, in one embodiment, the first capacitor C1 filters the output of the first power source VCC1 to provide a stable power input to the switching chip U1.

Furthermore, the circuit for remotely upgrading the FPGA chip further comprises a voltage matching unit 2, and the serial interface SPI of the central processing unit CPU is connected with the first switching sub-terminal a of the switching unit 1 through the voltage matching unit 2. Specifically, in one embodiment, the level of the serial interface SPI output of the CPU is 1.8V, the memory is powered by 3.3V, and the interface on the switching unit 1 is also 3.3V, so it is necessary to match the levels between the CPU and the switching unit 1 through the voltage matching unit 2.

Further, the voltage matching unit 2 includes a first resistor R1 and a voltage matching chip U2, the first resistor R1 is connected between the input terminal I of the voltage matching chip U2 and the serial interface SPI of the central processing unit CPU, and the output terminal O of the voltage matching chip U2 is connected to the first switch terminal a of the switch chip U1. Specifically, in one embodiment, the first resistor R1 functions as an impedance matching in the circuit, and reduces the reflection on the line when the signal is transmitted from the CPU to the voltage matching chip U2, so as to improve the quality of signal transmission.

Further, the voltage matching unit 2 further includes a second power source VCC2, a second capacitor C2, a third power source VCC3, and a third capacitor C3, the second power source VCC2 is connected to the first power terminal VA of the voltage matching chip U2, and the second capacitor C2 is connected between the second power source VCC2 and ground; the third power source VCC3 is connected to the second power source terminal VB of the voltage matching chip U2, and the third capacitor C3 is connected between the third power source VCC3 and ground. Specifically, in one embodiment, the second capacitor C2 and the third capacitor C3 act as a filter in the circuit to provide a stable power input to the voltage matching chip U2. The first power supply terminal VA of the voltage matching chip U2 tracks the voltage of the second power supply VCC2, and the second power supply terminal VB tracks the voltage of the third power supply VCC 3; the first power supply terminal VA can accept any power supply voltage in the range of 1.2V to 3.6V, and the first power supply terminal VA can accept any power supply voltage in the range of 1.65V to 5.5V. In this embodiment, the voltage of the second power source VCC2 is 1.8V, and the voltage of the third power source VCC3 is 3.3V.

Further, the circuit for remotely upgrading the FPGA chip further comprises a second resistor R2, and the general purpose interface GPIO of the central processing unit CPU is connected to the switching terminal SEL of the switching chip U1 through the second resistor R2. Specifically, in one embodiment, the second resistor R2 functions as an impedance matching circuit to reduce the reflection on the circuit when the signal is transmitted from the CPU to the switch chip U1, so as to improve the quality of signal transmission.

Further, the model of the switching chip U1 is SN 3257. Specifically, in one embodiment, the switching chip U1 with model number SN3257 is a single-pole double-throw switch, a bi-directional four-channel switch, which has the advantages of high bandwidth and low delay.

Further, the model of the voltage matching chip U2 is TXS 0104. Specifically, in one embodiment, the voltage matching chip U2 of model TXS0104 enables bi-directional level shifting without direction control signals.

Further, the memory is a FLASH memory. Specifically, in one embodiment, the memory includes, but is not limited to, FLASH memory.

The utility model also provides an on-board equipment, on-board equipment includes as above-mentioned arbitrary the circuit of long-range upgrading FPGA chip. Specifically, in one embodiment, the circuit for remotely upgrading the FPGA chip is arranged in the vehicle-mounted equipment, so that the FPGA chip in the vehicle-mounted equipment is remotely and automatically upgraded, the labor and time cost is reduced, and the problem of blocked upgrade is avoided.

It should be noted that, in the power-on process of the vehicle-mounted device, the upgrade program of the FPGA chip and the system program are packaged together and sent to the central processing unit CPU through the remote communication module, the circuit of the remote upgrade FPGA chip automatically detects, judges, upgrades whether the code in the memory is the latest code and automatically downloads the latest start code, the upgrade process of the FPGA chip is covered by the system upgrade, the user does not feel, and inconvenience is not brought to the user because of upgrading the FPGA chip.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, while the invention has been described with respect to certain embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

The above description is for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope of the present invention, and these modifications or replacements should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. The utility model provides a circuit of long-range upgrading FPGA chip, this circuit is applied to on the mobile unit in order to realize carrying out long-range upgrading to the FPGA chip on the mobile unit, its characterized in that, the circuit of long-range upgrading FPGA chip includes: the system comprises a remote communication module, a central processing unit, a switching unit and a memory;

the central processing unit is remotely connected with the remote communication module and is used for receiving and storing an upgrading program of the FPGA chip from the remote communication module;

the switching unit comprises a switching chip, a serial interface of the central processing unit is connected with a first switching sub-end of the switching chip, a general interface of the central processing unit is connected with a switching terminal of the switching chip, the memory is connected with a common end of the switching chip, and the FPGA chip is connected with a second switching sub-end of the switching chip;

when the first switching sub-end of the switching chip is connected with the common end of the switching chip, the starting code in the central processing unit is updated to the memory; and when the second switching sub-terminal of the switching chip is connected with the public terminal of the switching chip, the FPGA chip acquires a starting code from the memory to start.

2. The circuit for remotely upgrading an FPGA chip according to claim 1, wherein the switching unit further comprises a first power supply and a first capacitor, the first power supply is connected with a power supply terminal of the switching chip, and the first capacitor is connected between the first power supply and ground.

3. The circuit for remotely upgrading an FPGA chip according to claim 1, further comprising a voltage matching unit, wherein the serial interface of the central processing unit is connected with the first switch terminal of the switching unit through the voltage matching unit.

4. The circuit for remotely upgrading an FPGA chip according to claim 3, wherein the voltage matching unit comprises a first resistor and a voltage matching chip, the first resistor is connected between an input terminal of the voltage matching chip and a serial interface of the CPU, and an output terminal of the voltage matching chip is connected with a first switch terminal of the switching chip.

5. The circuit for remotely upgrading an FPGA chip according to claim 3, wherein the voltage matching unit further comprises a second power supply, a second capacitor, a third power supply and a third capacitor, the second power supply is connected with the first power supply terminal of the voltage matching chip, and the second capacitor is connected between the second power supply and the ground; the third power supply is connected with a second power supply terminal of the voltage matching chip, and the third capacitor is connected between the third power supply and the ground.

6. The circuit for remotely upgrading an FPGA chip according to claim 1, further comprising a second resistor, wherein the general interface of the CPU is connected with the switching terminal of the switching chip through the second resistor.

7. The circuit for remotely upgrading an FPGA chip as recited in claim 1, wherein the model of the switching chip is SN 3257.

8. The circuit for remotely upgrading an FPGA chip as recited in claim 4, wherein the voltage matching chip is TXS0104 in model number.

9. The circuit for remotely upgrading an FPGA chip of claim 1, wherein said memory is a FLASH memory.

10. An on-board device comprising circuitry to remotely upgrade an FPGA chip as claimed in any one of claims 1 to 9.