CN217112947U - Data line driving circuit for liquid crystal display device - Google Patents
Data line driving circuit for liquid crystal display device Download PDFInfo
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- CN217112947U CN217112947U CN202220698055.4U CN202220698055U CN217112947U CN 217112947 U CN217112947 U CN 217112947U CN 202220698055 U CN202220698055 U CN 202220698055U CN 217112947 U CN217112947 U CN 217112947U
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Abstract
The utility model provides a data line drive circuit for liquid crystal display device, including many first data lines and many second data lines, change over switch connects between input stage and intermediate level, and change over switch is including being arranged in realizing that input stage and intermediate level are connected or the switch block two of interrupt in the same data line and being arranged in realizing that input stage and intermediate level are connected or interrupt when output stage polarity conversion. The utility model discloses in, when the pixel capacitance polarity of data line output changes, through switch one and the synchronous disconnection of switch two, switch three and the synchronous closure of switch four to when pixel capacitance polarity changes, use the same set of input stage amplifier to charge all the time, the pixel capacitance that can guarantee the output has the voltage deviation volume that is close when positive and negative polarity, thereby makes liquid crystal display panel can show the same luminance when changing page or leaf polarity, can effectively reduce the uneven probability of liquid crystal display.
Description
Technical Field
The utility model relates to a liquid crystal display drive technical field, concretely relates to a data line drive circuit for liquid crystal display device.
Background
In the liquid crystal display, by scanning lines using a scanning line driving circuit, voltages are applied to liquid crystal capacitors from a data line driving circuit through active elements respectively arranged at respective pixels to control a rotation angle of liquid crystal, the different rotation angles correspond to different luminances, and since the data line driving circuit is driven by many output driving lines, in 4K TV, the data line driving circuit needs to output 11520 lines, if a deviation amount of voltages between lines is excessively large, a difference in the rotation angle of liquid crystal is generated, and thus a phenomenon of luminance unevenness is seen on a liquid crystal panel, and thus, in order to avoid the above-mentioned problems on liquid crystal display, a very strict deviation amount requirement is imposed on output voltages of display lines.
SUMMERY OF THE UTILITY MODEL
The utility model provides a use same a set of input stage when liquid crystal capacitor polarity conversion to reduce amplifier circuit output level voltage deviation's inconsistency, thereby reduce the liquid crystal display device's of display demonstration uneven probability data line drive circuit.
In order to solve the technical problem, the utility model adopts the following technical scheme:
a data line driving circuit for a liquid crystal display device, comprising a plurality of first data lines and a plurality of second data lines, each of the first and second data lines including an input stage, an intermediate stage, and an output stage, further comprising:
the change-over switch is connected between the input stage and the intermediate stage, the change-over switch comprises a first switch group used for realizing connection or disconnection between the input stage and the intermediate stage in the same data line and a second switch group used for realizing connection or disconnection between the input stage and the intermediate stage in the adjacent first data line and the second data line when the polarity of the output stage is switched, and the first switch group and the second switch group are switched and separated.
Preferably, the first switch group comprises a switch K1 and a switch K2; the second switch group comprises a switch K3 and a switch K4, one end of the switch K1 is connected with the input-stage first output end O1, the other end of the switch K1 is connected with the intermediate-stage first input end O3, one end of the switch K2 is connected with the input-stage second output end O2, and the other end of the switch K2 is connected with the intermediate-stage second input end O4; the switch K3 is connected in parallel with the switch K1, one end of the switch K3 is connected with the first output end of the input stage, the other end of the switch K3 is connected with the first input end O3 of the middle stage in the adjacent data line, the switch K4 is connected in parallel with the switch K2, one end of the switch K4 is connected with the second output end O2 of the input stage, and the other end of the switch K4 is connected with the second input end O4 of the middle stage in the adjacent data line; the switch K1 and the switch K2 are switched synchronously, and the switch K3 and the switch K4 are switched synchronously.
Preferably, the input stage includes a thin film transistor VT1, a thin film transistor VT2, and a thin film transistor VT 3; the intermediate level comprises a thin film transistor VT4, a thin film transistor VT5, a thin film transistor VT6, a thin film transistor VT7, a control circuit Q1, a control circuit Q2, a thin film transistor VT8, a thin film transistor VT9, a thin film transistor VT10, a thin film transistor VT11, a thin film transistor VT12 and a thin film transistor VT 13; the source electrode of the thin film transistor VT1 is grounded, the drain electrode is connected with the source electrodes of the thin film transistor VT2 and the thin film transistor VT3, the drain of the thin film transistor VT2 is connected with one end of the switch K1, the other end of the switch K1 is connected with the thin film transistor VT4 and the thin film transistor VT6, the drain electrode of the thin film transistor VT3 is connected with one end of a switch K2, the other end of the switch K2 is connected with the thin film transistor VT5 and the thin film transistor VT7, the switch K3 is connected with the switch K1 in parallel, one end of the switch K3 is connected with the drain electrode of the thin film transistor VT2, the other end of the switch K3 is connected with a node between the junction of the other end of the switch K1 in the adjacent data line and the source electrode of the thin film transistor VT4 and the drain electrode of the thin film transistor VT6, the switch K4 is connected with the switch K2 in parallel, one end of the switch K4 is connected to the drain of the thin film transistor VT3, and the other end of the switch K4 is connected to a node between the junction of the source of the thin film transistor VT5 and the drain of the thin film transistor VT7 in the adjacent data line and the other end of the switch K2.
Preferably, the gate of the thin film transistor VT4 is connected to the gate of the thin film transistor VT5, the drain of the thin film transistor VT4 is connected to the drain of the thin film transistor VT5, the gate of the thin film transistor VT6 is connected to the gate of the thin film transistor VT7, the source of the thin film transistor VT6 is connected to the input of the control circuit Q1, the output of the control circuit Q1 is connected to the drain of the thin film transistor VT8, the source of the thin film transistor VT8 is connected to the drain of the thin film transistor VT10, the source of the thin film transistor VT10 is grounded, the source of the thin film transistor VT7 is connected to the input of the control circuit Q2, the output of the control circuit Q2 is connected to the drain of the thin film transistor VT9, the gate of the thin film transistor VT9 is connected to the gate of the thin film transistor VT8, the source of the thin film transistor VT9 is connected to the drain of the thin film transistor VT11, the gate of the thin film transistor 11 is connected to the gate of the thin film transistor VT10, the source electrode of the thin film transistor VT11 is grounded, the gate electrode of the thin film transistor VT12 is connected with the node between the source electrode of the thin film transistor VT7 and the input end of the control circuit Q2, and the source electrode of the thin film transistor VT12 is connected with the drain electrode of the thin film transistor VT 13.
Preferably, the output stage includes a switch K5, a switch K6 and a pixel capacitor C, one end of the switch K5 is connected to a node between the source of the thin film transistor VT12 and the drain of the thin film transistor VT13, the other end of the switch K5 is connected to the pixel capacitor C, the switch K6 is connected to the switch K5 in parallel, one end of the switch K6 is connected to a node between the source of the thin film transistor VT12 and the drain of the thin film transistor VT13, and the other end of the switch K6 is connected to a node between the other end of the switch K5 and the pixel capacitor in an adjacent data line.
According to the technical solution provided by the utility model, the utility model discloses following beneficial effect has: the utility model discloses a setting contains the change over switch of switch block one and switch block two, when the pixel electric capacity polarity conversion of data line output, switch one and the synchronous disconnection of switch two in the switch block one, switch three and the synchronous closure of switch four in the switch block two, thereby realize being connected between input stage and the intermediate level in the adjacent data line, thereby when output pixel electric capacity polarity conversion, use the same set of input stage amplifier all the time to charge, and then, the pixel electric capacity that can guarantee the output has the voltage deviation volume that is close when positive and negative polarity, thereby make liquid crystal display panel can show same luminance when changing page or leaf polarity, can effectively reduce the uneven problem of liquid crystal display.
Drawings
Fig. 1 is a circuit diagram of the embodiment of the present invention in which the data line S1 and the data line S2 output positive and negative polarities respectively;
FIG. 2 is a circuit diagram illustrating polarity inversion at the output terminals of the data line S1 and the data line S2 in FIG. 1;
FIG. 3 is a circuit diagram illustrating a prior art data line S1 and a data line S2 outputting positive and negative polarities, respectively;
fig. 4 is a circuit diagram illustrating the polarity inversion of the output terminals of the data line S1 and the data line S2 in fig. 3.
Detailed Description
A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings.
Since a large amount of voltage deviation between the lines in the data line driving circuit causes a difference in the rotation angle of the liquid crystal, and causes a problem of luminance unevenness in the liquid crystal panel, a strict amount of voltage deviation is required for the output voltage of the display lines. According to the principle of liquid crystal polarity, in order to make the liquid crystal rotate at the same angle when rotating different images, the deviation between the positive polarity and the negative polarity of the data line driving circuit cannot be too large, otherwise, the brightness difference is obvious when changing pages, and the problem of uneven brightness is caused.
The data line driving circuit is an amplifier circuit for driving the liquid crystal panel, and in order to avoid the problem of uneven brightness, the deviation of the output voltage of the amplifier circuit is as small as possible. Therefore, in order to make the rotation angles of the liquid crystal coincide with each other in different directions, it is desirable that the voltage deviation amount of the output stage of the amplifier circuit is the same for positive and negative polarities. And because the voltage offset of the output stage mainly comes from the input stage, the amplifier circuit can use the same input stage when outputting positive and negative polarities, so that the voltage offset with the positive and negative polarities close to each other can be kept, and the pixel capacitor of the liquid crystal panel can display the same brightness when changing the page polarity.
Based on this, referring to fig. 1 and 2, the present invention provides a data line driving circuit for a liquid crystal display device, including a plurality of first data lines and a plurality of second data lines, which are described by taking a first data line and a second data line as an example and named as a first data line S1 and a second data line S2, respectively, but the present invention provides a data line driving circuit for a liquid crystal display device not limited to two, each of the first data lines and the second data lines including an input stage, an intermediate stage and an output stage, wherein a switch is further disposed between the input stage and the intermediate stage, the switch includes a first switch group and a second switch group, the first switch group is used for implementing connection or disconnection between the input stage and the intermediate stage in the same data line, the second switch group is used for implementing connection or disconnection between the input stage and the intermediate stage in the adjacent first data line and second data line when the polarity of the pixel capacitor of the output stage is switched, and the first switch group and the second switch group are switched and separated. Therefore, through the switching function of the switch group I and the switch group II, the same input stage group is always used when the polarity of the pixel capacitor of the output stage of the amplifier circuit is switched, so that the inconsistency of the voltage deviation of the output stage of the amplifier is greatly reduced, and the probability of uneven brightness of the liquid crystal display is reduced.
Further, the input stage comprises a thin film transistor VT1, a thin film transistor VT2 and a thin film transistor VT 3; the first switch group comprises a switch K1 and a switch K2; the switch group II comprises a switch K3 and a switch K4; the intermediate level comprises a thin film transistor VT4, a thin film transistor VT5, a thin film transistor VT6, a thin film transistor VT7, a control circuit Q1, a control circuit Q2, a thin film transistor VT8, a thin film transistor VT9, a thin film transistor VT10, a thin film transistor VT11, a thin film transistor VT12 and a thin film transistor VT 13; the output stage comprises a switch K5, a switch K6 and a pixel capacitor C, wherein the switch K1 and the switch K2 are switched synchronously, the switch K3 and the switch K4 are switched synchronously, namely the switch K1 and the switch K2 are closed or opened simultaneously, and the switch K3 and the switch K4 are closed or opened simultaneously.
Further, the source of the thin film transistor VT1 is grounded, the drain of the thin film transistor VT2 is connected to the source of the thin film transistor VT3, the drain of the thin film transistor VT2 is connected to one end of the switch K1, the other end of the switch K1 is connected to the thin film transistor VT4 and the thin film transistor VT6, the drain of the thin film transistor VT3 is connected to one end of the switch K2, the other end of the switch K2 is connected to the thin film transistor VT5 and the thin film transistor VT7, the switch K7 is connected in parallel to the switch K7, one end of the switch K7 is connected to the drain of the thin film transistor VT7, the other end of the switch K7 is connected to a node between junctions between the source of the thin film transistor VT7 and the drain of the thin film transistor VT7 in an adjacent data line, the switch K7 is connected to the drain of the thin film transistor VT7, and the other end of the data line are connected to the drain of the thin film transistor VT7, and the junction between the drain of the thin film transistor VT7 and the drain of the thin film transistor VT7, and the drain of the other end of the thin film transistor VT7 are connected to the drain of the thin film transistor VT7, and the drain of the adjacent data line .
Further, the gate of the thin film transistor VT4 is connected to the gate of the thin film transistor VT5, the drain of the thin film transistor VT4 is connected to the drain of the thin film transistor VT5, the gate of the thin film transistor VT6 is connected to the gate of the thin film transistor VT7, the source of the thin film transistor VT6 is connected to the input of the control circuit Q1, the output of the control circuit Q1 is connected to the drain of the thin film transistor VT8, the source of the thin film transistor VT8 is connected to the drain of the thin film transistor VT10, the source of the thin film transistor VT10 is grounded, the source of the thin film transistor VT7 is connected to the input of the control circuit Q2, the output of the control circuit Q2 is connected to the drain of the thin film transistor VT9, the gate of the thin film transistor VT9 is connected to the gate of the thin film transistor VT8, the source of the thin film transistor VT9 is connected to the drain of the thin film transistor VT11, the grid electrode of the thin film transistor VT11 is connected with the grid electrode of the thin film transistor VT10, the source electrode of the thin film transistor VT11 is grounded, the grid electrode of the thin film transistor VT12 is connected with a node between the source electrode of the thin film transistor VT7 and the input end of the control circuit Q2, and the source electrode of the thin film transistor VT12 is connected with the drain electrode of the thin film transistor VT 13.
Further, one end of the switch K5 is connected to a node between the source of the thin film transistor VT12 and the drain of the thin film transistor VT13, the other end of the switch K5 is connected to the pixel capacitor C, the switch K6 is connected in parallel to the switch K5, one end of the switch K6 is connected to a node between the source of the thin film transistor VT12 and the drain of the thin film transistor VT13, and the other end of the switch K6 is connected to a node between the other end of the switch K5 and the pixel capacitor C in the adjacent data line.
When the pixel capacitor at the output end of the data line S1 needs to be output in positive polarity, the pixel capacitor needs to be charged by the positive polarity amplifier at the input stage of the data line S1; when the pixel capacitor at the output end of the data line S2 needs to be output with negative polarity, the pixel capacitor needs to be charged by the negative polarity amplifier at the input stage of the data line S2, because the switch K1 and the switch K2 are switched synchronously, and the switch K3 and the switch K4 are switched synchronously, when the switch K1 and the switch K2 are simultaneously closed, the switch K3 and the switch K4 are simultaneously opened, and the switch K5 is closed at the moment, the input stage and the output stage in the same data line can be conducted, that is, the input stage and the output stage in the first data line S1 and the second data line S2 are respectively conducted, so that the voltage output by the input stage in the same data line is applied to the pixel capacitor of the output stage, and the transmittance of each pixel capacitor is changed according to the voltage.
As shown in fig. 1 and 2, when the switch K3 and the switch K4 are simultaneously closed, the switch K1 and the switch K2 are simultaneously opened, the switch K6 is closed, and the switch K5 is opened, so that the input stage and the pixel capacitor of the output stage in the adjacent data line can be turned on, and the voltage output by the input stage is applied to the pixel capacitor in the adjacent data line, that is, when the pixel capacitor at the output end of the data line S1 needs to be output with negative polarity, the input stage of the data line S1 is converted into a negative polarity amplifier, and is electrically connected with the middle stage in the data line S2 through the switch K3 and the switch K4, and the pixel capacitor is charged through the negative polarity amplifier at the input stage in the data line S1; when the pixel capacitor at the output end of the data line S2 needs to be output in positive polarity, the input stage of the data line S2 is converted into a positive-polarity amplifier, and is electrically connected to the intermediate stage in the data line S1 through the switch K3 and the switch K4, and the pixel capacitor is charged through the negative-polarity amplifier of the input stage in the data line S2.
It should be noted that, the utility model discloses in the time of liquid crystal display panel polarity switching, the integrated circuit time schedule controller of driver integrated circuit front end can transmit a polarity switching signal to driver integrated circuit, comes the change over switch switching according to the height of this signal level.
As can be seen from the above-mentioned situation of polarity inversion of the pixel capacitors at the output ends of the data lines S1 and S2, when the polarity of the pixel capacitors at the output ends of the data lines is inverted, although the intermediate levels corresponding to the pixel capacitors are different, the input levels are the same, and the voltage deviation at the output ends of the data line driving circuits mainly comes from the input levels (the ratio is about 70-80%), so that the voltage deviation at the output ends of the amplifier circuits is greatly reduced, and the probability of uneven brightness of the liquid crystal display is reduced.
As shown in fig. 3 and 4, in the conventional data line driving circuit, when the pixel capacitor C at the output end of the data line S1 is output with positive polarity, the switch K5 is closed, so that the input stage and the output stage of the same data line are turned on, that is, the pixel capacitor at the output end is charged by the positive polarity amplifier at the input end of the data line S1, and correspondingly, the pixel capacitor at the output end is charged by the negative polarity amplifier at the input end of the data line S2, so that the pixel capacitor at the output end of the data line S2 is output with negative polarity. When the polarity of the pixel capacitor at the output end is switched, namely the pixel capacitor C at the output end of the data line S1 is output with negative polarity, at this time, the switch K6 is closed, and the pixel capacitor is charged through the negative polarity amplifier at the input stage of the adjacent data line S2; accordingly, when the pixel capacitor C at the output terminal of the data line S2 is positive polarity output, the pixel capacitor is charged through the positive polarity amplifier at the input stage of the adjacent data line S1. As can be seen from the above-mentioned polarity switching, the input stage amplifiers corresponding to the pixel capacitors at the output ends of the data lines S1 and S2 are different, and different input stage amplifiers have different output voltages, so that the rotation angles of the pixel capacitors at the output ends are different, and the problem of uneven brightness on the liquid crystal panel is caused.
The above-mentioned embodiments are only to describe the preferred embodiments of the present invention, but not to limit the scope of the present invention, and various modifications and improvements made by those skilled in the art without departing from the design spirit of the present invention should fall into the protection scope defined by the claims of the present invention.
Claims (5)
1. A data line driving circuit for a liquid crystal display device, comprising a plurality of first data lines and a plurality of second data lines, each of the first data lines and the second data lines including an input stage, an intermediate stage, and an output stage, further comprising:
the change-over switch is connected between the input stage and the intermediate stage, the change-over switch comprises a first switch group used for realizing connection or disconnection between the input stage and the intermediate stage in the same data line and a second switch group used for realizing connection or disconnection between the input stage and the intermediate stage in the adjacent first data line and the second data line when the polarity of the output stage is switched, and the first switch group and the second switch group are switched and separated.
2. The data line driving circuit for a liquid crystal display device according to claim 1, wherein the switch group one includes a switch K1 and a switch K2; the second switch group comprises a switch K3 and a switch K4, one end of the switch K1 is connected with the input stage first output end O1, the other end of the switch K1 is connected with the intermediate stage first input end O3, one end of the switch K2 is connected with the input stage second output end O2, and the other end of the switch K2 is connected with the intermediate stage second input end O4; the switch K3 is connected in parallel with the switch K1, one end of the switch K3 is connected with the first output end of the input stage, the other end of the switch K3 is connected with the first input end O3 of the middle stage in the adjacent data line, the switch K4 is connected in parallel with the switch K2, one end of the switch K4 is connected with the second output end O2 of the input stage, and the other end of the switch K4 is connected with the second input end O4 of the middle stage in the adjacent data line; the switch K1 and the switch K2 are switched synchronously, and the switch K3 and the switch K4 are switched synchronously.
3. The data line driving circuit for a liquid crystal display device according to claim 2, wherein the input stage includes a thin film transistor VT1, a thin film transistor VT2, and a thin film transistor VT 3; the intermediate level comprises a thin film transistor VT4, a thin film transistor VT5, a thin film transistor VT6, a thin film transistor VT7, a control circuit Q1, a control circuit Q2, a thin film transistor VT8, a thin film transistor VT9, a thin film transistor VT10, a thin film transistor VT11, a thin film transistor VT12 and a thin film transistor VT 13; the source electrode of the thin film transistor VT1 is grounded, the drain electrode is connected with the source electrodes of the thin film transistor VT2 and the thin film transistor VT3, the drain of the thin film transistor VT2 is connected with one end of the switch K1, the other end of the switch K1 is connected with the thin film transistor VT4 and the thin film transistor VT6, the drain electrode of the thin film transistor VT3 is connected with one end of a switch K2, the other end of the switch K2 is connected with the thin film transistor VT5 and the thin film transistor VT7, the switch K3 is connected with the switch K1 in parallel, one end of the switch K3 is connected with the drain electrode of the thin film transistor VT2, the other end of the switch K3 is connected with a node between the junction of the other end of the switch K1 in the adjacent data line and the source electrode of the thin film transistor VT4 and the drain electrode of the thin film transistor VT6, the switch K4 is connected with the switch K2 in parallel, one end of the switch K4 is connected to the drain of the thin film transistor VT3, and the other end of the switch K4 is connected to a node between the junction of the source of the thin film transistor VT5 and the drain of the thin film transistor VT7 in the adjacent data line and the other end of the switch K2.
4. The data line driving circuit for a liquid crystal display device according to claim 3, wherein the gate of the thin film transistor VT4 is connected to the gate of the thin film transistor VT5, the drain of the thin film transistor VT4 is connected to the drain of the thin film transistor VT5, the gate of the thin film transistor VT6 is connected to the gate of the thin film transistor VT7, the source of the thin film transistor VT6 is connected to the input terminal of the control circuit Q1, the output terminal of the control circuit Q1 is connected to the drain of the thin film transistor VT8, the source of the thin film transistor VT8 is connected to the drain of the thin film transistor VT10, the source of the thin film transistor VT10 is grounded, the source of the thin film transistor VT7 is connected to the input terminal of the control circuit Q2, the output terminal of the control circuit Q2 is connected to the drain of the thin film transistor VT9, the gate of the thin film transistor VT9 is connected to the gate of the thin film transistor VT8, the source electrode of the thin film transistor VT9 is connected with the drain electrode of the thin film transistor VT11, the grid electrode of the thin film transistor VT11 is connected with the grid electrode of the thin film transistor VT10, the source electrode of the thin film transistor VT11 is grounded, the grid electrode of the thin film transistor VT12 is connected with a node between the source electrode of the thin film transistor VT7 and the input end of the control circuit Q2, and the source electrode of the thin film transistor VT12 is connected with the drain electrode of the thin film transistor VT 13.
5. The data line driving circuit for a liquid crystal display device according to claim 4, wherein the output stage includes a switch K5, a switch K6 and a pixel capacitor C, one terminal of the switch K5 is connected to a node between a source electrode of the thin film transistor VT12 and a drain electrode of the thin film transistor VT13, the other terminal of the switch K5 is connected to the pixel capacitor C, the switch K6 is connected in parallel to the switch K5, one terminal of the switch K6 is connected to a node between a source electrode of the thin film transistor VT12 and a drain electrode of the thin film transistor VT13, and the other terminal of the switch K6 is connected to a node between the other terminal of the switch K5 and the pixel capacitor in the adjacent data line.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220698055.4U CN217112947U (en) | 2022-03-28 | 2022-03-28 | Data line driving circuit for liquid crystal display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220698055.4U CN217112947U (en) | 2022-03-28 | 2022-03-28 | Data line driving circuit for liquid crystal display device |
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