CN217087132U - Laser chip for flip chip bonding on silicon photonics chip - Google Patents

Abstract

A laser chip for flip chip bonding on a silicon photonics chip is provided. The laser chip includes: a chip main body composed of a p region and an n region in a vertical direction and extending from a front end face to a rear end face in a longitudinal direction; a pair of first vertical stoppers formed beyond both sides of the chip main body based on a wider width of the n-region, respectively; an active region buried in the chip body between the p region and the n region in the vertical direction and extending from the front end face to the back end face in the longitudinal direction; a first alignment mark formed on a top surface of the p-region near the front facet, having a lateral distance defined with sub-micron accuracy with respect to a vertical projection line of the active region in the top surface of the p-region; and a thin metal film having a skived edge shared with the front facet on a surface of the p-region.

Description

Laser chip for flip chip bonding on silicon photonics chip

Technical Field

The utility model relates to an optical telecommunication technique. More specifically, the present invention provides a laser chip for flip chip bonding on a silicon photonic chip with enhanced passive alignment.

Background

The use of communication networks has increased explosively over the past several decades. In the early days of the internet, popular applications were limited to email, bulletin boards, and were mostly informative and text-based web surfing, and the amount of data transmitted was typically relatively small. Today, internet and mobile applications require a large amount of bandwidth to transfer photos, videos, music and other multimedia files. For example, social networks like Facebook handle more than 500TB of data per day. With the demand for data and data transmission so high, there is a need to improve existing data communication systems to meet these demands.

Data rate broadband DWDM (dense wavelength division multiplexing) optical transmission of 40-Gbit/s followed by 100-Gbit/s over existing single mode fibers is the target of next generation fiber optic communication networks. Recently, optical components have been integrated on silicon substrates for the fabrication of large scale photonic integrated circuits that coexist with microelectronic chips. A series of photonic components including filters, (de) multiplexers, splitters, modulators and photodetectors have been shown (mainly on silicon photonics platforms). Silicon photonic platforms on silicon-on-insulator substrates are particularly suitable for standard WDM communications bands at 1300nm and 1550nm, since silicon (n ═ 3.48) and its oxide SiO ₂ (n ═ 1.44) are both transparent and form a high index of refraction contrast, high-confinement waveguides are ideally suited for medium-to-high integrated silicon photonic integrated circuits (SPCS).

Semiconductor lasers in silicon photonics platforms have been implemented for many applications of optical telecommunications. In some applications, laser chips are applied to silicon photonics devices by flip chip bonding for broadband high-speed optical communication with increased spectral efficiency. However, there are technical challenges to achieve excellent and reliable passive alignment in the vertical, longitudinal and lateral directions. Accordingly, improved techniques are desired.

SUMMERY OF THE UTILITY MODEL

The utility model relates to an optical telecommunication technique. More particularly, the present invention provides a laser chip and method for flip chip bonding with enhanced 3D passive alignment on a silicon photonics chip. More specifically, the present invention provides a laser chip configured with sub-micron accuracy in 3D passive alignment between a laser and a waveguide in a silicon photonic chip with less than 3dB optical loss with doubled vertical alignment tolerance window for various high-speed data communication applications (although other applications are possible).

In an embodiment, the present invention provides a laser chip for flip chip bonding on a silicon photonics chip with 3D passive alignment features. The laser chip includes: a chip body, which is constituted by a p region and an n region in a vertical direction and extends from a front end face to a rear end face in a longitudinal direction. The laser chip further includes a pair of first vertical stoppers formed beyond both sides of the chip body based on a wider width of the n-region, respectively. In addition, the laser chip includes a linearly-shaped active region buried in the chip body between the p-region and the n-region in the vertical direction and extending from the front end face to the rear end face in the longitudinal direction. Furthermore, the laser chip further comprises a first alignment mark in the longitudinal direction formed on a top surface of the p-region near the front facet, having a lateral distance defined with sub-micron accuracy with respect to a vertical projection line of the active region in the top surface of the p-region. Further, the laser chip includes a thin metal film having a cutting edge shared with the front facet on the surface of the p region.

In an alternative embodiment, the present invention provides a method for bonding laser chips with enhanced 3D alignment accuracy and tolerance on a silicon photonics chip, comprising: providing a laser chip comprising: forming a chip body having an active region buried between a p region and an n region in a vertical direction and extending from a front end face to a rear end face in a longitudinal direction; forming a pair of first vertical stoppers beyond respective sides of the chip body; forming a first alignment mark in the longitudinal direction on a top surface of the p-region near the front facet, having a lateral distance defined with sub-micron accuracy with respect to a vertical projection line of the active region in the top surface of the p-region; and forming a thin metal film having a skived edge matching the front end face; providing a chip site in a recessed surface of the silicon photonic chip, the silicon photonic chip having a waveguide port located at a height above the recessed surface, the chip site including a second pair of vertical stops on the recessed surface and a second alignment mark in the recessed surface, the second alignment mark having a lateral distance defined with sub-micron precision relative to a vertical projection line of the waveguide port in the recessed surface; bonding the laser chip with the top surface of the p-region facing down to the chip site in the recessed surface via a solder material, wherein the first pair of vertical stops respectively engage with the second pair of vertical stops for determining vertical alignment between the active region and the waveguide port; determining a lateral alignment by aligning the first alignment mark with the second alignment mark; and determining a longitudinal alignment by identifying the front facet based on a reflection contrast at the skived edge of the thin metal film.

In another alternative embodiment, the present invention provides a laser chip for flip chip bonding with enhanced passive alignment features on a silicon photonics chip. The laser chip includes a chip body composed of a p region and an n region in a vertical direction, and extending from a front end face to a rear end face in a longitudinal direction. Further, the laser chip includes a pair of first vertical stoppers formed beyond both sides of the chip body based on a wider width of the n region, respectively. Further, the laser chip includes a linearly-shaped active region, is buried in the chip body between the p-region and the n-region in the vertical direction, and extends from the front end face to the rear end face in the longitudinal direction. Further, the laser chip comprises a first alignment mark in the longitudinal direction formed on a top surface of the p-region near the front facet having a lateral distance defined with sub-micron accuracy with respect to a vertical projection line of the active region in the top surface of the p-region.

In yet another alternative embodiment, the present invention provides a laser chip for flip chip bonding with enhanced passive alignment features on a silicon photonics chip. The laser chip includes a chip body composed of a p region and an n region in a vertical direction, and extending from a front end face to a rear end face in a longitudinal direction. In addition, the laser chip includes a linearly-shaped active region buried in the chip body between the p-region and the n-region in the vertical direction and extending from the front end face to the rear end face in the longitudinal direction. Further, the laser chip comprises a first alignment mark in the longitudinal direction formed on a top surface of the p-region near the front facet having a lateral distance defined with sub-micron accuracy with respect to a vertical projection line of the active region in the top surface of the p-region. Further, the laser chip includes a thin metal film having a cutting edge shared with the front facet on the surface of the p region.

The present invention achieves these and other benefits in the context of known technologies for semiconductor lasers associated with silicon photonics platforms. However, a further understanding of the nature and advantages of the inventions may be realized by reference to the latter portions of the specification and the drawings.

Drawings

The following chart is merely an example, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize many other variations, modifications, and alternatives. It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this process and scope of the appended claims.

Fig. 1A is a top view of a laser flip chip bonded on a chip site of a silicon photonics chip with 3D alignment features according to an embodiment of the present invention.

Fig. 1B is a side view of a laser flip chip bonded on a chip site of a silicon photonics chip with 3D alignment features in accordance with an embodiment of the present invention.

Fig. 2 is a graph of optical coupling efficiency versus vertical misalignment for laser flip chip bonding on a silicon photonics chip in accordance with an embodiment of the present invention.

Fig. 3A is a schematic diagram illustrating a method of forming lateral alignment marks for a laser chip prior to regrowth of the cladding layer of the laser diode according to an embodiment of the invention.

Fig. 3B is a schematic diagram illustrating a method of forming lateral alignment marks for a laser chip after regrowth of the cladding of the laser diode according to an embodiment of the invention.

Fig. 4 is a graph of InP growth rate over the active layer for forming alignment marks after cladding layer regrowth versus oxide mask width, in accordance with an embodiment of the present invention.

Fig. 5A to 5D are schematic diagrams illustrating a method of forming a lateral alignment mark for a laser chip according to an embodiment of the present invention.

Fig. 6A is a schematic diagram illustrating a method of forming lateral alignment marks of a laser chip prior to regrowth of the cladding layer of the laser diode according to another embodiment of the invention.

Fig. 6B is a schematic diagram illustrating a method of forming lateral alignment marks for a laser chip after regrowth of the cladding layer of the laser diode according to another embodiment of the invention.

Fig. 7 is a schematic top view illustrating a method of forming a thin metal film for marking a front facet of a laser chip according to an embodiment of the present invention.

Detailed Description

The utility model relates to an optical telecommunication technique. More particularly, the present invention provides a laser chip and method for flip chip bonding with enhanced 3D passive alignment on a silicon photonics chip. More specifically, the present invention provides a laser chip configured with sub-micron accuracy in 3D passive alignment between a laser and a waveguide in a silicon photonic chip with less than 3dB optical loss with doubled vertical alignment tolerance window for various high-speed data communication applications (although other applications are possible).

The following description is presented to enable one of ordinary skill in the art to make and use the invention and is incorporated in the context of a particular application. Various modifications and uses in different applications will be apparent to those skilled in the art, and the generic principles defined herein may be applied to a wide variety of embodiments. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

The reader is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

Furthermore, any element in the claims that does not explicitly recite "a means for …" to perform a specified function, or "a step for …" to perform a particular function, should not be construed as an "means" or "a step" clause specified in chapter six, 112, 35 u.s.c. In particular, the use of "step …" or "action …" in the claims herein is not intended to refer to the provisions of chapter 112, sixth, 35 u.s.c.

Note that, if used, the label: inner, outer, left, right, front, back, top, bottom, end, side, forward, reverse, vertical, longitudinal, transverse, concave, ridge, valley, clockwise, and counterclockwise are used for convenience only and are not intended to imply any particular securing orientation. Rather, they are used to reflect the relative position and/or orientation between various parts of the object.

In one aspect, the present disclosure provides a semiconductor laser chip with enhanced 3D passive alignment for flip chip bonding on a silicon photonic chip. In an example, the laser may be configured for high power operability of a semiconductor optical amplifier in a broadband wavelength tunable laser applied in a silicon photonic platform. Fig. 1A is a top view of a laser flip chip bonded on a chip site in a recessed surface of a silicon photonics chip with 3D alignment features according to an embodiment of the present invention, and fig. 1B is a side view of a laser flip chip bonded on a chip site in a recessed surface of a silicon photonics chip with 3D alignment features according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown, in a top view, a laser chip with p-region 103 facing upward and n-region 105 facing downward is shown on the left side of the figure. The laser chip comprises an active region 101 (which should in fact be located below the p-region 103 and not directly visible in top view), the active region 101 being located between the p-region 103 and the n-region 105 and extending in the longitudinal direction (y-direction) from a front facet 107 to a back facet 108. Optionally, n-region 105 has a wider width than P-region 103. Based on the wider width of the n-region 105, a pair of first vertical stops 201 are formed beyond two opposite sides of the p-region 103. Optionally, the first vertical stop 201 has an elongated shape in the y-direction. In this top view, the laser chip also includes one or two alignment marks 203 on the surface of the p-region 103. Each alignment mark 203 is a linear feature near the front facet 107 in the longitudinal (y) direction that is located at a lateral distance d from the projected line of the active region 101 at the top surface of the p-region 103, respectively. Alternatively, two alignment marks are symmetrically formed on both sides having an equal distance d with respect to the projection line of the active region 101 at the top surface of the p region 103. Alternatively, the distance d may be controlled with submicron precision by using a photolithography mask and performing a laser confinement/cladding (clad layer) regrowth process around the laser active region 101. Further, a thin metal film 205 is formed that shares an edge with the front facet 107, which is configured to identify the position of the front facet of the laser under the microscope to facilitate alignment in the longitudinal (Y) direction.

Referring to fig. 1A, in a top view, a laser chip is designed to be flip chip bonded to a chip site 300 that is pre-disposed on a surface 30 of a silicon photonics chip. As shown in the middle of the top view, the chip site 300 includes at least one pair of second vertical stoppers 301 erected on the surface 30 of the silicon photonics chip, having an elongated shape along the y-direction, and having a lateral spacing substantially equal to that of the pair of first vertical stoppers 201. The chip site 300 is also formed with two alignment marks 303 engraved into the surface of the surface 30 of the silicon photonics chip, which are designed to align with the alignment marks 203 on the laser chip in the lateral (x) direction with sub-micron accuracy.

Referring again to fig. 1A, in the top view of the right portion, the laser chip is flip-chip bonded to a chip site 300 in the surface 30 of the silicon photonics chip. In the flip-chip bonding position, when the pair of first vertical stops 201 and the pair of second vertical stops 301 have substantially equal lateral spacing, the pair of first vertical stops 201 on the laser chip abut or engage (join) the pair of second vertical stops on the surface 30. As will be shown later, each of the first and second vertical stops has a particular height design such that the active region 101 of the laser chip is aligned in the vertical (z) direction with a waveguide in the silicon photonics chip, and has a desired optical coupling loss of less than 3dB in a relatively large vertical distance tolerance window. The alignment mark 203 of the laser chip is used to align with the alignment mark 303 on the surface 30 of the silicon photonics chip so that the active region 101 of the laser chip can be aligned with the waveguide with sub-micron precision in the lateral (x) direction to support the realization of less than 3dB coupling loss of laser light entering the waveguide from the active region. The thin metal film 205 may be used to generate good contrast for optical reflection for identifying the position of the front facet 107, which is a key reference point for alignment in the longitudinal y-direction to support the realization of less than 3db coupling loss of laser light entering the waveguide from the active region.

Referring to fig. 1B, an upper side view illustrates a cross-sectional view along the AA' plane (along the x-direction) of a laser chip flip-chip bonded on a recessed surface 30 of a silicon photonics chip. As shown, the p-region 103 is turned face down and bonded to the recessed surface 30 of the silicon photonics chip (chip site 300) via solder material 305. At the same time, the pair of first vertical stops 201 is brought close to the pair of second vertical stops 301 to bond with the second vertical stops 301, the pair of second vertical stops 301 determining the vertical position of the active region 101, while the surface of the P region can flexibly push away the additional solder material 305 to deposit (pitch) on top of the recessed surface 30 with the remainder of the solder material 305.

The lower portion of the side view illustration shows a cross-sectional view along the BB' plane (along the y-direction) of a laser chip flip-chip bonded on the recessed surface 30 of the silicon photonics chip via solder material 305, with the active region 101 laid in a substantially linear shape between the p-region 103 (at the bottom) and the n-region 105 (on the top). Alternatively, when the p-region is deposited on the recessed surface 30 via the solder material 305, the active region 101 is disposed at a height h above the recessed surface 30 ₁ To (3). When formed in a silicon photonics chip, the optical waveguide 310 runs horizontally along the y-direction, with a receiving port at the sidewall associated with the recessed surface 30 facing the front facet 107 of the laser flip-chip. Optionally, the optical waveguide 310 including the port at the sidewall is designed to have a height h above the recessed surface 30 ₂ . As shown in fig. 2, perfect vertical alignment is required for ideal optical alignment with maximum coupling efficiency between linear active region 101 and optical waveguide 310 to give h ₁ ＝h ₂ Or vertical misalignment value g ═ h ₁ -h ₂ ＝0。

Referring to fig. 2, the maximum coupling efficiency corresponding to perfect vertical alignment may be associated with a coupling loss of about-2 dB. For laser flip-chip bonding, the vertical alignment position of the active region of the laser relative to the waveguide port in the silicon photonics chip is primarily determined by the relative position of the first pair of vertical stops relative to the active region in the laser chip and the relative position of the second pair of vertical stops relative to the optical waveguide in the silicon photonics chip. This may give maximum coupling efficiency when the active region 101 is perfectly aligned to the port of the optical waveguide 310 at the sidewall with a vertical misalignment value g of 0. In practice, however, there may always be some debris forming a stop plane to the second (or first) vertical stop, so that when they are connected together the laser chip and hence the active region 101 is physically forced to be placed higher. This allows the coupling efficiency between the active region and the optical waveguide 310 to fall within the range of R0, given the worst acceptable coupling efficiency of-3 dB. Therefore, R0 becomes a vertical alignment tolerance (tolerance) range. Alternatively, the tolerance range R0 is from 0 to about 0.5-0.7 μm.

In an embodiment of the present invention, the vertical alignment design of the laser chip is based on the vertical height of the stop plane of the second vertical stop 301 relative to the optical waveguide 310 above the recessed surface 30 in the corresponding silicon photonic chip for the laser chip to be bonded, the vertical height of the first vertical stop 201 in the laser chip to the stop plane relative to the active region 101 being adjusted during the molding process of the laser chip. The stop plane referred to here is the end plane of the vertical stop. The vertical height of the first vertical stop 201 is the height of the corresponding stop plane relative to its base at the n-region 105, with the n-region 105 having a wider width relative to the n-region 103. The vertical height of the second vertical stop 301 is the height of the corresponding stop plane relative to its base at the recessed surface 30. The goal of the vertical alignment design is to intentionally set the vertical misalignment value g <0 to be about-0.5 μm-0.7 μm lower than the optical waveguide 310. In this embodiment, as shown in FIG. 2, the vertical alignment tolerance range R1 almost doubles in window size from-0.5 to-0.7 μm to +0.5 to 0.7 μm for the same acceptable coupling efficiency of-3 dB between the active region 101 and the optical waveguide 310.

In another aspect, the present invention provides a method of forming a laser chipset for flip chip bonding on a silicon photonics chip with sub-micron precision using 3D passive optical alignment. Fig. 1A-1B illustrate features for achieving lateral alignment in a chip site of a silicon photonics chip that use vertical stops to control/adjust vertical alignment tolerance with sub-micron accuracy, as well as features of alignment marks on the top surface of the p-region of the laser chip. Fig. 3A-3B are schematic diagrams illustrating a method of forming lateral alignment marks for a laser chip before (a) and after (B) regrowth of the cladding layer of the laser diode, respectively, in accordance with an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

In an embodiment, fig. 3A shows a schematic diagram of an intermediate portion of a laser chip formation process. As shown, an active layer 400 is formed over the confinement/cladding layer 40. Depending on the operating wavelength spectrum, the active layer 400 comprises different semiconductor materials, including one or more compound semiconductors or a combination of InAsP, GalnNAs, GaInAsP and A1GaInAs configured as a multiple quantum well structure. The confinement/cladding layer 40 typically comprises InP-based semiconductor materials with various doping profiles and different energy gaps compared to the energy gap of the active layer 400. Optionally, the confinement/cladding layer 40 is doped with an n-type impurity to be configured as an n-region 105 (n-region 105 of the laser chip, see fig. 1A-1B).

Referring to fig. 3A, a method of forming a set of laser chips for flip chip bonding to a silicon photonics chip with 3D passive optical alignment includes: a first oxide mask 401 of a first width w1 is placed over the active layer 400 where the active region 101 (fig. 1A-1B) is to be formed, and a second oxide mask 402 of a second width w2 is placed over the active layer 400 where the first alignment mark is to be formed. Fig. 3A is a cross-sectional view illustrating the second oxide mask 402 of width w2 formed at a lateral distance s from the first oxide mask 401 of width w 1. This can be done using well established techniques of masking and lithography to achieve sub-micron accuracy in setting the dimensions of w1, w2 and s. Alternatively, the first width w1 is set to be about 1.5 μm to 3.5 μm. Alternatively, as shown in FIG. 3A, the second width w2 is set to be about 0.1 μm to 2 μm or 1 to 3.5 μm smaller than the first width w 1. Alternatively, as shown in FIG. 6A, in another embodiment, the second width w2 is set to be about 2.5 μm to 8.5 μm or 1 μm to 5 μm greater than the first width w 1. Optionally, the first width w1 and the second width w2 are configured to have a difference between 1 μm and 5 μm at their lateral positions at sub-micron accuracy. Alternatively, third oxide masks similar to the second oxide mask may be formed at equal intervals d on opposite sides of the first oxide mask, intended to form symmetrical first alignment marks.

Referring to fig. 3B, a method of forming a laser chipset for flip chip bonding to a silicon photonics chip with 3D passive optical alignment includes: a regrowth process applied to the structure shown in fig. 3A is performed to form alignment marks 203 on the regrown top surface of the p-region of the laser chip. Fig. 3B shows a cross-sectional view of the completed p-region formed by the regrowth of the p-type confinement/cladding layer 40 'with the mask removed, leaving the active region 101 under the first oxide mask, and a narrower portion 112 of the active layer (400) under the second oxide mask (402) between the p-type confinement/cladding layer 40' and the n-type confinement/cladding layer 40. Note that although not shown in this cross-sectional view, the active region 101 has a long length extending from the front facet to the back facet of the laser chip in the longitudinal y-direction (perpendicular to the cross-sectional plane), while the narrower portion 112 has only a short length in the longitudinal y-direction. In particular, the top surface of the completed p-region includes a profile having a relatively flat region 411 above the previously placed first oxide mask resulting in the formation of the active region 101 due to the more uniform growth rate of the nearby p-type confinement/cladding layer 40 ', and the top surface of the completed p-region also includes a short length of shallow-trench (bunker) region 413 near the small peak/ridge bump region 203 on the previously placed second oxide mask resulting in the formation of a narrower portion 112 of the active layer due to the slower growth rate of the nearby p-type confinement/cladding layer 40'.

Fig. 4 is a graph of InP growth rate versus oxide mask width over an active layer used to form alignment marks after cladding layer regrowth, in accordance with an embodiment of the present invention. As shown, the growth of the cladding layer under the regrowth process associated with different oxide masks shows interesting effects: the growth enhancement of the InP based cladding layer in the regrowth process depends almost linearly on the oxide mask width. This effect causes the growth rate of the InP-based material in the regions associated with the second oxide mask of second width w2 to be smaller relative to the growth rate of the InP-based material in the regions associated with the first oxide mask of first width w1(w1 > w2) during the regrowth process after the masks are removed (see fig. 3A). Thus, as the regrowth process progresses, the shallow-trench regions 413 are formed and effectively form short-length ridge-bump regions 203 (fig. 3B) that are substantially vertically on top of the previously placed second oxide mask 402 locations (and now indicated by the narrower portions of the active layer 112 that remain in the middle of the cladding layer). Alternatively, the second ridge bump regions may be formed based on a third oxide mask on the other side with an equal spacing d with respect to the active region.

In another embodiment shown in fig. 6A, the second width w2 of the second mask 402 may be made larger than the first width w1 of the first oxide mask 401. Optionally, the first width w1 and the second width w2 are configured to have a difference between 1 μm and 5 μm in their lateral position at the pitch s at sub-micron accuracy. Alternatively, the first width w1 is set to be about 1.5 μm to 3.5 μm. The second width w2 is set to be about 2.5 μm to 8.5 μm. The growth enhancement effect shown in fig. 4 still works in the same way, so that the growth enhancement of the InP-based cladding layer in the regrowth process depends almost linearly on the oxide mask width. The growth rate of the cladding layer around the area near the second oxide mask will be greater than the growth rate around the area near the first oxide mask. As the regrowth process is applied to the structure shown in fig. 6A, the regrowth process with different growth rates in different oxide mask widths results in the formation of alignment marks 203' on the regrown top surface of the p-region of the laser chip (fig. 6B). Fig. 6B shows a cross-sectional view of the completed p-region formed by the regrowth of the p-type confinement/cladding layer 40 ' with the mask removed, leaving the active region 101 under the first oxide mask and the wider portion 112 ' of the active layer (400) under the second oxide mask (402 ') between the p-type confinement/cladding layer 40 ' and the n-type confinement/cladding layer 40 '. Note that although not shown in this sectional view, the active region 101 has a long length extending from the front end face to the rear end face of the laser chip in the longitudinal y direction (perpendicular to the cross-sectional plane), while the shorter portion 112 has only a short length in the longitudinal y direction. The top surface of the completed p-region in fig. 6B includes a relatively flat area 411 profile over the previously placed first oxide mask resulting in the formation of the active region 101 due to the more uniform growth rate of the nearby p-type confinement/cladding layer 40 ', and also includes a hillock region 443 over the previously placed second oxide mask having a short length near the valley region 203 resulting in the formation of a wider portion 112' of the active layer due to the higher growth rate of the nearby p-type confinement/cladding layer 40.

Finally, since the p-region of the laser chip is formed after the final growth to form the p-region having the top surface, the ridge bump region 203 or the valley depression region 203 'is formed with the shallow-groove region 413 higher than the periphery or the hillock region 443 lower than the periphery to become the first alignment mark 203 or 203' on the top surface of the p-region, as shown in fig. 1A. Alternatively, the lateral position carried by the projection line of the first alignment mark 203 (203') with respect to the active region 101 on the top surface of the p region is the same as the lateral position of the previously placed second oxide mask 402 with respect to the first oxide mask 401. Since the oxide mask can be laid down in its lateral position with sub-micron accuracy, the first alignment mark 203 (203') formed on the laser chip carries the same sub-micron accuracy that can be used to achieve the desired lateral alignment of the laser flip-chip bonded to the silicon photonics chip. Alternatively, another first alignment mark having similar ridge/valley regions may be symmetrically formed at opposite sides with an equal interval d with respect to a projection line of the active region at the top surface of the p region.

Fig. 5A to 5D are schematic diagrams illustrating a method of forming a lateral alignment mark for a laser chip according to an embodiment of the present invention. These figures are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, possibilities, and modifications. In a particular embodiment, the method includes the steps of placing a first oxide mask 401 over the active layer 400 where the active region 101 (fig. 1A-1B) is to be formed, and placing a second oxide mask 402 of a second width w2 over the active layer 400 where the alignment mark is to be formed. Optionally, an oxide layer is deposited on the active layer 400. A patterning/photolithography process is performed on the oxide layer to define a first mask 401 having a first width w1 (and a first length extending in the longitudinal y-direction from a front facet position to a back facet position) and a second mask 402 having a second width w2 (and a second length parallel to the first length of about 1 μm or less). Optionally, the first width w1 and the second width w2 are configured to have a difference between 1 μm and 5 μm at their lateral positions with a sub-micron precision pitch s. Optionally, an oxide etch process is performed to cause formation of a first oxide mask 401 and a second oxide mask 402 (see fig. 5A).

In addition, the method includes mesa etching (mesa etching) to remove the unmasked active layer 400, which includes additional portions of the n-type confinement/cladding layer 40 under the active layer 400 that utilize portions of the undercut oxide mask to form voids 421, 422, 423 (see fig. 5B) around the oxide mask. In addition, the method includes, as shown in fig. 5C, forming current blocking layers 431, 432, 433 in those voids 421, 422, 423. Optionally, current blocking layer 431 or 432 or 433 is made of a reverse biased p-n junction layer (e.g., a first p-type InP layer, followed by an n-type InP layer). Alternatively, the current blocking layer 431 or 432 or 433 may be a p-n-i-n structure or an iron-doped insulating material. A reverse biased p-n junction will block current flow from the sides. Current flows only from the active region where the p-n junction is not reverse biased. These current blocking layers cause a regrowth enhancing effect so that the growth rate around the oxide mask differs depending on the width of the oxide mask. Optionally, the regrowth rate extracted in the region above the current blocking layer is higher than the regrowth rate extracted in the region above the second current blocking layer. Optionally, the method comprises the step of removing the first oxide mask and the second oxide mask to leave the active region 101 having a first length and a narrower second portion of the active layer 112 having a short second length.

Further, the method includes the step of performing a regrowth process to add a confinement/cladding layer (p-type) to the structure of fig. 5C, wherein the oxide mask is removed. The regrowth process includes depositing a p-type InP-based material using MOCVD to grow the p-region 40 'of the laser chip, the p-region 40' of the laser chip having a different growth rate for the region caused by the current blocking layer around the active region 101 and the region caused by the current blocking layer around the narrower second portion of the active layer 112. Optionally, the growth rate of the InP-based material is lower around the narrower second portion of the active layer 112 to create a shallow-trench (bunker) region 413, while resulting in a hillock region 203 over the narrower second portion of the active layer 112. The area above the active area 101 grows at a relatively uniform rate (higher than the rate of the shallow-trench area 413) to achieve a relatively flat area 411. Furthermore, the method comprises the step of performing a final growth to complete the formation of the p-region 40 ', wherein the top surface of the p-region 40' has a relatively flat region 411 covering the active region 101 and a ridge region 203 over the narrower second portion of the active layer 112 and having a short length in the longitudinal direction. On the top surface of the p-region 40', the ridge region 203 becomes a first alignment mark. Alternatively, another ridge region having a similar structure may be formed on the opposite side by placing the third oxide mask at an opposite position having an equal lateral distance s with respect to the first oxide mask. Thus, alternatively, the first alignment mark formed on the laser chip may be a pair of alignment marks having symmetrical lateral positions with respect to the active region. Alternatively, the lateral position of these alignment marks may be determined with sub-micron accuracy on one or both symmetrical sides of the active area of the laser chip. Optionally, these alignment marks may be formed at the top surface of the p-region or the n-region, depending on the fabrication process settings.

Alternatively, one or two first alignment marks formed in the laser chip as described above may be used to laterally align a laser used for flip chip bonding to a chip site on a silicon photonics chip with one or two corresponding second alignment marks formed on the (recessed) surface on which the chip site is designed (see fig. 1A-1B). The second alignment marks on the (recessed surface) of the silicon photonics chip may be formed in many ways with sub-micron precision to meet the requirements of passive alignment between the active region and the waveguide port.

In another embodiment, the laser chip is formed with another alignment feature configured to identify the front facet of the chip body so that the laser chip can be well positioned along the longitudinal direction (along the active region). Fig. 7 is a schematic top view diagram illustrating a method of forming a thin metal film for marking a front facet of a laser chip according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown, in the simplified diagram, two adjacent chip dies are shown on a wafer used to fabricate the laser chips. Referring to the die 1, which is almost completed in the manufacturing process, the laser chip of the die 1 includes all the features shown in fig. 1A-1B, including the p-region 103, the n-region 105, the active region 101 buried between the p-region and the n-region, the two vertical stops 201, the pair of first alignment marks 203 formed on the top surface of the p-region 103. In addition, the laser chip of die 1 also includes a thin metal film 205 formed on the top surface of p-region 103. Alternatively, the thin metal film 205 may be formed in the same process used to form the patterned p-type metal on the top surface of the p-region 103, the p-type metal film 205 being configured to form electrical contacts for the laser chip. In particular, die 1 and die 2 remain in a single body in the wafer. Due to the wafer process, a thin metal film 205 is patterned and formed across a boundary line 107 perpendicular to the active region 101 between the die 1 and the die 2. At the end of the wafer process for forming the laser chips, a dicing process is performed to dice the wafer through the boundary line covered with the thin metal film to separate the die 1 from the die 2 to obtain respective individual laser chips. The dicing process automatically creates a cut edge (cleaned edge) of the thin metal film and an end face for each of the two laser chip bodies. Thus, the laser chip is obtained with the front facet 107 sharing a skived edge with the thin metal film 205, making the skived edge an automatic alignment feature for identifying the front facet 107 for optical alignment along the longitudinal direction when the laser chip is flip-chip bonded to a silicon photonics chip.

Embodiments of the present disclosure provide a method for bonding laser chips with enhanced 3D alignment accuracy and tolerance on silicon photonics chips, comprising: providing a laser chip comprising: forming a chip body having an active region buried between a p region and an n region in a vertical direction and extending from a front end face to a rear end face in a longitudinal direction; forming a pair of first vertical stoppers beyond respective sides of the chip body; forming a first alignment mark in the longitudinal direction on a top surface of the p-region near the front facet, having a lateral distance defined with sub-micron accuracy with respect to a vertical projection line of the active region in the top surface of the p-region; and forming a thin metal film having a skived edge matching the front end face; providing a chip site in a recessed surface of the silicon photonic chip, the silicon photonic chip having a waveguide port located at a height above the recessed surface, the chip site including a second pair of vertical stops on the recessed surface and a second alignment mark in the recessed surface, the second alignment mark having a lateral distance defined with sub-micron precision relative to a vertical projection line of the waveguide port in the recessed surface; bonding the laser chip with the top surface of the p-region facing down to the chip site in the recessed surface via a solder material, wherein the first pair of vertical stops respectively engage with the second pair of vertical stops for determining vertical alignment between the active region and the waveguide port; determining a lateral alignment by aligning the first alignment mark with the second alignment mark; and determining a longitudinal alignment by identifying the front facet based on a reflection contrast at the skived edge of the thin metal film.

In one implementation, the chip site setting includes: a second stop plane is defined above the recessed surface with sub-micron precision relative to the waveguide port for each of the pair of second vertical stops.

In one implementation, wherein forming the first vertical stop pair comprises: in accordance with the second stop planes defined for each of the second pair of vertical stops above the recessed surface of the silicon photonics chip, a first stop plane is defined for each of the first pair of vertical stops relative to the active region of the laser chip.

In one implementation, defining the first stop plane for each of the pair of first vertical stops includes: providing an etch stop material at a location having a defined vertical distance relative to the active region and a defined lateral distance beyond each of two sides of the p-region of the chip body.

In one implementation, wherein defining the first stop plane for each of the pair of first vertical stops further comprises: setting a position of the active region of the laser chip to be vertically lower than a height of the waveguide port by about 0.5 to 0.7 μm based on the vertical distance defined by the first stopper plane with respect to the second stopper plane above the active region and the recess surface when the first stopper plane is combined with the second stopper plane.

In one implementation, wherein setting the position of the active region to be vertically lower than the height of the waveguide port by about 0.5 μ ι η to 0.7 μ ι η comprises: doubling a vertical alignment tolerance window for the laser chip to flip-chip bond to the chip site in the recessed surface of the silicon photonics chip via the solder material with a limit of less than 3dB of coupling loss.

In one implementation, wherein forming the first alignment mark comprises: after forming an active layer on an n region of the laser chip, placing a first oxide mask of a first width over the active layer where the active region is to be formed, and placing a second oxide mask of a second width over the active layer where the first alignment mark is to be formed at the lateral position with sub-micron accuracy with respect to the first oxide mask, wherein the first width is about 1 to 5 μm greater than the second width; performing a mesa etch to remove a major portion of the active layer except for the active region under the first oxide mask and a narrower second portion of the active layer under the second oxide mask; forming a first current blocking layer around the active region and a second current blocking layer around the narrower second portion of the active layer, wherein a higher regrowth rate is induced for a region around the first oxide mask than for a region around the second oxide mask; removing the first oxide mask and the second oxide mask; performing a regrowth of a p-region of the laser chip at a higher growth rate around the active region and a lower growth rate around the narrower second portion of the active layer; and performing a final growth to complete formation of the p-region having a top surface with a relatively flat region over the active region and a ridge feature having a short length in a longitudinal direction over the narrower second portion of the active layer, wherein the ridge feature becomes the first alignment mark.

In one implementation, wherein forming the first alignment mark comprises: after forming an active layer on an n region of the laser chip, placing a first oxide mask of a first width over the active layer where the active region is to be formed, and placing a second oxide mask of a second width over the first alignment mark is to be formed over the active layer at the lateral position with sub-micron precision with respect to the first oxide mask, wherein the first width is smaller than the second width by about 1 to 5 μm; performing a mesa etch to remove a major portion of the active layer except for the active region under the first oxide mask and a wider second portion of the active layer under the second oxide mask; forming a first current blocking layer around the active region and a second current blocking layer around the wider second portion of the active layer, wherein a regrowth rate induced for a region around the first oxide mask is lower than a regrowth rate induced for a region around the second oxide mask; removing the first oxide mask and the second oxide mask; performing a regrowth of a p-region of the laser chip at a lower growth rate around the active region and a higher growth rate around the wider second portion of the active layer; and performing a final growth to complete formation of the p-region having a top surface with a relatively flat region over the active region and a valley feature having a short length in a longitudinal direction over the wider second portion of the active layer, wherein the valley feature becomes the first alignment mark.

In one implementation, wherein forming the thin metal film comprises: performing a wafer process to form a metal contact layer on the top surface of the p-region, the metal contact layer comprising the thin metal film formed across a boundary of two adjacent laser chip dies, wherein the wafer process further comprises cutting through the boundary to shave the thin metal film to obtain the shaved edge and form the front facet matching the shaved edge for two laser chips.

While the above is a complete description of certain embodiments, various modifications, alternative constructions, and equivalents may be used. Accordingly, the above description and illustrations should not be taken as limiting the scope of the invention, which is defined by the appended claims.

Claims (11)

1. A laser chip for flip chip bonding on a silicon photonics chip with 3D passive alignment features, the laser chip comprising:

a chip body constituted by a p region and an n region in a vertical direction and extending from a front end face to a rear end face in a longitudinal direction;

a pair of first vertical stoppers formed beyond both sides of the chip body based on a wider width of the n-region, respectively;

a linearly-shaped active region buried in the chip body between the p-region and the n-region in the vertical direction and extending from the front end face to the back end face in the longitudinal direction;

a first alignment mark in the longitudinal direction formed on a top surface of the p-region near the front end face, having a lateral distance defined with sub-micron accuracy with respect to a vertical projection line of the active region in the top surface of the p-region; and

a thin metal film on the surface of the p-region having a skived edge shared with the front facet.

2. The laser chip of claim 1, wherein the first alignment mark comprises one line feature in the top surface of the p-region, the one line feature being formed via a regrowth process using one alignment oxide mask of a second width, the one alignment oxide mask being placed on an active layer at a location having a lateral distance defined with sub-micron precision relative to an active region oxide mask of a first width placed on the same active layer used to form the active region, the first width differing from the second width by 1 to 5 μ ι η.

3. The laser chip of claim 1, wherein the first alignment mark comprises two line features in the top surface of the p-region, the two line features formed via a regrowth process using two alignment oxide masks of a second width placed on an active layer at two locations having a lateral distance of sub-micron precision at respective two opposing sides of an active region oxide mask of a first width placed on the same active layer used to form the active region, the first width differing from the second width by 1 to 5 μ ι η.

4. The laser chip according to claim 1, wherein the first alignment mark in the longitudinal direction is alternatively formed on a top surface of the n-region near the front facet, having a lateral distance defined with sub-micron accuracy with respect to a vertical projection line of the active region in the top surface of the n-region.

5. The laser chip of claim 1, wherein, depending on the design used for the silicon photonic chip, each of the pair of first vertical stops is defined by a first stop plane at a vertical distance relative to the active region, the silicon photonics chip having a chip site in a surface, the chip site including a pair of second vertical stops, each second vertical stop defined by a second stop plane located at a vertical distance relative to a waveguide port located at a height above the surface of the silicon photonics chip, such that when the laser chip is flipped such that the p-region is bonded to the chip site in the surface via solder material with the first stop plane and the second stop plane joined, the active region is disposed 0.5 μm to 0.7 μm lower than a height of the waveguide port.

6. The laser chip of claim 1, wherein the thin metal film is formed in the same wafer process used to form a contact metal layer on the top surface of the p-region.

7. The laser chip of claim 6, wherein the wafer process further comprises:

forming the thin metal film across a boundary of two adjacent laser chip dies on a top surface of the p-region; and

the wafer is cut through the boundary to shave the thin metal film to obtain the shaved edge, and the front facet matching the shaved edges of the two laser chips is formed.

8. The laser chip of claim 1, wherein the active region comprises a heterojunction structure based on a compound semiconductor InAsP, GalnNAs, GalnAsP, GaInAs, or AlGalnAs.

9. The laser chip of claim 1, wherein the p-region and the n-region comprise respective p-type InP-based compound semiconductors or n-type InP-based compound semiconductors.

10. A laser chip for flip chip bonding with enhanced passive alignment features on a silicon photonics chip, the laser chip comprising:

a chip main body composed of a p region and an n region in a vertical direction and extending from a front end face to a rear end face in a longitudinal direction;

a pair of first vertical stoppers formed beyond both sides of the chip body based on a wider width of the n-region, respectively;

a linearly-shaped active region buried in the chip body between the p-region and the n-region in the vertical direction and extending from the front end face to the back end face in the longitudinal direction; and

a first alignment mark in the longitudinal direction formed on a top surface of the p-region near the front end face, having a lateral distance defined with sub-micron accuracy with respect to a vertical projection line of the active region in the top surface of the p-region.

11. A laser chip for flip chip bonding with enhanced passive alignment features on a silicon photonics chip, the laser chip comprising:

a chip body constituted by a p region and an n region in a vertical direction and extending from a front end face to a rear end face in a longitudinal direction;

a linearly-shaped active region buried in the chip body between the p-region and the n-region in the vertical direction and extending from the front end face to the back end face in the longitudinal direction;

a first alignment mark in the longitudinal direction formed on a top surface of the p-region near the front end face, having a lateral distance defined with sub-micron accuracy with respect to a vertical projection line of the active region in the top surface of the p-region; and

a thin metal film on the surface of the p-region having a skived edge shared with the front facet.

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