CN217086139U

CN217086139U - Power supply protection circuit, test equipment and test system of solid state disk

Info

Publication number: CN217086139U
Application number: CN202220025765.0U
Authority: CN
Inventors: 孙成思; 孙日欣; 柏艾林; 徐永刚
Original assignee: Biwin Storage Technology Co Ltd
Current assignee: Biwin Storage Technology Co Ltd
Priority date: 2022-01-06
Filing date: 2022-01-06
Publication date: 2022-07-29
Anticipated expiration: 2032-01-06

Abstract

The utility model discloses a power supply protection circuit of solid state hard drives, this power supply protection circuit of solid state hard drives includes: the device comprises a control circuit, a detection circuit, a switch circuit, a solid state disk access end, a power supply input end and a precision resistor; the power input end is electrically connected with the precision resistor, the switch circuit is connected in series between the precision resistor and the solid state disk access end, the detection circuit is connected with the precision resistor in parallel through a first detection end and a second detection end, a signal sending end of the detection circuit is electrically connected with a signal receiving end of the control circuit, and a control signal output end of the control circuit is electrically connected with a control signal input end of the switch circuit. The utility model discloses solid state hard drives's power supply protection circuit realizes monitoring solid state hard drives's power supply circuit's voltage and consumption to can in time protect solid state hard drives when the power supply is unusual. Furthermore, the utility model discloses still disclose a test equipment and test system.

Description

Power supply protection circuit, test equipment and test system of solid state disk

Technical Field

The utility model relates to a solid state hard drives test field, in particular to power supply protection circuit, test equipment and test system of solid state hard drives.

Background

A Solid State Drive (SSD), commonly called Solid State Disk, is a hard Disk made of a Solid State electronic memory chip array, and is composed of a control unit and a memory unit (FLASH chip, dram (dynamic Random Access memory) chip).

At present, in the production test process of the solid state disk, a power supply circuit is needed to supply power to the solid state disk. However, if the voltage and power consumption of the solid state disk fluctuate too much due to abnormal power supply of the power supply circuit, if emergency measures cannot be taken in time, the solid state disk may be burned out, and sometimes even the host of the solid state disk may be damaged.

The above is only for the purpose of assisting understanding of the technical solutions of the present invention, and does not represent an admission that the above is the prior art.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a solid state hard disk's power supply protection circuit aims at realizing monitoring solid state hard disk's power supply circuit's voltage and consumption to can in time protect solid state hard disk when the power supply is unusual.

In order to achieve the above object, the utility model provides a power supply protection circuit of solid state hard drives, this solid state hard drives's power supply protection circuit includes: the device comprises a control circuit, a detection circuit, a switch circuit, a solid state disk access end, a power supply input end and a precision resistor; the power supply input end is electrically connected with the precision resistor, the switch circuit is connected in series between the precision resistor and the solid state disk access end, the detection circuit is connected with the precision resistor in parallel through a first detection end and a second detection end, a signal sending end of the detection circuit is electrically connected with a signal receiving end of the control circuit, and a control signal output end of the control circuit is electrically connected with a control signal input end of the switch circuit;

the detection circuit is used for detecting current values at two ends of the precision resistor, calculating circuit voltage and circuit power consumption based on the current values, and sending the circuit voltage and the circuit power consumption to the control circuit through the signal sending end;

the control circuit is used for outputting a corresponding control signal to the switch circuit according to the circuit voltage and the circuit power consumption;

the switch circuit is used for controlling the connection or disconnection between the precision resistor and the access end of the solid state disk according to the control signal;

the solid state disk access end is used for accessing the solid state disk, and when the precision resistor and the solid state disk access end are switched on, the power input end supplies power to the solid state disk so as to test the solid state disk.

Optionally, the detection circuit includes a detection chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, and a second capacitor; the detection chip is provided with a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin; the signal transmitting end of the detection circuit comprises a first transmitting end and a second transmitting end; wherein,

the first pin, the second pin and the sixth pin are grounded;

the first resistor is connected between the third pin and the first sending end in series, and the second resistor is connected between the fourth pin and the second sending end in series; the third resistor is connected between the first transmitting end and a driving power supply in series, and the fourth resistor is connected between the second transmitting end and the driving power supply in series;

the fifth pin is electrically connected with a driving power supply, and the first capacitor is connected with the detection chip in parallel through the fifth pin and the sixth pin;

the fifth resistor is connected in series between the seventh pin and the second detection end, the sixth resistor is connected in series between the eighth pin and the first detection end, and the second capacitor is connected in parallel with the detection chip through the seventh pin and the eighth pin.

Optionally, the control circuit includes a single chip microcomputer and a reset module, and the single chip microcomputer has a ninth pin, a tenth pin, an eleventh pin, a twelfth pin, a thirteenth pin and a fourteenth pin; the signal receiving end comprises a first receiving end and a second receiving end; wherein,

the ninth pin is connected with the control signal output end and used for outputting the control signal with high level or outputting the control signal with low level;

the tenth pin is connected with the first receiving end, and the twelfth pin is connected with the second receiving end;

the twelfth pin is electrically connected with the reset module, and the reset module is used for controlling the single chip microcomputer to carry out power-on reset;

the thirteenth pin is grounded, and the fourteenth pin is electrically connected with a driving power supply.

Optionally, the reset module includes an eleventh resistor and a fourth capacitor, the eleventh resistor is connected in series between the twelfth pin and the driving power supply, and the fourth capacitor is connected in series between the twelfth pin and the ground.

Optionally, the number of the thirteenth pins is three, and the number of the fourteenth pins is three.

Optionally, the switch circuit includes a PMOS (P-Metal-Oxide-Semiconductor) transistor, an NMOS (N-Metal-Oxide-Semiconductor) transistor, a seventh resistor, an eighth resistor, a ninth resistor, and a third capacitor; wherein,

the source electrode of the PMOS tube is electrically connected with the precision resistor, and the drain electrode of the PMOS tube is electrically connected with the access end of the solid state disk;

the seventh resistor is connected between the source electrode of the PMOS tube and the grid electrode of the PMOS tube in series, the third capacitor is connected between the source electrode of the PMOS tube and the grid electrode of the PMOS tube in series, and the eighth resistor is connected between the grid electrode of the PMOS tube and the drain electrode of the NMOS tube in series;

the grid electrode of the NMOS tube is electrically connected with the control signal input end, the source electrode of the NMOS tube is grounded, and the ninth resistor is connected between the grid electrode of the NMOS tube and the source electrode of the NMOS tube in series.

Optionally, the power supply protection circuit of the solid state disk further includes a tenth resistor and a photodiode; wherein,

the tenth resistor is connected in series between the access end of the solid state disk and the anode of the photosensitive diode, the cathode of the photosensitive diode is grounded, and the photosensitive diode is used for displaying the working state of the access end of the solid state disk.

The utility model discloses further provide a test equipment, test equipment includes as above-mentioned solid state hard disk's power supply protection circuit.

The utility model discloses still further provide a test system, test system includes terminal equipment, and as above-mentioned test equipment, terminal equipment with test equipment communication connection.

The utility model discloses technical scheme's beneficial effect lies in: the power supply protection circuit of the solid state disk is used for monitoring the circuit voltage and the power consumption in the power supply process while supplying power for the production test of the solid state disk, so that whether the power supply is abnormal or not is judged, and the power supply to the solid state disk is cut off in time when the power supply is abnormal, so that the solid state disk is prevented from being burnt out, and a host for testing the solid state disk can be protected.

Drawings

Fig. 1 is a schematic structural diagram of an embodiment of a power supply protection circuit of a solid state disk according to the present invention;

fig. 2 is a schematic diagram of a detection circuit according to an embodiment of the power supply protection circuit of the solid-state hard disk of the present invention;

fig. 3 is a schematic structural diagram of a control circuit according to an embodiment of the power supply protection circuit of the solid-state hard disk of the present invention;

fig. 4 is a schematic structural diagram of a switch circuit according to an embodiment of the power supply protection circuit of the solid-state hard disk of the present invention;

fig. 5 is a schematic diagram of a photodiode circuit according to an embodiment of the power supply protection circuit of the solid-state hard disk of the present invention.

The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.

Detailed Description

In the following, the embodiments of the present invention will be described in detail with reference to the accompanying drawings, and obviously, the described embodiments are only some embodiments, not all embodiments, of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.

It will also be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit ly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.

The utility model provides a power supply protection circuit of solid state hard drives, referring to fig. 1, this power supply protection circuit of solid state hard drives includes: the device comprises a control circuit 10, a detection circuit 20, a switch circuit 30, a solid state disk access end 40, a power supply input end Ui and a precision resistor R0; the power input end Ui is electrically connected with the precision resistor R0, the switch circuit 30 is connected in series between the precision resistor R0 and the solid state disk access end 40, the detection circuit 20 is connected in parallel with the precision resistor R0 through a first detection end and a second detection end, a signal sending end of the detection circuit 20 is electrically connected with a signal receiving end of the control circuit 10, and a control signal output end of the control circuit 10 is electrically connected with a control signal input end of the switch circuit 30;

the detection circuit 20 is configured to detect a current value at two ends of the precision resistor R0, calculate a circuit voltage and a circuit power consumption based on the current value, and send the circuit voltage and the circuit power consumption to the control circuit 10 through the signal sending end;

the control circuit 10 is configured to output a corresponding control signal to the switch circuit 30 according to the circuit voltage and the circuit power consumption;

the switch circuit 30 is configured to control the precision resistor R0 and the solid state disk access end 40 to be turned on or off according to the control signal;

the solid state disk access end 40 is used for accessing a solid state disk, and when the precision resistor R0 is conducted with the solid state disk access end 40, the solid state disk is powered on through the power input end Ui, so that the solid state disk is tested.

In this embodiment, the control circuit 10 establishes a communication connection with an external terminal device. After the solid state disk is connected to the solid state disk access end 40, an external terminal device may send a test instruction to the control circuit 10, and after the control circuit 10 receives the test instruction, a high-level control signal is output to the control signal input end of the switch circuit 30 through the control signal output end. When the switch circuit 30 receives a high-level control signal through the control signal input terminal, the circuit between the precision resistor R0 and the solid state disk access terminal 40 is controlled to be turned on.

It should be noted that, when the power supply protection circuit of the solid state disk does not need to supply power to the solid state disk access terminal 40, the control circuit 10 outputs a low-level control signal to the control signal input terminal of the switch circuit 30 through the control signal output terminal, and when the switch circuit 30 receives the low-level control signal through the control signal input terminal, the circuit between the precision resistor R0 and the solid state disk access terminal 40 is controlled to be disconnected.

Optionally, after the circuit between the precision resistor R0 and the solid state disk access end 40 is turned on, the current provided by the power input end Ui flows through the precision resistor R0 and reaches the solid state disk access end 40 to supply power to the solid state disk accessed by the solid state disk access end 40, so that the power supply test can be performed on the solid state disk.

In the process of supplying power to the power supply protection circuit of the solid state disk, the detection circuit 20 detects the current values at the two ends of the precision resistor R0 through the first detection end and the second detection end connected to the two ends of the precision resistor R0, calculates the circuit voltage and the circuit power consumption based on the detected current values, and then sends the calculated circuit voltage and the calculated circuit power consumption to the control circuit 10 through the signal sending end by the detection circuit 20.

It should be noted that, a specific resistance value of the precision resistor R0 is preset and preset in the detection circuit 20, and the detection circuit 20 can calculate and obtain a corresponding circuit voltage and a corresponding circuit power consumption based on the current value detected at the two ends of the precision resistor R0 and the corresponding resistance value of the precision resistor R0.

Optionally, the resistance value of the precision resistor R0 may be 25m Ω ± 1%.

Optionally, the control circuit 10 may monitor the circuit voltage and the circuit power consumption in real time or at regular time through the detection circuit 20, wherein the value range of the regular time duration may be selected from 1ms to 10ms, and is preferably 5 ms.

Optionally, when the control circuit 10 receives the circuit voltage and the circuit power consumption sent by the detection circuit 20 through the signal receiving terminal, it detects whether the circuit voltage is greater than the preset voltage and whether the circuit power consumption is greater than the preset power consumption. The preset voltage and the preset power consumption are preset values and can be determined according to the maximum voltage and the maximum power consumption which can be borne by the tested solid state disk.

Optionally, for an NVMe (Non-Volatile memory express) solid state disk, the value of the preset voltage may be 3.3V ± 5%; for sata (serial Advanced Technology attachment) solid state disk, the value of the preset voltage may be 5V ± 5%; an optional value of the preset power consumption is 8000 mW.

Optionally, when the control circuit 10 detects that the circuit voltage is less than or equal to the preset voltage and detects that the circuit power consumption is less than or equal to the preset power consumption, it is determined that the current circuit is powered normally, and at this time, the control circuit 10 may not process the current circuit voltage or report only the current circuit voltage and the current circuit power consumption related information to the terminal device, and continue to control the power supply protection circuit to perform the power supply test on the solid state disk.

Optionally, when the control circuit 10 detects that the circuit voltage is greater than the preset voltage, and/or when the control circuit 10 detects that the circuit power consumption is greater than the preset power consumption, the control circuit outputs a low-level control signal to the control signal input end of the switch circuit 30 through the control signal output end. When the switch circuit 30 receives a low-level control signal through the control signal input end, the circuit between the precision resistor R0 and the solid state disk access end 40 is controlled to be switched off, so that the solid state disk access end is powered off, and further, when the circuit voltage and/or the circuit power consumption are abnormal, the power supply to the solid state disk is cut off, so that the solid state disk is protected.

Of course, when the control circuit 10 detects that the circuit voltage is greater than the preset voltage and/or when the control circuit 10 detects that the circuit power consumption is greater than the preset power consumption, it may also report the power supply abnormality information to the terminal device first, and when receiving a confirmation instruction fed back by the terminal device based on the power supply abnormality information, output a low-level control signal to the control signal input end of the switch circuit 30 through the control signal output end to cut off the power supply to the solid state disk.

Therefore, when the power supply protection circuit of the solid state disk supplies power for production test of the solid state disk, circuit voltage and power consumption are monitored in the power supply process, whether power supply is abnormal or not is judged, and power supply to the solid state disk is cut off in time when the power supply is abnormal, so that the solid state disk is prevented from being burnt out, and a host (such as terminal equipment) for testing the solid state disk can be protected.

In an embodiment, referring to fig. 2, based on the embodiment shown in fig. 1, the detection circuit 20 includes a detection chip 21, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, and a second capacitor C2; the detection chip 21 is provided with a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin; the signal transmitting end of the detection circuit 20 includes a first transmitting end and a second transmitting end; wherein,

the first pin, the second pin and the sixth pin are grounded;

the first resistor R1 is connected in series between the third pin and the first transmitting terminal, and the second resistor R2 is connected in series between the fourth pin and the second transmitting terminal; the third resistor R3 is connected in series between the first transmitting terminal and a driving power supply VCC, and the fourth resistor R4 is connected in series between the second transmitting terminal and the driving power supply VCC;

the fifth pin is electrically connected with a driving power supply VCC, and the first capacitor C1 is connected in parallel with the detection chip 21 through the fifth pin and the sixth pin;

the fifth resistor R5 is connected in series between the seventh pin and the second detection terminal, the sixth resistor R6 is connected in series between the eighth pin and the first detection terminal, and the second capacitor C2 is connected in parallel with the detection chip 21 through the seventh pin and the eighth pin.

The first pin of the detection chip 21 is a1 pin, the second pin is a0 pin, and both the first pin and the second pin are directly connected to the ground.

The third pin of the detection chip 21 is an SDA pin, and is configured to output a data signal to the first sending end; the fourth pin is an SCL pin and is used for outputting the clock signal to the second transmitting terminal. The third pin, the fourth pin, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 jointly form a communication module of the detection circuit 20, and power is supplied to the communication module through the driving power source VCC. Optionally, the first resistor R1 and the second resistor R2 are both bridge resistors (or called zero-ohm resistors), and the values of the third resistor R3 and the fourth resistor R4 may both be 4.7K Ω ± 5%.

The fifth pin of the detection chip 21 is a VS power pin, the sixth pin is a GND ground pin, the fifth pin is connected to the driving power VCC, the sixth pin is connected to the ground, and the first capacitor C1 is connected in parallel with the detection chip 21 through the fifth pin and the sixth pin, and forms a driving module of the detection chip 21 with the ground and the driving power VCC. Optionally, the value of the first capacitor C1 may be 0.1 μ F.

Optionally, the value of the regulated voltage provided by the driving power source VCC may be 3.3V.

Wherein, the seventh pin of the detection chip 21 is an IN-pin, and the eighth pin is an IN + pin; the fifth resistor R5 is connected in series between the seventh pin and the second detection end of the detection circuit 20, and the second detection end is electrically connected with the current outflow end of the precision resistor R0; the sixth resistor R6 is connected in series between the eighth pin and the first detection end of the detection circuit 20, and the first detection end is electrically connected with the current input end of the precision resistor R0; the second capacitor C2 is connected in parallel with the detection chip 21 through the seventh pin and the eighth pin.

Optionally, the fifth resistor R5 and the sixth resistor R6 are both connected across a resistor (or zero ohm resistor); the value of the second capacitance C2 may optionally be 0.1 muf.

Optionally, the seventh pin, the eighth pin, the fifth resistor R5, the sixth resistor R6, the second capacitor C2, the first detection end and the second detection end form a detection module of the detection circuit 20, the detection chip 21 can obtain a current value of the precision resistor R0 through the detection module, the detection chip 21 calculates a circuit voltage and a circuit power consumption based on the detected current value through operation inside the chip, and then the detection chip 21 further sends the circuit voltage and the circuit power consumption to the control circuit 10 through the communication module of the detection circuit 20.

Therefore, accurate detection of circuit voltage and circuit power consumption can be realized.

In an embodiment, referring to fig. 3, based on the embodiments shown in fig. 1 to 2, the control circuit 10 includes a single chip microcomputer 11 and a reset module, where the single chip microcomputer 11 has a ninth pin, a tenth pin, an eleventh pin, a twelfth pin, a thirteenth pin and a fourteenth pin; the signal receiving end comprises a first receiving end and a second receiving end; wherein,

the twelfth pin is electrically connected with the reset module, and the reset module is used for controlling the single chip microcomputer 11 to perform power-on reset;

the thirteenth pin is grounded, and the fourteenth pin is electrically connected with a driving power supply VCC.

Optionally, the ninth pin is a PB0 pin, and may be used to output a high-level control signal or output a low-level control signal.

Optionally, the tenth pin is a PB1 pin, the tenth pin is connected to the first receiving terminal, and the first receiving terminal is electrically connected to the first sending terminal of the detection circuit 20 and is configured to receive the data signal sent by the first sending terminal; the eleventh pin is a PB2 pin, the eleventh pin is connected to the second receiving terminal, and the second receiving terminal is electrically connected to the second transmitting terminal of the detection circuit 20 and is configured to receive the clock signal transmitted by the second transmitting terminal.

Optionally, the twelfth pin is an NRST pin and is electrically connected to the reset module. The reset module comprises an eleventh resistor R11 and a fourth capacitor C4, the eleventh resistor R11 is connected in series between the twelfth pin and the driving power VCC, and the fourth capacitor C4 is connected in series between the twelfth pin and the ground line. Optionally, the value of the eleventh resistor R11 may be 4.7K Ω ± 5%; the value of the fourth capacitance C4 may be 0.1 muf.

Optionally, the thirteenth pin is a VSS ground pin, and the thirteenth pin is connected to the ground; in some embodiments, the number of the thirteenth pins may be three (not shown), and all of the pins are connected to the ground.

Optionally, the fourteenth pin is a VDD power pin, and the fourteenth pin is connected to the driving power VCC; in some embodiments, the number of the fourteenth pins may be three (not shown), and all of the pins are connected to the ground.

After receiving the circuit voltage and the circuit power consumption sent by the detection module 20 through the tenth pin and the eleventh pin, the single chip 21 controls whether the ninth pin outputs a high-level control signal or a low-level control signal to the control signal output terminal based on the circuit voltage and the circuit power consumption.

In this way, the control circuit 10 can output a corresponding control signal to the switch circuit 30 according to the circuit voltage and the circuit power consumption.

Optionally, the control circuit 10 may further include a USB communication module (not shown in the figure), and the single chip 21 may include a first USB pin and a second USB pin (not shown in the figure), and is connected to the USB communication module through the first USB pin and the second USB pin, and then communicates with an external terminal device based on the USB communication module.

In this way, the control circuit 10 is communicatively connected to an external terminal device.

In an embodiment, referring to fig. 4, based on the above embodiments shown in fig. 1 to 3, the switch circuit 30 includes a PMOS transistor Q1, an NMOS transistor Q2, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a third capacitor C3; wherein,

the source S of the PMOS tube Q1 is electrically connected with the precision resistor R0, and the drain D of the PMOS tube Q1 is electrically connected with the solid state disk access end 40;

the seventh resistor R7 is connected in series between the source S of the PMOS transistor Q1 and the gate G of the PMOS transistor Q1, the third capacitor C3 is connected in series between the source S of the PMOS transistor Q1 and the gate G of the PMOS transistor Q1, and the eighth resistor R8 is connected in series between the gate G of the PMOS transistor Q1 and the drain D of the NMOS transistor Q2;

the gate G of the NMOS transistor Q2 is electrically connected to the control signal input terminal, the source S of the NMOS transistor Q2 is grounded, and the ninth resistor R9 is connected in series between the gate G of the NMOS transistor Q2 and the source S of the NMOS transistor Q2.

Optionally, values of the seventh resistor and the ninth resistor may be 10K Ω ± 1%; the value of the eighth resistor may be 1K Ω; the value of the third capacitance may be 0.1 muf.

Optionally, when the switch circuit 30 receives a high-level control signal through the control signal input terminal, the gate G of the NMOS transistor Q2 is influenced by the high-level control signal transmitted by the control signal input terminal, the level is pulled high, and then the source S and the drain D of the NMOS transistor Q2 are cut off, so that the gate G of the PMOS transistor Q1 may not be influenced by the ground line; at this time, the current flowing out of the precision resistor R0 can flow to the gate G of the PMOS transistor Q1 through the seventh resistor R7, so as to raise the level of the gate G of the PMOS transistor Q1, and make conduction between the source S and the drain D of the PMOS transistor Q1, so that the current flowing out of the precision resistor R0 can flow to the solid-state disk access terminal 40 through the source S and the drain D of the PMOS transistor Q1, i.e. make the circuit between the precision resistor R0 and the solid-state disk access terminal 40 conductive.

Optionally, when the switch circuit 30 receives a low-level control signal through the control signal input terminal, the gate G of the NMOS transistor Q2 is influenced by the low-level control signal transmitted by the control signal input terminal, and the level is pulled down, then the source S and the drain D of the NMOS transistor Q2 are turned on, and further the level of the gate G of the PMOS transistor Q1 is pulled down through the ground line, so that the source S and the drain D of the PMOS transistor Q1 are cut off, and at this time, the current flowing out from the precision resistor R0 cannot flow to the solid-state disk access terminal 40, that is, the circuit between the precision resistor R0 and the solid-state disk access terminal 40 is cut off.

In this way, the switching circuit 30 is implemented based on the PMOS transistor Q1 and the NMOS transistor Q2, and controls the circuit between the precision resistor R0 and the solid state disk access terminal 40 to be turned on or off according to the level of the control signal.

In an embodiment, referring to fig. 5, on the basis of the embodiments shown in fig. 1 to 4, the power supply protection circuit of the solid state disk further includes a tenth resistor R10 and a photodiode P; wherein,

the tenth resistor R10 is connected in series between the solid state disk access end 40 and the positive electrode of the photodiode P, the negative electrode of the photodiode P is grounded, and the photodiode P is used for displaying the working state of the solid state disk access end 40.

Optionally, 470 Ω ± 5% of the tenth resistor R10.

When the circuit between the precision resistor R0 and the solid-state disk access end 40 is turned on, a part of the current flowing from the precision resistor R0 to the solid-state disk access end 40 flows to the photodiode P through the tenth resistor R10, so that the photodiode P is powered on and emits light, and the current working state of the solid-state disk access end 40 is displayed to be normal; when the circuit between the precision resistor R0 and the solid state disk access end 40 is disconnected, when the solid state disk access end 40 loses power supply, the photodiode P also loses power supply, and cannot be powered on to emit light, and at this time, the unlighted state of the photodiode P represents that the current working state of the solid state disk access end 40 is abnormal in work or does not work.

Therefore, the working state of the solid state disk access end 40 can be conveniently known by a user through the photosensitive diode P.

The utility model discloses a further test equipment that provides includes above-mentioned embodiment solid state hard disk's power supply protection circuit, this solid state hard disk's power supply protection circuit's concrete structure refers to above-mentioned embodiment, because this test equipment has adopted all technical scheme of above-mentioned all embodiments, consequently has all technical effect that the technical scheme of above-mentioned embodiment brought at least, no longer gives unnecessary details one by one here.

The utility model discloses still further provide a test system, including terminal equipment, and as above-mentioned test equipment. The terminal equipment is in communication connection with the testing equipment.

Further, the terminal device may send a test instruction to the test device, and may receive information about the circuit voltage and the circuit power consumption sent by the test device.

What just go up be the utility model discloses a part or preferred embodiment, no matter be characters or the drawing can not consequently restrict the utility model discloses the scope of protection, all with the utility model discloses a holistic thought down, utilize the equivalent structure transform that the contents of the description and the drawing do, or direct/indirect application all includes in other relevant technical field the utility model discloses the within range of protection.

Claims

1. A power supply protection circuit of a solid state disk is characterized by comprising: the device comprises a control circuit, a detection circuit, a switch circuit, a solid state disk access end, a power supply input end and a precision resistor; the power supply input end is electrically connected with the precision resistor, the switch circuit is connected in series between the precision resistor and the solid state disk access end, the detection circuit is connected with the precision resistor in parallel through a first detection end and a second detection end, a signal sending end of the detection circuit is electrically connected with a signal receiving end of the control circuit, and a control signal output end of the control circuit is electrically connected with a control signal input end of the switch circuit;

2. The power supply protection circuit of the solid state disk of claim 1, wherein the detection circuit comprises a detection chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor and a second capacitor; the detection chip is provided with a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin; the signal transmitting end of the detection circuit comprises a first transmitting end and a second transmitting end; wherein,

the first pin, the second pin and the sixth pin are grounded;

3. The power supply protection circuit of the solid state disk according to claim 1, wherein the control circuit comprises a single chip microcomputer and a reset module, wherein the single chip microcomputer is provided with a ninth pin, a tenth pin, an eleventh pin, a twelfth pin, a thirteenth pin and a fourteenth pin; the signal receiving end comprises a first receiving end and a second receiving end; wherein,

the tenth pin is connected with the first receiving end, and the eleventh pin is connected with the second receiving end;

4. The power supply protection circuit of the solid state disk, according to claim 3, wherein the reset module comprises an eleventh resistor and a fourth capacitor, the eleventh resistor is connected in series between the twelfth pin and a driving power supply, and the fourth capacitor is connected in series between the twelfth pin and a ground line.

5. The power supply protection circuit of the solid state disk as claimed in claim 3, wherein the number of the thirteenth pin is three, and the number of the fourteenth pin is three.

6. The power supply protection circuit of the solid state disk of claim 1, wherein the switch circuit comprises a PMOS transistor, an NMOS transistor, a seventh resistor, an eighth resistor, a ninth resistor and a third capacitor; wherein,

7. The power supply protection circuit of the solid state disk of claim 1, further comprising a tenth resistor and a photodiode; wherein,

8. Test equipment, characterized in that it comprises a power supply protection circuit of a solid state disk according to any of claims 1 to 7.

9. A test system comprising a terminal device and a test device according to claim 8, the terminal device being communicatively connected to the test device.