CN217085172U - Partial discharge signal detection circuit - Google Patents

Abstract

The utility model relates to a partial discharge signal detection technical field discloses a partial discharge signal detection circuitry, including signal attenuation module, lower limit frequency selection module, upper limit frequency selection module, signal amplification module, power module and single chip microcomputer control module, power module does respectively signal attenuation module, signal amplification module, the power supply of single chip microcomputer control module, single chip microcomputer control module controls respectively signal attenuation module, lower limit frequency selection module, upper limit frequency selection module, signal attenuation module is used for receiving the partial discharge signal that high frequency sensor gathered, and will the partial discharge signal loops through lower limit frequency selection module, upper limit frequency selection module, signal amplification module and transmits the waveform for oscilloscope in order to show the discharge signal. The invention increases the dynamic range of the partial discharge signal by adjusting the sequence of the signal attenuation module and the signal amplification module.

Description

Partial discharge signal detection circuit

Technical Field

The utility model relates to a signal detection technical field is put in the office, concretely relates to partial discharge signal detection circuitry.

Background

At present, in production and life, the use of electric power is very common, the electric power brings convenience to people and correspondingly causes the safety problems of power supply and self power utilization of various electrical appliances and equipment, and in order to guarantee the safety of power supply and power utilization, the electric power equipment needs to be detected and positioned by receiving sensor signals.

The prior detection circuit has the following defects:

1. the bandwidth is fixed, and the energy of the detected partial discharge signal is limited to a certain extent, so that the sensitivity is not high, and the waveform information of the partial discharge signal cannot be well acquired;

2. the partial discharge signal is amplified and attenuated, so that the amplitude interval of the detected partial discharge signal has great limitation, and the dynamic range of signal input is not high.

SUMMERY OF THE UTILITY MODEL

The utility model provides a partial discharge signal detection circuitry has solved the problem that the aforesaid exists.

The utility model discloses a following technical scheme realizes:

a partial discharge signal detection circuit comprises a signal attenuation module, a lower limit frequency selection module, an upper limit frequency selection module, a signal amplification module, a power module and a single chip microcomputer control module, wherein the power module supplies power for the signal attenuation module, the signal amplification module and the single chip microcomputer control module respectively, the signal attenuation module is used for receiving a partial discharge signal acquired by a high-frequency sensor and transmitting the partial discharge signal to an oscilloscope through the lower limit frequency selection module, the upper limit frequency selection module and the signal amplification module in sequence to display the waveform of the discharge signal.

As optimization, the power supply module comprises an HFCT power supply module and a chip power supply module, wherein the input end of the HFCT power supply module is respectively connected with a power supply, and the output end of the HFCT power supply module is connected with the power supply input ends of the signal attenuation module and the signal amplification module; and the output end of the chip power supply module is connected with the power supply input end of the single-chip microcomputer control module.

Preferably, the chip power supply module comprises a voltage reduction circuit and a chip power supply circuit, the voltage reduction circuit comprises a second chip U2, a fifth capacitor C5, a sixth capacitor C6, a forty-first capacitor C41 and a forty-second capacitor C42, the forty-first capacitor C41 and the forty-second capacitor C42 are arranged IN parallel, one end of a parallel link of the forty-first capacitor C41 and the forty-second capacitor C42 is grounded, and the other end of the parallel link of the forty-first capacitor C41 and the forty-second capacitor C42 is respectively connected with a power supply and an IN pin of the second chip U2; the fifth capacitor C5 and the sixth capacitor C6 are arranged in parallel, one end of a parallel link of the fifth capacitor C5 and the sixth capacitor C6 is grounded, and the other end of the parallel link of the fifth capacitor C5 and the sixth capacitor C6 is connected with the OUT pin and the TH pin of the second chip U2 and the input end of the chip power supply circuit.

Preferably, the chip power supply circuit comprises a fourth chip U4, a thirteenth capacitor C13, a fourteenth capacitor C14, a seventeenth capacitor C17 and an eighteenth capacitor C18, the seventeenth capacitor C17 and the eighteenth capacitor C18 are arranged IN parallel, one end of a parallel link of the seventeenth capacitor C17 and the eighteenth capacitor C18 is grounded, and the other end of the parallel link of the seventeenth capacitor C17 and the eighteenth capacitor C18 is connected with an OUT pin of a second chip U2 and an IN pin of the fourth chip U4 respectively; the thirteenth capacitor C13 and the fourteenth capacitor C14 are arranged in parallel, one end of a parallel link of the thirteenth capacitor C13 and the fourteenth capacitor C14 is grounded, and the other end of the parallel link of the thirteenth capacitor C13 and the fourteenth capacitor C14 is connected with the OUT pin and the TH pin of the fourth chip U4 and the power supply input end of the single-chip microcomputer control module.

Preferably, the HFCT power supply module includes a fifth chip U5, a fifteenth capacitor C15, a sixteenth capacitor C16, a nineteenth capacitor C19 and a twentieth capacitor C20, the nineteenth capacitor C19 and the twentieth capacitor C20 are arranged IN parallel, one end of a parallel link of the nineteenth capacitor C19 and the twentieth capacitor C20 is grounded, and the other end of the parallel link of the nineteenth capacitor C19 and the twentieth capacitor C20 is connected to a power supply and an IN pin of the fifth chip U5 respectively; the fifteenth capacitor C15 and the sixteenth capacitor C16 are arranged in parallel, one end of a parallel link of the fifteenth capacitor C15 and the sixteenth capacitor C16 is grounded, and the other end of the parallel link of the fifteenth capacitor C15 and the sixteenth capacitor C16 is connected with the OUT pin and the TH pin of the fifth chip U5 and the power supply input ends of the signal attenuation module and the signal amplification module.

For optimization, the signal attenuation module comprises a signal chip LB1, a first resistor R1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a filter capacitor bank (C7-C10), a first diode D1 and a BNC connector for collecting a partial discharge signal of the high-frequency sensor, a VDD pin of the signal chip LB1 is connected with an OUT pin of the fifth chip U5 through the first resistor R1, and meanwhile, one end of the first resistor R1, which is far away from the VDD pin of the signal chip LB1, is grounded through the first capacitor C1; the pin RF1 of the signal chip LB1 is connected with the BNC connector through a third capacitor C3, the other end of the BNC connector is grounded, the BNC connector is connected in parallel with the first diode D1, the cathode of the first diode D1 is connected with the third capacitor C3, the anode of the first diode D1 is grounded, and the ACG pin group (ACG1-ACG7) of the signal chip LB1 is grounded through the filter capacitor group.

Preferably, the lower limit frequency selection module comprises a third chip U3 and a seventh chip U7, pins A and B of the third chip U3 are connected with the single-chip microcomputer control module, an RFC pin of the third chip U3 is connected with an RF2 pin of the signal chip LB1 through a second capacitor C2, an RF2 pin of the third chip U3 is connected with an RF1 pin of the seventh chip U7, an RF1 pin of the third chip U3 is connected with an RF2 pin of the seventh chip U7 through a thirty-first capacitor C31, a thirty-second capacitor C3 and a thirty-third capacitor C33 which are connected in series, and one end of the first inductor L1, one end of the second inductor L2, the other end of the first inductor L2 and the other end of the second inductor L1 are connected between the thirty-first capacitor C31 and the thirty-second capacitor C32 and between the thirty-second capacitor C3 and the thirty-third capacitor C33 respectively, pins A and B of the seventh chip U7 are connected with a singlechip control module, and RFC pins of the seventh chip U7 are connected with the input end of the upper limit frequency selection module.

Preferably, the upper limit frequency selection module includes an eighth chip U8 and a ninth chip U9, pins a and B of the eighth chip U8 are connected to the single-chip microcomputer control module, an RFC pin of the eighth chip U8 is connected to an RFC pin of the seventh chip U7, a pin RF1 of the eighth chip U8 is connected to a pin RF2 of the ninth chip U9, a pin RF2 of the eighth chip U8 is connected to a pin RF1 of the ninth chip U9 through a filter module LB2, a pin B and a pin a of the ninth chip U9 are connected to the single-chip microcomputer control module, and an RFC pin of the ninth chip U9 is connected to an input terminal of the signal amplification module.

Preferably, the signal amplification module comprises a tenth chip U10, a second resistor R2, a thirty-fourth capacitor C34, a thirty-fifth capacitor C35, a thirty-sixth capacitor C36, a thirty-seventh capacitor C37, a thirty-eighth capacitor C38 and a third inductor L3, the RFC pin of the ninth chip U9 is connected with the IN pin of the tenth chip U10 through a thirty-fourteenth capacitor C34, the OUT pin of the tenth chip U10 is connected with the output port through a thirty-eighteenth capacitor C38, the thirty-fifth capacitor C35, the thirty-sixth capacitor C36 and the thirty-seventh capacitor C37 are connected IN parallel, one end of a parallel link of the thirty-fifth capacitor C35, the thirty-sixth capacitor C36 and the thirty-seventh capacitor C8746 is grounded, one end of the parallel link of the thirty-fifth capacitor C35, the thirty-sixth capacitor C36 and the thirty-seventh capacitor C37 is connected with the tenth inductor L10 IN series, and the third inductor L6852 is connected with the OUT pin IN turn, and the other end of the parallel link of the thirty-fifth capacitor C35, the thirty-sixth capacitor C36 and the thirty-seventh capacitor C37 is connected with the OUT pin of the fifth chip U5.

Preferably, the single-chip microcomputer control module comprises a sixth positive chip U6A and a sixth secondary chip U6B, the VDD pin group of the sixth secondary chip U6B is connected with the OUT pin of the fourth chip U4, and the VDD pin group of the sixth secondary chip U6B is grounded through a parallel link of a second thirteenth capacitor C23, a twenty-fourth capacitor C24, a twenty-fifth capacitor C25 and a twenty-sixth capacitor C26; the VSS pin group of the sixth sub-chip U6B is grounded; the pins PA13 and PA14 of the sixth positive chip U6A are respectively connected to the port 2 and the port 3 of the terminal P5, the port 1 of the terminal P5 is connected to the OUT pin of the fourth chip U4, the pin PD0-OSC _ IN and the pin PD0-OSC _ OUT of the sixth positive chip U6A are connected to an oscillation circuit, and the pins PB12, PB13, PB14, PA8, PA9 and PA10 of the sixth positive chip U6A are respectively connected to the pin V6-V1 of the signal chip LB 1; a pin PB3 of the sixth positive chip U6A is connected to a pin a of the third chip U3 and a pin B of the seventh chip U7, respectively, and a pin PA11 of the sixth positive chip U6A is connected to a pin B of the third chip U3 and a pin a of the seventh chip U7, respectively; a PB5 pin of the sixth positive chip U6A is connected to the a pin of the eighth chip U8 and the B pin of the ninth chip U9, respectively, and a PB4 pin of the sixth positive chip U6A is connected to the B pin of the eighth chip U8 and the a pin of the ninth chip U9, respectively.

Compared with the prior art, the utility model, following advantage and beneficial effect have:

1. the dynamic range of the partial discharge signal is enlarged by adjusting the sequence of the signal attenuation module and the signal amplification module;

2. the purpose of frequency through selection is achieved by adding the lower limit frequency selection module and the upper limit frequency selection module, and the waveform information of the partial discharge signal can be better acquired.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

fig. 1 is a schematic block diagram of a partial discharge signal detection circuit according to the present invention;

FIG. 2 is a schematic circuit diagram of the HFCT power supply module of FIG. 1;

FIG. 3 is a schematic circuit diagram of the chip power module of FIG. 1;

FIG. 4 is a schematic circuit diagram of a portion of the single-chip microcomputer control module of FIG. 1;

FIG. 5 is a schematic circuit diagram of another portion of the single-chip microcomputer control module of FIG. 1;

FIG. 6 is a schematic circuit diagram of the signal attenuation module of FIG. 1;

FIG. 7 is a circuit diagram of a lower limit frequency selection module of FIG. 1;

FIG. 8 is a circuit diagram of the upper limit frequency selection module of FIG. 1;

fig. 9 is a circuit diagram of the signal amplifying module in fig. 1.

Detailed Description

To make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the following examples and drawings, and the exemplary embodiments and descriptions thereof of the present invention are only used for explaining the present invention, and are not intended as limitations of the present invention.

Example 1

As shown in fig. 1 to 9, a partial discharge signal detection circuit includes a signal attenuation module, a lower limit frequency selection module, an upper limit frequency selection module, a signal amplification module, a power supply module, and a single chip microcomputer control module, where the power supply module supplies power to the signal attenuation module, the signal amplification module, and the single chip microcomputer control module respectively controls the signal attenuation module, the lower limit frequency selection module, and the upper limit frequency selection module, and the signal attenuation module is configured to receive a partial discharge signal acquired by a high-frequency sensor, and transmit the partial discharge signal to an oscilloscope through the lower limit frequency selection module, the upper limit frequency selection module, and the signal amplification module in sequence to display a waveform of the discharge signal. During detection, the high-frequency sensor obtains waveform information of a partial discharge signal generated on the power equipment through a detection circuit.

In this embodiment, the power supply module includes an HFCT power supply module and a chip power supply module, an input end of the HFCT power supply module is connected to the power supply, and an output end of the HFCT power supply module is connected to power supply input ends of the signal attenuation module and the signal amplification module; and the output end of the chip power supply module is connected with the power supply input end of the single-chip microcomputer control module.

IN this embodiment, the chip power supply module includes a voltage reduction circuit and a chip power supply circuit, the voltage reduction circuit includes a second chip U2, a fifth capacitor C5, a sixth capacitor C6, a forty-first capacitor C41 and a forty-second capacitor C42, the forty-first capacitor C41 and the forty-second capacitor C42 are arranged IN parallel, one end of a parallel link of the forty-first capacitor C41 and the forty-second capacitor C42 is grounded, and the other end of the parallel link of the forty-first capacitor C41 and the forty-second capacitor C42 is connected to a power supply and an IN pin of the second chip U2 respectively; the fifth capacitor C5 and the sixth capacitor C6 are arranged in parallel, one end of a parallel link of the fifth capacitor C5 and the sixth capacitor C6 is grounded, and the other end of the parallel link of the fifth capacitor C5 and the sixth capacitor C6 is connected with the OUT pin and the TH pin of the second chip U2 and the input end of the chip power supply circuit.

IN this embodiment, the chip power supply circuit includes a fourth chip U4, a thirteenth capacitor C13, a fourteenth capacitor C14, a seventeenth capacitor C17 and an eighteenth capacitor C18, the seventeenth capacitor C17 and the eighteenth capacitor C18 are connected IN parallel, one end of a parallel link of the seventeenth capacitor C17 and the eighteenth capacitor C18 is grounded, and the other end of the parallel link of the seventeenth capacitor C17 and the eighteenth capacitor C18 is connected to an OUT pin of a second chip U2 and an IN pin of the fourth chip U4 respectively; the thirteenth capacitor C13 and the fourteenth capacitor C14 are arranged in parallel, one end of a parallel link of the thirteenth capacitor C13 and the fourteenth capacitor C14 is grounded, and the other end of the parallel link of the thirteenth capacitor C13 and the fourteenth capacitor C14 is connected with the OUT pin and the TH pin of the fourth chip U4 and the power supply input end of the single-chip microcomputer control module.

IN this embodiment, the HFCT power supply module includes a fifth chip U5, a fifteenth capacitor C15, a sixteenth capacitor C16, a nineteenth capacitor C19, and a twentieth capacitor C20, where the nineteenth capacitor C19 and the twentieth capacitor C20 are connected IN parallel, one end of a parallel link of the nineteenth capacitor C19 and the twentieth capacitor C20 is grounded, and the other end of the parallel link of the nineteenth capacitor C19 and the twentieth capacitor C20 is connected to a power supply and an IN pin of the fifth chip U5 respectively; the fifteenth capacitor C15 and the sixteenth capacitor C16 are arranged in parallel, one end of a parallel link of the fifteenth capacitor C15 and the sixteenth capacitor C16 is grounded, and the other end of the parallel link of the fifteenth capacitor C15 and the sixteenth capacitor C16 is connected with the OUT pin and the TH pin of the fifth chip U5 and the power supply input ends of the signal attenuation module and the signal amplification module.

The models of the second chip U2 and the fifth chip U5 are: AMS1117-5, and the fourth chip U4 is AMS 1117-3.3. The voltage reduction circuit in the chip power supply module reduces the voltage of 8.4V output by the battery or the charger to 5V, and then the voltage is reduced to 3.3V through the chip power supply circuit, so that power is supplied to a chip (the model is STM32F103C8T6) of the single chip microcomputer control module. The HFCT power supply module reduces the voltage of 8.4V output by the battery or the charger to 5V, and supplies power to a signal chip LB1 (model HMC472ALP4E) of the signal attenuation module and a tenth chip U10 (model MAR-8ASM +) of the signal amplification module.

In this embodiment, the signal attenuation module includes a signal chip LB1, a first resistor R1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a filter capacitor bank (C7-C10), a first diode D1, and a BNC connector for collecting a partial discharge signal of the high-frequency sensor, a VDD pin of the signal chip LB1 is connected to an OUT pin of the fifth chip U5 through the first resistor R1, and meanwhile, one end of the first resistor R1, which is far away from the VDD pin of the signal chip LB1, is grounded through the first capacitor C1; the pin RF1 of the signal chip LB1 is connected with the BNC connector through a third capacitor C3, the other end of the BNC connector is grounded, the BNC connector is connected in parallel with the first diode D1, the cathode of the first diode D1 is connected with the third capacitor C3, the anode of the first diode D1 is grounded, and the ACG pin group (ACG1-ACG7) of the signal chip LB1 is grounded through the filter capacitor group. And adjusting the attenuation gain through the singlechip control module so as to change the amplitude of the partial discharge signal.

In this embodiment, the lower limit frequency selection module includes a third chip U3 and a seventh chip U7, pins a and B of the third chip U3 are connected to the single chip control module, an RFC pin of the third chip U3 is connected to a RF2 pin of the signal chip LB1 through a second capacitor C2, a RF2 pin of the third chip U3 is connected to a RF1 pin of the seventh chip U7, a RF1 pin of the third chip U3 is connected to a RF2 pin of the seventh chip U7 through a thirty-first capacitor C31, a thirty-second capacitor C3, and a thirty-third capacitor C33 connected in series, and a space between the thirty-first capacitor C31 and the thirty-second capacitor C32 and a space between the thirty-second capacitor C3 and the thirty-third capacitor C33 is respectively connected to one end of the first inductor L1, one end of the second inductor L2, the other end of the first inductor L1, and the other end of the second inductor L2, pins A and B of the seventh chip U7 are connected with a singlechip control module, and RFC pins of the seventh chip U7 are connected with the input end of the upper limit frequency selection module. The switch chips (the third chip U3 and the seventh chip U7) are controlled by the singlechip control module to select whether the lower limit cut-off frequency of the partial discharge signal is straight-through or 3 MHz. When the direct connection is selected, partial discharge signals of all frequencies can pass through; when 3MHz is selected, partial discharge signals below this frequency cannot pass.

In this embodiment, the upper limit frequency selection module includes an eighth chip U8 and a ninth chip U9, pins a and B of the eighth chip U8 are connected to the single chip microcomputer control module, an RFC pin of the eighth chip U8 is connected to an RFC pin of the seventh chip U7, an RF1 pin of the eighth chip U8 is connected to an RF2 pin of the ninth chip U9, an RF2 pin of the eighth chip U8 is connected to an RF1 pin of the ninth chip U9 through a filter module LB2, pins B and a of the ninth chip U9 are connected to the single chip microcomputer control module, and an RFC pin of the ninth chip U9 is connected to an input terminal of the signal amplification module. The switch chips (the eighth chip U8 and the ninth chip U9) are controlled by the singlechip control module to select whether the upper limit cut-off frequency of the partial discharge signal is through or 100 MHz. When the direct connection is selected, partial discharge signals of all frequencies can pass through; when 100MHz is selected, partial discharge signals above this frequency cannot pass.

IN this embodiment, the signal amplifying module includes a tenth chip U10, a second resistor R2, a thirty-fourth capacitor C34, a thirty-fifth capacitor C35, a thirty-sixth capacitor C36, a thirty-seventh capacitor C37, a thirty-eighth capacitor C38, and a third inductor L3, an RFC pin of the ninth chip U9 is connected to an IN pin of the tenth chip U10 through a thirty-fourteenth capacitor C34, an OUT pin of the tenth chip U10 is connected to an output port through a thirty-eighteenth capacitor C38, the thirty-fifth capacitor C35, a thirty-sixth capacitor C36, and a thirty-seventh capacitor C37 are connected IN parallel, and one end of a parallel link of the thirty-fifth capacitor C35, the thirty-sixth capacitor C36, and the thirty-seventh capacitor C37 is grounded, one end of the thirty-fifth capacitor C35, the thirty-sixth capacitor C36, and the other end of the thirty-seventh capacitor C37 is connected to the tenth inductor L2 and the third chip 6474 sequentially through the resistor R6852 and the OUT pin, and the other end of the parallel link of the thirty-fifth capacitor C35, the thirty-sixth capacitor C36 and the thirty-seventh capacitor C37 is connected with the OUT pin of the fifth chip U5. The output port is a port connected with the oscilloscope. Because the amplitude of the partial discharge signal is small, the waveform of the partial discharge signal is inconvenient to observe, and the signal is amplified through the signal amplification module.

In this embodiment, the single chip microcomputer control module includes a sixth positive chip U6A and a sixth secondary chip U6B, the VDD pin group of the sixth secondary chip U6B is connected to the OUT pin of the fourth chip U4, and the VDD pin group of the sixth secondary chip U6B is grounded through a parallel link of a second thirteenth capacitor C23, a twenty-fourth capacitor C24, a twenty-fifth capacitor C25 and a twenty-sixth capacitor C26; the VSS pin group of the sixth sub-chip U6B is grounded; the pins PA13 and PA14 of the sixth positive chip U6A are respectively connected to the port 2 and the port 3 of the terminal P5, the port 1 of the terminal P5 is connected to the OUT pin of the fourth chip U4, the pin PD0-OSC _ IN and the pin PD0-OSC _ OUT of the sixth positive chip U6A are connected to an oscillation circuit, and the pins PB12, PB13, PB14, PA8, PA9 and PA10 of the sixth positive chip U6A are respectively connected to the pin V6-V1 of the signal chip LB 1; a pin PB3 of the sixth positive chip U6A is connected to a pin a of the third chip U3 and a pin B of the seventh chip U7, respectively, and a pin PA11 of the sixth positive chip U6A is connected to a pin B of the third chip U3 and a pin a of the seventh chip U7, respectively; a PB5 pin of the sixth positive chip U6A is connected to the a pin of the eighth chip U8 and the B pin of the ninth chip U9, respectively, and a PB4 pin of the sixth positive chip U6A is connected to the B pin of the eighth chip U8 and the a pin of the ninth chip U9, respectively; the PD0-OSC _ IN pin and the PD1-OSC _ OUT pin of the sixth chip U6A are connected with an oscillating circuit, and the oscillating circuit is composed of capacitors C21 and C22 and a crystal oscillator Y1. The function button on the positioning instrument is connected with the input control end of the sixth calibration chip U6A. The operation button can control the gain of the attenuation chip and attenuate the partial discharge signal; the channel selection of the switch chip can be controlled.

In this embodiment, the sensor is a high-frequency sensor, a partial discharge signal acquired by the high-frequency sensor is transmitted to the signal attenuation module through the RF coaxial connector, the attenuated signal is sequentially transmitted to the lower limit frequency selection module and the upper limit frequency selection module to screen the partial discharge signal, the partial discharge signal is amplified, and finally the amplified partial discharge signal is transmitted to the oscilloscope through the RF coaxial connector, so that a waveform of the partial discharge signal is obtained.

The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only the embodiments of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. A partial discharge signal detection circuit is characterized by comprising a signal attenuation module, a lower limit frequency selection module, an upper limit frequency selection module, a signal amplification module, a power supply module and a single chip microcomputer control module, wherein the power supply module is used for supplying power to the signal attenuation module, the signal amplification module and the single chip microcomputer control module respectively, the single chip microcomputer control module is used for controlling the signal attenuation module, the lower limit frequency selection module and the upper limit frequency selection module respectively, the signal attenuation module is used for receiving a partial discharge signal acquired by a high-frequency sensor and transmitting the partial discharge signal to an oscilloscope to display the waveform of the discharge signal through the lower limit frequency selection module, the upper limit frequency selection module and the signal amplification module in sequence.

2. The partial discharge signal detection circuit of claim 1, wherein the power supply module comprises an HFCT power supply module and a chip power supply module, the input terminals of the HFCT power supply module are respectively connected to a power supply, and the output terminal of the HFCT power supply module is connected to the power supply input terminals of the signal attenuation module and the signal amplification module; and the output end of the chip power supply module is connected with the power supply input end of the single-chip microcomputer control module.

3. The partial discharge signal detection circuit of claim 2, wherein the chip power supply module comprises a voltage reduction circuit and a chip power supply circuit, the voltage reduction circuit comprises a second chip U2, a fifth capacitor C5, a sixth capacitor C6, a forty-first capacitor C41 and a forty-second capacitor C42, the forty-first capacitor C41 and the forty-second capacitor C42 are arranged IN parallel, one end of a parallel link of the forty-first capacitor C41 and the forty-second capacitor C42 is grounded, and the other end of the parallel link of the forty-first capacitor C41 and the forty-second capacitor C42 is connected with a power supply and an IN pin of the second chip U2 respectively; the fifth capacitor C5 and the sixth capacitor C6 are arranged in parallel, one end of a parallel link of the fifth capacitor C5 and the sixth capacitor C6 is grounded, and the other end of the parallel link of the fifth capacitor C5 and the sixth capacitor C6 is connected with the OUT pin and the TH pin of the second chip U2 and the input end of the chip power supply circuit.

4. The partial discharge signal detection circuit of claim 3, wherein the chip power supply circuit comprises a fourth chip U4, a thirteenth capacitor C13, a fourteenth capacitor C14, a seventeenth capacitor C17 and an eighteenth capacitor C18, the seventeenth capacitor C17 and the eighteenth capacitor C18 are arranged IN parallel, one end of a parallel link of the seventeenth capacitor C17 and the eighteenth capacitor C18 is grounded, and the other end of the parallel link of the seventeenth capacitor C17 and the eighteenth capacitor C18 is connected with an OUT pin of a second chip U2 and an IN pin of the fourth chip U4 respectively; the thirteenth capacitor C13 and the fourteenth capacitor C14 are arranged in parallel, one end of a parallel link of the thirteenth capacitor C13 and the fourteenth capacitor C14 is grounded, and the other end of the parallel link of the thirteenth capacitor C13 and the fourteenth capacitor C14 is connected with the OUT pin and the TH pin of the fourth chip U4 and the power supply input end of the single-chip microcomputer control module.

5. The partial discharge signal detection circuit of claim 4, wherein the HFCT power supply module comprises a fifth chip U5, a fifteenth capacitor C15, a sixteenth capacitor C16, a nineteenth capacitor C19 and a twentieth capacitor C20, the nineteenth capacitor C19 and the twentieth capacitor C20 are arranged IN parallel, one end of a parallel link of the nineteenth capacitor C19 and the twentieth capacitor C20 is grounded, and the other end of the parallel link of the nineteenth capacitor C19 and the twentieth capacitor C20 is connected to a power supply and an IN pin of the fifth chip U5 respectively; the fifteenth capacitor C15 and the sixteenth capacitor C16 are arranged in parallel, one end of a parallel link of the fifteenth capacitor C15 and the sixteenth capacitor C16 is grounded, and the other end of the parallel link of the fifteenth capacitor C15 and the sixteenth capacitor C16 is connected with the OUT pin and the TH pin of the fifth chip U5 and the power supply input ends of the signal attenuation module and the signal amplification module.

6. The partial discharge signal detection circuit of claim 5, wherein the signal attenuation module comprises a signal chip LB1, a first resistor R1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a filter capacitor group, a first diode D1 and a BNC connector for collecting a partial discharge signal of the high-frequency sensor, the VDD pin of the signal chip LB1 is connected with the OUT pin of the fifth chip U5 through the first resistor R1, and meanwhile, one end of the first resistor R1, which is far away from the VDD pin of the signal chip LB1, is grounded through a first capacitor C1; the RF1 pin of the signal chip LB1 is connected with the BNC connector through a third capacitor C3, the other end of the BNC connector is grounded, the BNC connector is connected in parallel with the first diode D1, the cathode of the first diode D1 is connected with the third capacitor C3, the anode of the first diode D1 is grounded, and the ACG pin group of the signal chip LB1 is grounded through the filter capacitor group.

7. The partial discharge signal detection circuit according to claim 6, wherein the lower limit frequency selection module comprises a third chip U3 and a seventh chip U7, the A pin and the B pin of the third chip U3 are connected to the SCM control module, the RFC pin of the third chip U3 is connected to the RF2 pin of the LB1 through a second capacitor C2, the RF2 pin of the third chip U3 is connected to the RF1 pin of the seventh chip U7, the RF1 pin of the third chip U3 is connected to the RF2 pin of the seventh chip U7 through a thirty-first capacitor C31, a thirty-second capacitor C3 and a thirty-third capacitor C33 connected in series, and one end of the first inductor L38742 and one end of the second inductor L1 are connected between the thirty-second capacitor C3 and the thirty-third capacitor C936 respectively, the other end of the first inductor L1 and the other end of the second inductor L2 are grounded, the pin A and the pin B of the seventh chip U7 are connected with the single-chip microcomputer control module, and the RFC pin of the seventh chip U7 is connected with the input end of the upper limit frequency selection module.

8. The partial discharge signal detection circuit of claim 7, wherein the upper limit frequency selection module includes an eighth chip U8 and a ninth chip U9, pins a and B of the eighth chip U8 are connected to the single chip microcomputer control module, an RFC pin of the eighth chip U8 is connected to an RFC pin of the seventh chip U7, a pin RF1 of the eighth chip U8 is connected to a pin RF2 of the ninth chip U9, a pin RF2 of the eighth chip U8 is connected to a pin RF1 of the ninth chip U9 through a filter module LB2, a pin B and a pin a of the ninth chip U9 are connected to the single chip microcomputer control module, and the RFC pin of the ninth chip U9 is connected to an input terminal of the signal amplification module.

9. The partial discharge signal detection circuit of claim 8, wherein the signal amplification module comprises a tenth chip U10, a second resistor R2, a thirty-fourth capacitor C34, a thirty-fifth capacitor C35, a thirty-sixth capacitor C36, a thirty-seventh capacitor C37, a thirty-eighth capacitor C38 and a third inductor L3, the RFC pin of the ninth chip U9 is connected with the IN pin of the tenth chip U10 through a thirty-fourth capacitor C34, the OUT pin of the tenth chip U10 is connected with the output port through a thirty-eighth capacitor C38, the thirty-fifth capacitor C35, the thirty-sixth capacitor C36 and the thirty-seventh capacitor C37 are arranged IN parallel, one end of the parallel link of the thirty-fifth capacitor C35, the thirty-sixth capacitor C36 and the thirty-seventh capacitor C37 is grounded, and the other end of the parallel link of the thirty-fifth capacitor C35, the thirty-sixth capacitor C36 and the thirty-seventh capacitor C37 is connected with the third inductor L2 IN parallel and the other end of the parallel link of the thirty-fifth capacitor C3 is connected with the third inductor L2 IN series sequentially The OUT pin of the tenth chip U10 is connected, and the other end of the parallel link of the thirty-fifth capacitor C35, the thirty-sixth capacitor C36 and the thirty-seventh capacitor C37 is connected with the OUT pin of the fifth chip U5.

10. The partial discharge signal detection circuit of claim 9, wherein the single chip microcomputer control module comprises a sixth positive chip U6A and a sixth subordinate chip U6B, the VDD pin group of the sixth subordinate chip U6B is connected to the OUT pin of the fourth chip U4, and the VDD pin group of the sixth subordinate chip U6B is grounded through a parallel link of a second thirteenth capacitor C23, a twenty-fourth capacitor C24, a twenty-fifth capacitor C25 and a twenty-sixth capacitor C26; the VSS pin group of the sixth sub-chip U6B is grounded; the pins PA13 and PA14 of the sixth positive chip U6A are respectively connected to the port 2 and the port 3 of the terminal P5, the port 1 of the terminal P5 is connected to the OUT pin of the fourth chip U4, the pin PD0-OSC _ IN and the pin PD0-OSC _ OUT of the sixth positive chip U6A are connected to an oscillation circuit, and the pins PB12, PB13, PB14, PA8, PA9 and PA10 of the sixth positive chip U6A are respectively connected to the pin V6-V1 of the signal chip LB 1; a pin PB3 of the sixth positive chip U6A is connected to a pin a of the third chip U3 and a pin B of the seventh chip U7, respectively, and a pin PA11 of the sixth positive chip U6A is connected to a pin B of the third chip U3 and a pin a of the seventh chip U7, respectively; a PB5 pin of the sixth positive chip U6A is connected to the a pin of the eighth chip U8 and the B pin of the ninth chip U9, respectively, and a PB4 pin of the sixth positive chip U6A is connected to the B pin of the eighth chip U8 and the a pin of the ninth chip U9, respectively.

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