CN217063861U

CN217063861U - Pixel circuit and image sensor

Info

Publication number: CN217063861U
Application number: CN202122690804.7U
Authority: CN
Inventors: 侯金剑; 任冠京; 莫要武; 汪小勇; 杨光
Original assignee: SmartSens Technology Shanghai Co Ltd
Current assignee: SmartSens Technology Shanghai Co Ltd
Priority date: 2021-11-04
Filing date: 2021-11-04
Publication date: 2022-07-26
Anticipated expiration: 2031-11-04

Abstract

The application belongs to the technical field of semiconductor devices, and relates to a pixel circuit and an image sensor, which comprise: at least two pixel units arranged in an array, each pixel unit comprising at least two pixels; the transfer transistors of two pixels in at least one pixel unit are connected to the corresponding first group of transfer control lines, and the transfer transistors in the other pixel units are connected to the corresponding second group of transfer control lines. The pixel circuit and the image sensor provided by the application can control the phase focusing density of the image sensor by controlling the time sequence of the first group of transmission control lines and the second group of transmission control lines, the structure of the pixel does not need to be changed, and the pixel circuit and the image sensor are simple in structure and good in optical performance.

Description

Pixel circuit and image sensor

Technical Field

The present disclosure relates to semiconductor devices, and particularly to a pixel circuit and an image sensor.

Background

With the development of the technology of the image sensor, the application field of the image sensor is also more and more extensive, for example, the image sensor can be applied to the fields of medical radiation imaging, industrial flaw detection, security inspection and the like.

The current image sensor cannot adjust the density of phase focusing, so that the density of phase focusing cannot be switched according to a specific scene.

In response to the above problems, those skilled in the art have sought solutions.

The foregoing description is provided for general background information and does not necessarily constitute prior art.

Disclosure of Invention

The present application is directed to provide a pixel circuit and an image sensor to switch a phase focusing density and ensure optical performance, in order to overcome the above-mentioned drawbacks of the prior art.

The application is realized as follows:

the present application provides a pixel circuit, including: the pixel structure comprises at least two pixel units which are arranged in an array.

Each pixel unit includes at least two pixels. Wherein each pixel includes a photoelectric conversion element for generating a charge in response to incident light, and a transfer transistor; the transfer transistor is coupled between the photoelectric conversion element and a floating diffusion node, and is used for transferring charges accumulated by the photoelectric conversion element during exposure to the floating diffusion node according to a transfer control signal. The transmission transistors of at least two pixels in at least one pixel unit are connected with a corresponding first group of transmission control lines, the first group of transmission control lines comprises at least one transmission control line, and one pixel corresponds to one transmission control line; the transfer transistors in the other pixels are connected to the corresponding second group of transfer control lines.

Optionally, at least two pixels in the same pixel unit share one on-chip lens, and at least two pixels sharing the same on-chip lens are correspondingly connected with the first group of control lines.

Optionally, all of the pixels in the same pixel unit share one on-chip lens.

Alternatively, of the pixels of the pixel unit connected to the corresponding first group of transfer control lines, the remaining pixels other than the pixels connected to the first group of transfer control lines are connected to the second group of transfer control lines.

Optionally, the number of the transmission control lines in the first group of transmission control lines is greater than the number of the pixels in the corresponding pixel unit.

Optionally, the number of the transmission control lines in the first group of transmission control lines is less than or equal to the number of the pixels in the corresponding pixel unit.

Optionally, each row of pixel cells is provided with a corresponding first set of transmission control lines and a corresponding second set of transmission control lines.

Optionally, when the phase focusing density is one hundred percent, the timings of the transmission control signals received by the first group of transmission control lines and the second group of transmission control lines are the same; when the phase focusing density is not one hundred percent, the time sequence of the transmission control signals received by the first group of transmission control lines and the second group of transmission control lines is different.

Optionally, each pixel unit includes four pixels, and the first group of transmission control lines corresponding to each row of pixel units includes two transmission control lines; wherein the transmission transistors of at least two pixels in the pixel unit connected to the first group of transmission control lines are correspondingly connected to at least two transmission control lines in the corresponding first group of transmission control lines, respectively.

Optionally, when the phase focusing density is not one hundred percent, times that the first sub-transmission control line and the second sub-transmission control line in the first group of transmission control lines receive the transmission control signal of the effective level are staggered with each other to obtain left-right phase information and/or up-down phase information, and four transmission control lines in the second group of transmission control lines receive the transmission control signal of the effective level to obtain image information; the first sub-transmission control line comprises a transmission control line correspondingly connected with a first pixel in the four pixels, and the second sub-transmission control line comprises a transmission control line correspondingly connected with a pixel which is adjacent to the first pixel up and down or left and right in the four pixels.

Optionally, in the same row of pixel units, two pixel units connected to the first group of transmission control lines are separated by at least one pixel unit.

Optionally, the pixel units in the nth row in the pixel circuit are circularly arranged according to the first green and blue color filters, and the pixel units in the (n + 1) th row are circularly arranged according to the red and second green color filters; or each pixel unit group comprises four pixel units which are arranged in an array, and the four pixel units in each pixel unit group sequentially correspond to the first green color filter, the second green color filter, the first blue color filter, the second green color filter and the red color filter in the clockwise direction respectively; and the pixel units connected with the first group of transmission control lines are correspondingly arranged at the positions corresponding to the first green or the second green.

Optionally, in the same row of pixel units, at least one pixel unit is arranged between two pixel units connected with the first group of transmission control lines; and/or, in the same column of pixel units, at least one pixel unit is arranged between two pixel units connected with the first group of transmission control lines.

Optionally, the pixel circuit further comprises:

a reset transistor coupled between a first voltage source and the floating diffusion node; and/or the presence of a gas in the gas,

the amplification output unit is coupled to the floating diffusion node and used for amplifying and outputting a voltage signal of the floating diffusion node; and/or the presence of a gas in the atmosphere,

a dual conversion gain control unit coupled between the reset transistor and the floating diffusion node for implementing gain control; and/or the presence of a gas in the atmosphere,

and the row selection transistor is coupled between the output end of the amplification output unit and a column output line, and the grid electrode of the row selection transistor receives a row selection control signal and is used for outputting a voltage signal of the floating diffusion node.

Optionally, each pixel unit includes four pixels, four pixels in the same pixel unit share one on-chip lens, and the first group of transmission control lines each includes at least two transmission control lines;

wherein, in the pixel unit connected with the first group of transmission control lines, at least two pixels are connected with at least two transmission control lines in the first group of transmission control lines.

The present application also provides an image sensor including the pixel circuit as described above.

The application provides a pixel circuit and an image sensor, wherein the transmission transistors of at least two pixels in at least one pixel unit are connected with a corresponding first group of transmission control lines, and the transmission transistors in other pixels are connected with a corresponding second group of transmission control lines. Therefore, the pixel circuit and the image sensor provided by the application can control the phase focusing density of the image sensor by controlling the time sequence of the first group of transmission control lines and the second group of transmission control lines, the structure of the pixel is not required to be changed, the structure is simple, and the optical performance is good.

In order to make the aforementioned and other objects, features and advantages of the present application comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a pixel unit in a pixel circuit according to an embodiment of the present disclosure;

FIG. 3 is a circuit diagram of a pixel unit in a pixel circuit according to an embodiment of the present application;

FIG. 4 is a timing diagram of a pixel unit in a pixel circuit according to an embodiment of the present application;

FIG. 5 is a timing diagram of another pixel unit in a pixel circuit according to an embodiment of the present application;

FIG. 6 is a schematic diagram illustrating an effect of an image sensor according to an embodiment of the present application in achieving a phase-focusing mode with a top-bottom phase information density of 100%;

FIG. 7 is a schematic diagram illustrating an effect of an image sensor according to an embodiment of the present application in achieving a phase focusing mode with 100% of upper, lower, left and right phase information density;

FIG. 8a is a timing diagram of the image sensor according to the first embodiment of the present application when the up-down phase information density is 6%;

FIG. 8b is a timing diagram of the image sensor according to the first embodiment of the present application when the up-down phase information density is 6%;

FIG. 8c is a timing diagram of the image sensor according to the first embodiment of the present application when the up-down phase information density is 6%;

FIG. 9 is a timing diagram of an image sensor according to an embodiment of the present application when the left and right phase information density is 6%;

fig. 10 is an image sensor according to an embodiment of the present application.

Fig. 11 is a schematic structural diagram of a pixel circuit according to the second embodiment of the present application;

fig. 12 is a schematic structural diagram of a pixel unit in a pixel circuit according to the second embodiment of the present application;

FIG. 13 is a circuit diagram of a pixel unit in a pixel circuit according to the second embodiment of the present application;

FIG. 14a is a schematic diagram illustrating an effect of an image sensor according to the second embodiment of the present invention in a phase focusing mode with a left-right phase information density of 100%;

FIG. 14b is a timing diagram of the image sensor according to the second embodiment of the present invention when the left and right phase information density is 100%;

FIG. 15a is a schematic diagram illustrating an effect of the image sensor according to the second embodiment of the present application in achieving a phase-focusing mode with a top-bottom phase information density of 100%;

FIG. 15b is a timing diagram of the image sensor according to the second embodiment of the present application when the up-down phase information density is 100%;

FIG. 16 is a schematic diagram illustrating an effect of an image sensor according to the second embodiment of the present application in implementing a left-right, up-down phase information density 100% phase focusing mode;

FIG. 17a is a layout of pixels of an image sensor according to an embodiment of the present application, when the left and right phase information density is 3%;

FIG. 17b is a timing diagram of the image sensor according to the second embodiment of the present application when the left and right phase information density is 3%;

18a and 18b are two timing diagrams of the image sensor according to the second embodiment of the present application when the left and right phase information density is 6%;

FIG. 19a is a timing diagram of an image sensor according to the second embodiment of the present application when the left and right phase information density is 3%;

FIG. 19b is a layout of pixels of an image sensor according to the second embodiment of the present application, when the left and right phase information density is 3%;

fig. 20 shows an image sensor according to the second embodiment of the present application.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.

Example 1

The application provides a pixel circuit, pixel circuit includes that at least two are the pixel cell of array arrangement, and every pixel cell includes:

at least two pixels each including a photoelectric conversion element for accumulating charges generated by a photoelectric effect in response to incident light, including but not limited to a photodiode PD; the transfer transistor is coupled between the photoelectric conversion element and a floating diffusion node and used for transferring charges accumulated by the photoelectric conversion element in an exposure process to the floating diffusion node according to a transfer control signal;

a reset transistor coupled between a first voltage source and the floating diffusion node, for resetting a voltage of the floating diffusion node according to a reset control signal;

the amplifying output unit is coupled to the floating diffusion node and used for amplifying and outputting the voltage signal of the floating diffusion node;

the transmission transistor of at least one pixel in at least one pixel unit is connected with the corresponding first group of transmission control lines to obtain focusing information required by phase focusing. In one embodiment, the transfer transistors of at least two of the pixels in at least one of the pixel cells are connected to a corresponding first set of transfer control lines. Wherein the first group of the transfer control lines includes at least one transfer control line, one of the pixels corresponding to one of the transfer control lines; the transfer transistors in the other pixel cells are connected to a corresponding second group of transfer control lines, the first group of transfer control lines being different from the second group of transfer control lines.

According to one embodiment of the present application, the amplified output unit includes a source follower transistor having a gate coupled to the floating diffusion node, a drain coupled to a second voltage source, and a source as an output coupled to the row select transistor.

The first voltage source and the second voltage source may be the same voltage source, so that the reset transistor and the source follower transistor are simultaneously connected to the same voltage source, of course, the first voltage source and the second voltage source may also be different voltage sources, and the reset transistor and the source follower transistor are respectively connected.

In one embodiment, the pixel circuit further includes a dual conversion gain control unit coupled between the reset transistor and the floating diffusion node for implementing gain control.

In a specific embodiment, the dual conversion gain control unit comprises a dual conversion gain control transistor and a dual conversion gain capacitor, the dual conversion gain control transistor is coupled between the reset transistor and the floating diffusion node; a first terminal of the dual conversion gain capacitor is coupled at a node between the dual conversion gain transistor and the reset transistor, and a second terminal of the dual conversion gain capacitor is connected to a specified level or ground.

In one embodiment, the pixel circuit further includes a row selection transistor coupled between the output terminal of the amplification output unit and the column output line, and a gate of the row selection transistor receives a row selection control signal for outputting a voltage signal of the floating diffusion node.

In one embodiment, at least two pixels in the same pixel unit share one on-chip lens. For example, four pixels may share one on-chip lens, and in a further embodiment, one pixel unit includes four pixels, and four pixels in the same pixel unit share the same on-chip lens. In other embodiments, one pixel unit may include two pixels, and two pixels in the same pixel unit share the same on-chip lens. In one embodiment, all of the pixels in the same pixel cell share one of the on-chip lenses.

In one embodiment, the number of the transmission control lines in the first group of transmission control lines corresponding to each row of pixel units is equal to the number of the pixels in each pixel unit, and the pixels are in one-to-one correspondence with the transmission control lines. Of course, in other embodiments, the number of the transmission control lines in the first group of transmission control lines may be smaller than the number of the pixels in each corresponding pixel unit, for example, the pixel unit includes four pixels, two of the pixels are connected to the first group of transmission control lines, and the other two are connected to the second group of transmission control lines.

In one embodiment, when the phase focusing density is one hundred percent, the timing of the transmission control signals received by the first group of transmission control lines and the second group of transmission control lines is the same; when the phase focusing density is not one hundred percent, the time sequence of the transmission control signals received by the first group of transmission control lines and the second group of transmission control lines is different.

In one embodiment, each pixel unit comprises four pixels, four pixels in the same pixel unit share one on-chip lens, and the first group of transmission control lines corresponding to each row of pixel units comprises four transmission control lines; the transmission transistors of the four pixels in at least one pixel unit are correspondingly connected with the four transmission control lines in the corresponding first group of transmission control lines respectively.

In an embodiment, when the phase focusing density is not one hundred percent, the times at which the first sub-transmission control line and the second sub-transmission control line in the first group of transmission control lines receive the transmission control signal at the effective level are staggered with each other to obtain the left-right phase information and/or the up-down phase information, and the four transmission control lines in the second group of transmission control lines receive the transmission control signal at the effective level at the same time to obtain the image information. The first sub-transmission control lines comprise two transmission control lines correspondingly connected with a first pair of adjacent pixels in the four pixels, and the second sub-transmission control lines comprise two transmission control lines correspondingly connected with a second pair of pixels except the first pair of pixels in the four pixels.

The pixel circuit provided by the application comprises at least two pixel units, and all pixels in each pixel unit share the reset transistor, the amplification output unit and the row selection transistor, so that the area of a chip can be saved, and the miniaturization of a device is facilitated. And the transmission transistors of at least two pixels in at least one pixel unit are connected with the first group of transmission control lines, and the transmission transistors in other pixels are connected with the corresponding second group of transmission control lines, so that the phase focusing density of the image sensor can be controlled by controlling the first group of transmission control lines and the second group of transmission control lines, the structure of the pixels is not required to be changed, and the structure is simple and the optical performance is good. In addition, at least two pixels in the same pixel unit share one on-chip lens, so that mutual influence among the pixels can be avoided, the number of the transmission control lines in the first group of transmission control lines corresponding to each row of pixel units can be set to be equal to the number of the pixels in each pixel unit, the left and right phase information and/or the up and down phase information can be acquired while different phase focusing densities can be switched, and the flexibility can be further improved.

The embodiments of the present application will be described in detail with reference to specific examples.

Referring to fig. 1, fig. 2 and fig. 3, as shown in fig. 1, a pixel circuit provided in the present embodiment includes N pixel units (fig. 1 shows 8 × 4 pixel units, but the present application is not limited thereto), where the N pixel units are arranged in an array, where N is a positive integer and N ≧ 2.

As shown in fig. 2, in an embodiment, each pixel unit includes 4 pixels (i, ii, iii, and iv), but the present application is not limited thereto. In one embodiment, 4 pixels (i), ii, iii, and iv) correspond to one on-chip lens, and in other embodiments, 2 pixels may share one on-chip lens.

The transmission transistors of at least two pixels in at least one pixel unit are connected with a first group of transmission control lines, and the transmission transistors of other pixels are connected with a second group of transmission control lines; the first group of transmission control lines includes at least one transmission control line, one pixel corresponds to one transmission control line, and one pixel may be connected to only one transmission control line, and one transmission control line may be connected to pixels in different pixel units.

In one embodiment, each row of the pixel cells is provided with a corresponding first set of the transfer control lines and a corresponding second set of the transfer control lines. In an alternative example, for the pixel unit connected to the first group of transfer control lines, some of the pixels are connected to the first group of transfer control lines, and the remaining pixels are connected to the second group of transfer control lines.

In this embodiment, each pixel unit includes four pixels, and each row of pixel units corresponds to eight transmission control lines. Taking the pixel cells in the nth row as an example, the four transmission control lines txap < n >, (txbp < n >, (txcp < n >) and (txdp < n > (constituting the first group of transmission control lines) correspond to the four transmission control lines txa < n >, (txb < n >, (txc) n > -and (txd) n > (constituting the second group of transmission control lines).

The first pixel (I) of all the pixel units in the nth row is connected with a first transmission control line txa & lt n & gt in a second group of transmission control lines, the second pixel (II) is connected with a second transmission control line txb & lt n & gt in the second group of transmission control lines, the third pixel (III) is connected with a third transmission control line txc & lt n & gt in the second group of transmission lines, and the fourth pixel (III) is connected with a fourth transmission control line txd & lt n & gt in the second group of transmission lines.

As shown in fig. 1, in this embodiment, the transfer transistors of the four pixels of the pixel units in the 2 nd column and the 6 th column in the n +2 th row are respectively connected to the first group of transfer control lines txap, txbp, txcp, and txdp, and the transfer transistors of the remaining pixel units are all connected to the second group of transfer control lines txa, txb, txc, and txd.

In one embodiment, the number of the transmission control lines in the first group of transmission control lines is less than or equal to the number of the pixels in the corresponding pixel unit. In other embodiments, the number of the transmission control lines in the first group of transmission control lines is greater than the number of the pixels in the corresponding pixel units, in this case, the number of the transmission control lines in the pixel units in the same row may be greater than the number of the pixels in the pixel units, and in this case, the pixels in the pixel units may be connected to the corresponding transmission control lines according to an actual design.

As an example, for the pixel units connected to the first group of transmission control lines in the same row, the first group of transmission control lines may be divided into several sections, where among the different sections, the control lines may be completely different, or may have an overlap between two of them; one pixel unit selects one of the portions to be connected.

For example, four pixels in the first pixel unit are connected to four of the six transmission control lines, and four pixels in the second pixel unit in the same pixel unit row are selected to be connected to the remaining two control lines, or four pixels in the second pixel unit are connected to the remaining two control lines, and two pixels are selected to be connected to the pixels from the four control lines connected to the first pixel unit. Based on the above manner, flexible design for the relatively focused pixel can be realized.

As shown in fig. 3, four pixels in each pixel unit include photoelectric conversion elements PD1, PD2, PD3, PD4, and transfer transistors TXA, TXB, TXC, and TXD. Among them, the photoelectric conversion elements PD1, PD2, PD3, PD4 function to accumulate charges generated by a photoelectric effect in response to incident light. The transfer transistors TXA, TXB, TXC, TXD are coupled between the corresponding photoelectric conversion elements PD1, PD2, PD3, PD4 and the floating diffusion node FD for transferring charges accumulated during the exposure process of the corresponding photoelectric conversion elements PD1, PD2, PD3, PD4 to the floating diffusion node FD according to transfer control signals TXA, TXB, TXC, tcd or txap, txbp, txcp, txdp, respectively. Here, four pixels in one pixel unit may share one floating diffusion node FD, or two adjacent pixels may share one floating diffusion node, and the formed nodes FD1 and FD2 are simultaneously electrically connected to the gate of the source follower transistor SF, and signals corresponding to the two nodes FD1 and FD2 are simultaneously output based on an output circuit. Specifically, the anode terminals of the photoelectric conversion elements PD1, PD2, PD3, PD4 are connected to the ground terminal, and the cathode terminals thereof are coupled to the floating diffusion node FD through the corresponding transfer transistors TXA, TXB, TXC, TXD.

The reset transistor RST is coupled between a first voltage source Vrab and the floating diffusive node FD for resetting a voltage of the floating diffusive node FD according to a reset control signal RST.

The amplifying output unit is coupled to the floating diffusive node FD and is configured to amplify and output a voltage signal of the floating diffusive node FD. Specifically, in the present embodiment, the amplified output unit includes a first source follower transistor SF having a gate coupled to the floating diffusion node FD, a drain coupled to a second voltage source Vrsf, and a source as an output terminal coupled to the row select transistor. Of course, the present embodiment only schematically shows one implementation manner of the amplifying output unit, and those skilled in the art should realize that the amplifying output unit may also use other amplifying devices with different gains to replace the source follower transistor SF, for example, a two-stage or multi-stage amplifier may be used to replace the source follower transistor SF in the present embodiment, and these variations are also within the protection scope of the present application.

In one embodiment, the pixel circuit further includes a dual conversion gain control unit coupled between the reset transistor RST and the floating diffusion node FD for implementing gain control. In one embodiment, the dual conversion gain control unit includes a dual conversion gain control transistor DCG coupled between the reset transistor RST and the floating diffusion node FD, and a dual conversion gain capacitor Cdcg. A first terminal of the dual conversion gain capacitor Cdcg is coupled to a node between the dual conversion gain transistor DCG and the reset transistor RST, and a second terminal of the dual conversion gain capacitor Cdcg is connected to a specified level.

As a preferred embodiment, the pixel circuit provided by this embodiment further includes a row selection transistor RS, which is coupled between the output terminal (e.g. the source of the first source follower transistor SF) of the amplified output unit and the column output line, and the gate of which receives a control signal RS for outputting the voltage signal of the floating diffusion node FD in the rolling exposure mode. Of course, the row select transistor RS is present as a preferred embodiment, and the implementation of the present application does not necessarily require the row select transistor RS.

The reset transistor RST, the transfer transistor TX, the first source follower transistor SF, the row selection transistor RS, and the dual conversion gain control transistor DCG are all NMOS, N is 8 × 4, the four pixels of the 2 nd and 6 th columns of pixel units in the N +2 th row are connected to the transfer transistors of the first to fourth transfer control lines txap, the second to third transfer control lines txbp, the third to fourth transfer control lines txcp, and the fourth to fourth transfer control lines txdp in the first group of transfer control lines, the transfer transistors of the remaining pixel units in the N +2 th row are connected to the first to fourth transfer control lines txa, the second to third transfer control lines txb, the third to fourth to transfer control lines txc, and the fourth to transfer control lines txd in the second group of transfer control lines, and the control timing sequence is as shown in fig. 4 to illustrate the working principle of the image sensor of the present embodiment, and the specific working process is:

1. at time t0, the row selection signal rs is set to high level, and the quantization circuit prepares to quantize data of a corresponding row;

2. at the time t1, the reset signal rst and the dual conversion gain selection signal dcg are set to be low level, and a corresponding image reset signal is obtained; of course, in other embodiments, the dual conversion gain selection signal dcg can also be asserted high;

3. at time t2, setting the first transmission control lines txap and TXA in the first group of transmission control lines and the second transmission control lines txbp and TXB in the first group of transmission control lines and the second group of transmission control lines to high level, turning on the first pixels (i) and the second pixels (TXA and TXB) in all the pixel units in the (n + 2) th row, and starting to transmit the upper phase information in all the pixel units in the (n + 2) th row;

4. at the time of t3, setting the first transmission control lines txap and txa in the first group of transmission control lines and the second transmission control lines txbp and txb in the first group of transmission control lines and the second group of transmission control lines to be low levels, finishing transmitting the upper phase information by all the pixel units in the (n + 2) th row, and quantizing by a quantization circuit to obtain quantized upper phase information VTPD;

5. at time t4, setting the third transmission control lines txcp and TXC in the first group of transmission control lines and the second group of transmission control lines and the fourth transmission control lines txdp and TXD in the first group of transmission control lines and the second group of transmission control lines to high level, turning on the third pixels TXC and TXD in all the pixel units in the (n + 2) th row and the fourth pixels, and starting to transmit the lower phase information by all the pixel units in the (n + 2) th row;

6. at time t5, setting the third transmission control lines txcp and txc in the first group of transmission control lines and the second group of transmission control lines and the fourth transmission control lines txdp and txd in the first group of transmission control lines and the second group of transmission control lines to be low levels, finishing transmitting the lower phase information by all the pixel units in the (n + 2) th row, and if the two phase information are summed at the floating diffusion node fd, quantizing again through the quantization circuit to obtain the image information Vsum;

7. at time t6, the reset signal rst and the dual conversion gain selection signal dcg are set to high level, and the floating diffusion node fd is reset;

8. at time t7, the row selection signal rs is set to low level, and the current row quantization is finished.

Through digital operation, the lower phase information VLPD ═ Vsum-VTPD can be obtained, so that the pixel units in the n +2 th row in the image sensor of this embodiment can realize the up-down phase focusing mode.

In other embodiments, a reset operation in which the reset signal rst or the dual conversion gain selection signal dcg is set high and then set low may be added between time t3 and time t4, so that the quantization circuit quantizes the lower phase information alone instead of the summed Vsum at time t 5. In addition, it should be noted that, based on the above control principle, other focusing data for phase focusing may also be acquired based on txap, txbp, txcp, and txdp; in addition, the corresponding relation of txap, txbp, txcp, txdp and txa, txb, txc, tcd in time sequence can be designed according to actual requirements.

Fig. 5 is a timing diagram of another pixel unit in the pixel circuit according to an embodiment of the present disclosure. Referring to fig. 5, 2 and 3, at time t2, the first transmission control lines txap and txa of the first and second sets of transmission control lines corresponding to a pixel unit, and third transmission control lines txcp and txc in the first and second groups of transmission control lines are both set to high level, so that the transmission transistors TXA and TXC in the first pixel and the third pixel in the pixel unit are turned on, so that the pixel unit starts to transmit right phase information, and by connecting the first transmission control lines txap, txa in the first and second groups of transmission control lines corresponding to this pixel cell at time t3, and third transmission control lines txcp and txc in the first group of transmission control lines and the second group of transmission control lines are set to be low levels, the pixel unit finishes transmitting right phase information, and the quantized right phase information can be obtained through quantization by a quantization circuit. The principle of obtaining quantized left phase information is similar to that of obtaining right phase information, and is not described herein again.

Fig. 6 is a schematic diagram illustrating an effect of the image sensor according to an embodiment of the present application in achieving a phase-focus mode with a top-bottom phase information density of 100%. If each pixel unit in the pixel array is quantized by the timing control as shown in fig. 4 to obtain the upper phase information 10a and the lower phase information 10b, a phase focusing mode with 100% density of upper and lower phase information can be realized, and fig. 6 only shows the 4 × 4 array, but the present application is not limited thereto. The upper phase information 10a and the lower phase information 10b are used for phase focusing. In one embodiment, the effect shown in FIG. 6 may be achieved based on the readout timing in FIG. 4.

Fig. 7 is a schematic diagram illustrating an effect of the image sensor according to an embodiment of the present application in achieving a phase focusing mode with a 100% density of upper, lower, left, and right phase information. As shown in fig. 7, the 4x2 pixel array of the 4x4 pixel array obtains corresponding image information 10, right phase information 10a and left phase information 10b by the fig. 4 timing control quantization, and the 4x2 pixel array obtains corresponding image information 20, right phase information 20a and left phase information 20b by the fig. 6 timing control quantization, wherein the image information is used for imaging, and the left and right phase information and the up and down phase information are used for phase focusing. As shown in fig. 7, in the phase focusing mode with a density of 100%, the pixel units for acquiring the left and right phase information and the up and down phase information are 50% respectively in the image sensor in one embodiment. In other embodiments, the occupation ratio and the acquisition position of the pixel units for acquiring the left-right phase information, and the up-down phase information in the entire pixel array may be configured according to the phase focusing requirement. In one embodiment, the effect shown in fig. 7 can be achieved based on the read out timing combination of fig. 4 and 5.

Fig. 8a is a timing diagram of the image sensor according to the first embodiment of the present application when the up-down phase information density is 6%. Referring to fig. 1 and fig. 8a, as shown in fig. 1, in the 4 × 8 pixel array, the transmission transistors of the four pixels in the 2 nd column and the 6 th column in the n +2 th row are respectively connected to the first group of transmission control lines txap, txbp, txcp, txdp, and the transmission transistors of the remaining pixel units are connected to the second group of transmission control lines txa, txb, txc, txd.

Therefore, under the control of the timing signal shown in fig. 8a, two pixel units of the 2 nd column and the 6 th column in the n +2 th row are used to obtain the upper and lower phase information, and the remaining pixel units are all used to obtain the normal image information. Therefore, under the control of the timing signals shown in fig. 8a, the present application can realize a density of 2/4 × 8, i.e., equal to about 6% phase focusing mode.

In other embodiments, the timing sequences of the first transmission control line txap and the third transmission control line txcp in the first group of transmission control lines txap, txbp, txcp, txdp may also be set to be the same, and the timing sequences of the second transmission control line txbp and the fourth transmission control line txdp may also be set to be the same, so as to implement a phase focusing mode in which the left and right phase information density is 6%.

Fig. 8b is a timing diagram of the image sensor according to the first embodiment of the present application when the up-down phase information density is 6%. Referring to fig. 1 and 8b, as shown in fig. 1, in the 4 × 8 pixel array, the transfer transistors of the four pixels in the 2 nd column and the 6 th column of the pixel unit in the n +2 th row are respectively connected to the first group of transfer control lines txap, txbp, txcp and txdp, and the transfer transistors of the remaining pixel units are connected to the second group of transfer control lines txa, txb, txc and txd.

Therefore, under the control of the timing signal shown in fig. 8b, two pixel units, i.e., the pixel units in the 2 nd column and the 6 th column in the n +2 th row, can be used for acquiring the vertical phase information, and the remaining pixel units can be used for acquiring the vertical phase information under the control of the timing signal shown in fig. 8b, but the readout circuit (not shown) may not use the remaining pixel units for phase focusing. Therefore, under the control of the timing signals shown in fig. 8b, the present application can also realize a density of 2/4 × 8, i.e. equal to about 6% phase focusing mode.

Fig. 8c is a timing diagram of the image sensor according to the first embodiment of the present application when the up-down phase information density is 6%. Fig. 8c is substantially the same as the timing signals shown in fig. 8a, except that the first group of transmission control lines txap, txbp coincides with the time when the second group of transmission control lines txa, txb, txc, txd are high. Under the control of the timing signals shown in fig. 8c, the present application can also realize a density of 2/4 × 8, i.e. approximately equal to 6% phase focusing mode, and for the specific principle, please refer to the description corresponding to fig. 8a, which is not repeated herein.

It should be noted that phase focusing at any other ratio can also be realized by the readout manner of 8a to 8c, for example, 3% phase focusing can be realized based on the design of the first group of transmission control lines and the corresponding pixel units.

Fig. 9 is a timing diagram of an image sensor according to an embodiment of the present application when the left and right phase information density is 6%. Referring to fig. 1 and 9, as shown in fig. 1, in the 4 × 8 pixel array, the transfer transistors of the four pixels in the 2 nd column and the 6 th column of the pixel unit in the n +2 th row are respectively connected to the first group of transfer control lines txap, txbp, txcp and txdp, and the transfer transistors of the remaining pixel units are connected to the second group of transfer control lines txa, txb, txc and txd.

Therefore, under the control of the timing signals shown in fig. 9, the two pixel units of the 2 nd column and the 6 th column in the n +2 th row are used for acquiring the left and right phase information at different times. In addition, the remaining pixel units are used to acquire normal image information. For example, the left side of the vertical dividing line in fig. 9 indicates that data of 0 th to 7 th rows in the pixel array are read, and half of the phase information is acquired by the pixel cells connected to the first group of transfer control lines in the 8 rows of data; meanwhile, the right side of the vertical dividing line represents the data of 8 th to 15 th rows in the read pixel array, and the pixel units connected with the first group of transmission control lines in the 8 th row of data acquire the other half of phase information; so that completed phase information can be obtained based on the pixel cells of the 0 th to 15 th rows connected to the first group of transfer control lines. Therefore, under the control of the timing signals as shown in fig. 9, the present application can realize a phase focus mode in which the left and right phase information density is 6%. It should be noted that, in this mode, the pixel unit corresponding to one connection with the first group of transmission control lines is only used for acquiring half of the phase information, so that the density of the data corresponding to the acquired focusing information is reduced by half for the total pixel unit for acquiring the phase focusing information, and of course, other density variations designed by those skilled in the art according to actual requirements may be adopted.

In other embodiments, the timing sequences of the first and second transmission control lines txap, txbp in the first group of transmission control lines txap, txbp, txcp, txdp may be set to be the same, and the timing sequences of the third and fourth transmission control lines txcp, txdp may be set to be the same, so as to implement a phase focusing mode in which the up-down phase information density is 6%.

Example 2

at least two pixels each including a photoelectric conversion element for accumulating charges generated by a photoelectric effect in response to incident light, including but not limited to a photodiode PD; the transfer transistor is coupled between the photoelectric conversion element and a floating diffusion node, and is used for transferring charges accumulated by the photoelectric conversion element in an exposure process to the floating diffusion node according to a transfer control signal;

a reset transistor coupled between a first voltage source and the floating diffusion node for resetting a voltage of the floating diffusion node according to a reset control signal;

the amplifying output unit is coupled to the floating diffusion node and used for amplifying and outputting a voltage signal of the floating diffusion node;

wherein the transfer transistors of two pixels in at least one pixel unit are connected to a first group of transfer control lines, and the transfer transistors in the other pixels are connected to a corresponding second group of transfer control lines. The first set of transmission control lines is different from the second set of transmission control lines.

According to one embodiment of the present application, the amplified output unit includes a first source follower transistor having a gate coupled to the floating diffusion node, a drain coupled to a second voltage source, and a source as an output coupled to the row select transistor. The first voltage source and the second voltage source may be the same voltage source, so that the reset transistor and the source follower transistor are simultaneously connected to the same voltage source, and of course, the first voltage source and the second voltage source may also be different voltage sources, and the reset transistor and the source follower transistor are respectively connected.

In two embodiments, the pixel circuit further comprises a dual conversion gain control unit coupled between the reset transistor and the floating diffusion node for implementing gain control.

In one embodiment, the dual conversion gain control unit comprises a dual conversion gain control transistor and a dual conversion gain capacitor, wherein the dual conversion gain control transistor is coupled between the reset transistor and the floating diffusion node; a first terminal of the dual conversion gain capacitor is coupled at a node between the dual conversion gain transistor and the reset transistor, and a second terminal of the dual conversion gain capacitor is connected to a specified level or ground.

In two embodiments, the pixel circuit further includes a row selection transistor coupled between the output terminal of the amplification output unit and the column output line, and a gate of the row selection transistor receives a row selection control signal for outputting a voltage signal of the floating diffusion node.

In both embodiments, at least two pixels in the same pixel unit share one on-chip lens. Further, two of the pixel pairs sharing the same on-chip lens are connected to the first set of control lines.

In a second embodiment, when the phase focusing density is one hundred percent, the timings of the transmission control signals received by the first group of transmission control lines and the second group of transmission control lines are the same; when the phase focusing density is not one hundred percent, the time sequence of the transmission control signals received by the first group of transmission control lines and the second group of transmission control lines is different.

In the second embodiment, each pixel unit comprises four pixels, the four pixels in the same pixel unit share one on-chip lens, and the first group of transmission control lines corresponding to each row of pixel units comprises two transmission control lines; the transmission transistors of two pixels in at least one pixel unit are correspondingly connected with two transmission control lines in the corresponding first group of transmission control lines respectively.

The pixel circuit provided by the application comprises at least two pixel units, and all pixels in each pixel unit share the reset transistor, the amplification output unit and the row selection transistor, so that the area of a chip can be saved, and the miniaturization of a device is facilitated. And the transmission transistors of two pixels in at least one pixel unit are connected with the first group of transmission control lines, and the transmission transistors in other pixels are connected with the corresponding second group of transmission control lines, so that the phase focusing density of the image sensor can be controlled by controlling the time sequence of the first group of transmission control lines and the second group of transmission control lines, the structure of the pixels does not need to be changed, and the structure is simple and the optical performance is good. In addition, at least two pixels in the same pixel unit share one on-chip lens, so that mutual influence among the pixels can be avoided.

Referring to fig. 11, 12 and 13, as shown in fig. 11, a pixel circuit provided in the embodiment of the present application includes N pixel units (fig. 11 shows 16 × 16 pixel units, each pixel unit includes four pixels, and each pixel unit shares one on-chip lens, but the present application is not limited thereto, where only the on-chip lens of the pixel unit corresponding to the first group of transmission control lines is shown in the figure, and the on-chip lenses of the other pixel units are not shown), and the N pixel units are arranged in an array, where N is a positive integer and N ≧ 2.

As shown in fig. 12, in the two embodiments, each pixel unit includes 4 pixels (r, g, and r), but the present application is not limited thereto. In the two embodiments, 4 pixels (i), ii, iii, and iv) correspond to one on-chip lens, and in other embodiments, 2 pixels may share one on-chip lens.

The transmission transistors of two pixels in at least one pixel unit are connected with a first group of transmission control lines, and the transmission transistors of other pixels are connected with a second group of transmission control lines; the first group of transmission control lines includes at least two transmission control lines, one pixel corresponds to one transmission control line, and one pixel may be connected to only one transmission control line, and one transmission control line may be connected to pixels in different pixel units.

In this embodiment, each pixel unit includes four pixels, and each row of pixel units corresponds to six transmission control lines. Taking the pixel cell in row 0 as an example, the corresponding transmission control lines are txap < 0 >, (txa < 0 >, (txb < 0 >, (txc < 0 >, (txd < 0 >) and (txcp < 0 >); taking the pixel cells in row 4 as an example, the corresponding transmission control lines are txbp < 0 >, txa < 4 >, txb < 4 >, txc < 4 >, txd < 4 > and txdp < 0 > in the order of arrangement.

In one embodiment, the first pixel (r) of all the pixel units in the nth row (n is an odd number and n > is 1) is connected to the first transmission control line txa < n > in the second group of transmission control lines, the second pixel (r) is connected to the second transmission control line txb < n > in the second group of transmission control lines, the third pixel (r) is connected to the third transmission control line txc < n > in the second group of transmission control lines, and the fourth pixel (r) is connected to the fourth transmission control line txd < n > in the second group of transmission control lines.

As shown in fig. 11, in the present embodiment, the transmission transistors of the first pixel (i) and the third pixel (iii) in the pixel units of the 5 th column and the 13 th column in the 0 th row and the 2 nd row and the pixel units of the 1 st column and the 9 th column in the 12 th row and the 14 th row are respectively connected to the first group of transmission control lines txap and txcp, and the transmission transistors of the remaining pixel units in the corresponding row are all connected to the second group of transmission control lines txa, txb, txc and txd;

the transfer transistors of the pixel units of the 1 st column and the 9 th column in the 4 th row and the 6 th row and the pixel units of the 5 th column and the 13 th column in the 8 th row and the 10 th row are connected to the first group of transfer control lines txbp and txdp, respectively, and the transfer transistors of the remaining pixel units in the corresponding row are connected to the second group of transfer control lines txa, txb, txc and txd, respectively.

In other embodiments, the number and the position of the pixel units connected to the first group of transmission control lines may be adjusted as needed, and the application is not limited thereto.

In this embodiment, the first pixel (r) and the third pixel (c) of the pixel unit in the a-th column in the pixel unit in the (n-1) th row (n is an odd number, and n > -1) are connected to the corresponding first group of transmission control lines, and the second pixel (r) and the fourth pixel (r) of the pixel unit in the a-3 th column in the pixel unit in the (n + 1) th row are connected to the corresponding first group of transmission control lines. In other embodiments, the number and the position of the pixel units connected to the first group of transmission control lines may be adjusted as needed, and the application is not limited thereto. Wherein N is less than or equal to N, and a is greater than or equal to 3.

Each pixel includes a photoelectric conversion element and a transfer transistor, and as shown in fig. 13, four pixels in each pixel unit include photodiodes PD1, PD2, PD3, PD4, and transfer transistors TXA, TXB, TXC, TXD. Among them, the photodiodes PD1, PD2, PD3, PD4 are used to accumulate charges generated by the photoelectric effect in response to incident light. The transfer transistors TXA, TXB, TXC, TXD are coupled between the corresponding photodiodes PD1, PD2, PD3, PD4 and the floating diffusion node FD for transferring charges accumulated during the exposure process of the corresponding photodiodes PD1, PD2, PD3, PD4 to the floating diffusion node FD according to the transfer control signals TXA, TXB, TXC, tcd, respectively. Here, one floating diffusion node FD may be shared by four pixels in one pixel unit, or two adjacent pixels may share one floating diffusion node, and the nodes FD1 and FD2 are formed to be electrically connected to the gate of the source follower transistor SF at the same time, and signals corresponding to the two nodes FD1 and FD2 are output at the same time based on an output circuit. Specifically, the anode terminals of the photodiodes PD1, PD2, PD3, PD4 are connected to ground, and the cathode terminals thereof are coupled to the floating diffusion node FD via the corresponding pass transistors TXA, TXB, TXC, TXD.

The reset transistor RST is coupled between a first voltage source Vrab and the floating diffusion node FD for resetting a voltage of the floating diffusion node FD according to a reset control signal RST.

The amplification output unit is coupled to the floating diffusion node FD and is configured to amplify and output a voltage signal of the floating diffusion node FD. Specifically, in the present embodiment, the amplified output unit includes a source follower transistor SF having a gate coupled to the floating diffusion node FD, a drain coupled to the second voltage source Vrsf, and a source as an output terminal coupled to the row select transistor. Of course, the present embodiment only schematically shows one implementation of the amplifying output unit, and those skilled in the art should realize that the amplifying output unit may also use other amplifying devices with different gains to replace the source follower transistor SF, for example, a two-stage or multi-stage amplifier may be used to replace the source follower transistor SF in the present embodiment, and these variations are also within the protection scope of the present application.

In both embodiments, the pixel circuit further includes a dual conversion gain control unit coupled between the reset transistor RST and the floating diffusion node FD for implementing gain control. In one embodiment, the dual conversion gain control unit includes a dual conversion gain control transistor DCG coupled between the reset transistor RST and the floating diffusion node FD, and a dual conversion gain capacitor Cdcg. A first terminal of the dual conversion gain capacitor Cdcg is coupled to a node between the dual conversion gain transistor DCG and the reset transistor RST, and a second terminal of the dual conversion gain capacitor Cdcg is connected to a prescribed level.

As a preferred embodiment, the pixel circuit provided in this embodiment further includes a row selection transistor RS, which is coupled between an output terminal (e.g., a source of the source follower transistor SF) of the amplified output unit and the column output line, and a gate of which receives a control signal RS for outputting a voltage signal of the floating diffusion node FD. Of course, the row select transistor RS is present as a preferred embodiment, and the implementation of the present application does not necessarily require the row select transistor RS.

The reset transistor RST, the transmission transistor TX, the source follower transistor SF, the row selection transistor RS, and the dual conversion gain control transistor DCG are all NMOS, N is 16 × 16, the transmission transistors of the pixels (r) in the 5 th column and the 13 th column in the 0 th row and the 2 nd row are respectively connected to the first transmission control line txap and the second transmission control line txcp in the first group of transmission control lines, the transmission transistors of the remaining pixel units in the 0 th row and the 2 nd row are respectively connected to the first transmission control line txa, the second transmission control line txb, the third transmission control line txc, and the fourth transmission control line txd in the second group of transmission control lines, and the control timing sequence thereof is as shown in fig. 14b to exemplify the operating principle of the image sensor of the present embodiment, and the specific operating process thereof is as follows:

2. at the time of t1, setting the reset signal rst and the dual conversion gain selection signal dcg to be low levels to obtain corresponding image reset signals; of course, in other embodiments, the dual conversion gain selection signal dcg may be asserted high;

3. at time t2, setting the first transmission control lines txap and txa in the first group of transmission control lines and the second group of transmission control lines and the third transmission control lines txcp and txc in the first group of transmission control lines and the second group of transmission control lines to be high level, and starting to transmit right phase information by all the pixel units in the 0 th row, the 2 nd row, the 12 th row and the 14 th row;

4. at the time of t3, setting the first transmission control lines txap and txa in the first group of transmission control lines and the second group of transmission control lines and the third transmission control lines txcp and txc in the first group of transmission control lines and the second group of transmission control lines to be low levels, finishing transmitting right phase information by all pixel units in the 0 th row, the 2 nd row, the 12 th row and the 14 th row, and quantizing by a quantization circuit to obtain right phase information VRPD;

5. at time t4, setting the second transmission control lines txbp and txb in the first group of transmission control lines and the second group of transmission control lines and the fourth transmission control lines txdp and txd in the first group of transmission control lines and the second group of transmission control lines to high level, and starting to transmit left phase information by all pixel units in the 4 th row, the 6 th row, the 8 th row and the 10 th row;

6. at time t5, setting the second transmission control lines txbp and txb in the first group of transmission control lines and the second group of transmission control lines and the fourth transmission control lines txdp and txd in the first group of transmission control lines and the second group of transmission control lines to be low level, finishing transmitting left phase information by all pixel units in the 4 th row, the 6 th row, the 8 th row and the 10 th row, and obtaining image information Vsum through quantization by a quantization circuit if the two kinds of phase information are summed at a floating diffusion node fd;

7. at the time t6, the reset signal rst or the dual conversion gain selection signal dcg is set to be at a high level, and the floating diffusion node fd is reset;

8. at time t7, the row selection signal rs is set to low level, and the quantization of the current row is ended.

Through digital operation, left phase information VLPD ═ Vsum-VRPD can be obtained, so that the image sensor of the embodiment can realize phase focusing with the full-array left-right phase information density of 100%.

In other embodiments, a reset operation in which the reset signal rst or the dual conversion gain selection signal dcg is set high and then set low may be added between time t3 and time t4, so that the quantization circuit quantizes only left phase information instead of the summed Vsum again at time t 5. In addition, it should be noted that, based on the above control principle, other focusing data for phase focusing may also be acquired based on txap and txcp; in addition, the corresponding relationship between txap and txcp and txa, txb, txc and tcd in time sequence can be designed according to actual requirements.

Fig. 14a is a schematic diagram illustrating an effect of the image sensor according to the second embodiment of the present application in achieving a phase focusing mode with a left-right phase information density of 100%. If each pixel unit in the pixel array is quantized by the timing control shown in fig. 14b to obtain the left phase information 10b and the right phase information 10a, a phase focusing mode with a left-right phase information density of 100% can be realized, and fig. 14a only shows the 4 × 2 array, but the present application is not limited thereto. The left phase information 10b and the right phase information 10a are used for phase focusing.

Fig. 15b is a timing diagram of the image sensor according to the second embodiment of the present application when phase focusing with a top and bottom phase information density of 100% is achieved. Referring to fig. 15b, 12 and 13, the first transmission control lines txap and TXA in the first and second sets of transmission control lines and the second transmission control lines txbp and TXB in the first and second sets of transmission control lines corresponding to a pixel unit are all set to high level to turn on the transmission transistors TXA and TXB in the first and second pixel units to start transmitting the upper phase information, and after a period of time, the first transmission control lines txap and TXA in the first and second sets of transmission control lines and the second transmission control lines txbp and TXB in the first and second sets of transmission control lines are set to low level to set the transmission transistors txbp and TXB in the first and second pixel units to start transmitting the upper phase information, TXB is cut off, so that the pixel unit finishes transmitting the upper phase information, and the quantized upper phase information can be obtained through quantization by the quantization circuit. In addition, the principle of obtaining quantized lower phase information is similar to that of obtaining upper phase information, and is not described herein again.

Fig. 15a is a schematic diagram illustrating an effect of the image sensor according to the second embodiment of the present application in achieving a phase focusing mode with a top and bottom phase information density of 100%. If each pixel unit in the pixel array is quantized by the timing control as shown in fig. 15b to obtain the upper phase information 20a and the lower phase information 20b, a phase focusing mode with 100% upper and lower phase information density can be realized, and fig. 15a only shows the 4 × 2 array, but the present application is not limited thereto. The upper phase information 20a and the lower phase information 20b are used for phase focusing.

Fig. 16 is a schematic diagram illustrating an effect of the image sensor according to the second embodiment of the present application in achieving a phase focusing mode with 100% of left, right, up and down phase information density. As with the 4x4 image sensor array, pixel array 500 may be extended to any suitable size for the respective application. The 4x2 in the pixel array 500 is quantized by the timing control of fig. 14b to obtain the corresponding image information 130, right phase information 130a, and left phase information 130b, and the 4x2 in the pixel array 500 is quantized by the timing control of fig. 15b to obtain the corresponding image information 131, right phase information 131a, and left phase information 131b, wherein the image information is used for imaging, the left and right phase information is used for phase focusing, and actually, the left and right phase information accounts for the ratio of the whole image array according to the phase focusing requirement.

Fig. 17b is a timing diagram of the image sensor according to the second embodiment of the present invention when the left and right phase information density is 3%, and fig. 17a shows a corresponding pixel layout design, please refer to fig. 11 and fig. 17a and 17b at the same time, as shown in fig. 1, in the 16 × 16 pixel array, for example, the transmission transistors of two pixels of the 5 th and 13 th column pixel units in the 2 nd row and the 1 st and 9 th column pixel units in the 14 th row are respectively connected to the first group of transmission control lines txap and txcp, and the transmission transistors of the remaining pixel units in the 2 nd and 14 th rows are connected to the corresponding second group of transmission control lines txa, txb, txc and txd; the transfer transistors of two pixels in the 1 st column and the 9 th column of pixel unit in the 6 th row and the 5 th column and the 13 th column of pixel unit in the 10 th row are connected to the first group of transfer control lines txbp and txdp, respectively, and the transfer transistors of the remaining pixel units are connected to the second group of transfer control lines txa, txb, txc and txd, respectively.

Therefore, under the control of the timing signal shown in fig. 17b, txa/txb/txc/txd/txap/txbp/txcp/txdp for the rows without phase focusing pixel points are simultaneously turned on to obtain normal image information, txa/txb/txc/txd for the rows with phase focusing pixel points are simultaneously turned on, txap/txbp/txcp/txdp are set at a low level, normal image information is obtained for the pixel points not in phase focusing in a row, phase focusing points of txap/txcp are connected to obtain phase information in the left direction (obtained based on the pixels connected to the second group of transmission control lines), and phase focusing points of txbp/txdp are connected to obtain phase information in the right direction (obtained based on the pixels connected to the second group of transmission control lines). Therefore, under the control of the timing signals as shown in fig. 17b, the present application can realize the 3% phase focus mode. Of course, other density focusing may be achieved by the design and readout of the pixels connected to the first set of transfer control lines.

Fig. 18a and 18b are timing diagrams of the image sensor according to the second embodiment of the present application when the left-right phase information density is 6%. Referring to fig. 11 and fig. 18a and 18b, as shown in fig. 11, in the 16 × 16 pixel array, the transfer transistors of the two pixels of the pixel units in the 5 th column and the 13 th column in the 0 th row and the 2 nd row and the pixel units in the 1 st column and the 9 th column in the 12 th row and the 14 th row are respectively connected to the first group of transfer control lines txap and txcp, and the transfer transistors of the remaining pixel units in the 0 th row, the 2 nd row, the 12 th row and the 14 th row are respectively connected to the corresponding second group of transfer control lines txa, txb, txc and txd; the transfer transistors of two pixels in the 1 st column and the 9 th column of pixel units in the 4 th row and the 6 th row and the 5 th column and the 13 th column of pixel units in the 8 th row and the 10 th row are connected to the first group of transfer control lines txbp, txdp, respectively, and the transfer transistors of the remaining pixel units are connected to the second group of transfer control lines txa, txb, txc, txd, respectively.

Therefore, under the control of the timing signals shown in fig. 18a, eight pixel units, namely, the pixel units of the 5 th column and the 13 th column in the 0 th row and the 2 nd row and the pixel units of the 1 st column and the 9 th column in the 12 th row and the 14 th row, are used for acquiring right phase information, and the rest pixel units in the 0 th row, the 2 nd row, the 12 th row and the 14 th row are used for acquiring normal image information; eight pixel units, namely, pixel units at 1 st column and 9 th column in 4 th row and 6 th row and pixel units at 5 th column and 13 th column in 8 th row and 10 th row, are used for acquiring left phase information, and the rest pixel units are used for acquiring normal image information. For a specific implementation principle, please refer to the above description, which is not repeated herein. Therefore, under the control of the timing signals as shown in fig. 18a, the present application can realize a 6% phase focus mode.

Fig. 18b is a timing diagram of the image sensor according to the second embodiment of the present application when the left-right phase information density is 6%. Fig. 18b is substantially the same as the timing signals shown in fig. 18a, except that the time at which the first group of transmission control lines txap, txcp and the second group of transmission control lines txa, txb, txc, txd are high level coincides. Under the control of the timing signal shown in fig. 18b, the present application can also realize a 6% phase focusing mode, and for the specific principle, please refer to the corresponding description of fig. 18a, which is not repeated herein.

Fig. 19a is a timing diagram of the image sensor according to the second embodiment of the present application when the left-right phase information density is 3%, and fig. 19b shows a corresponding pixel layout design, please refer to fig. 11 and fig. 19a and 19b, in fig. 19a, the left side of the vertical dividing line represents reading data of 0-7 th rows in the pixel array, and half of the phase information is obtained from the pixel units connected to the first group of transmission control lines in the 8 rows; in the first 8 rows of pixel units, the focusing pixels in the 4 th row and the 6 th row can acquire left phase information. Meanwhile, the right side of the vertical dividing line represents the data of 8 th to 15 th rows in the read pixel array, and the pixel units connected with the first group of transmission control lines in the 8 th row of data acquire the other half of phase information; in the last 8 rows of pixel units, the 12 th row and the 14 th row can acquire right phase information. Therefore, complete phase information can be obtained based on the pixel units connected with the first group of transmission control lines in the 0 th to 15 th rows, but for the focusing pixel units connected with the first group of transmission control lines in fig. 11, half of unread phase information is equivalent, and the focusing pixel units actually correspond to a 3% phase focusing mode, so that under the control of the timing signals shown in fig. 19a, the application can realize the 3% phase focusing mode with the left and right phase information density, and of course, other density transformations designed by those skilled in the art according to actual requirements can also be realized.

Referring to fig. 20, as shown in fig. 20, the present embodiment provides an image sensor 100, which includes a pixel array 110, where the pixel array 110 is arranged in rows and columns, a structure of each pixel in the pixel array 110 may be the pixel structure shown in fig. 12 and 13, and for a specific situation of the pixel structure, reference is made to the above description, and details are not repeated here.

Besides, as an exemplary embodiment, the image sensor further includes a logic control unit 120, a driving unit, a column a/D conversion unit 150, and an image processing unit 160; wherein:

the logic control unit 120 is used for controlling the working sequence logic of the whole system;

one end of the driving unit is connected to the logic control unit 120, and the other end of the driving unit is coupled to the pixel array 110, and is used for driving and controlling each control signal line in the pixel array 110; specifically, the driving unit includes a row driving unit 130 and a column driving unit 140, one end of the row driving unit 130 is connected to the logic control unit 120, and the other end is coupled to the pixel array 110, for providing a corresponding row control signal to the pixel array 110; one end of the column driving unit 140 is connected to the logic control unit 120, and the other end is coupled to the pixel array 110, for providing a corresponding column control signal to the pixel array 110;

the column a/D conversion unit 150 corresponds to each column of pixels in the pixel array 110, and is configured to implement analog/digital conversion of column signals under the control of the logic control unit 120;

the image processing unit 160 is configured to perform image processing on the image digital signals output by the column a/D conversion unit 150 under the control of the logic control unit 120.

It will be apparent to those skilled in the art that various changes and modifications may be made to the invention without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well. All possible combinations of the technical features of the above embodiments may not be described for the sake of brevity, but should be considered as within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the statement that an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the processes, methods, articles, or apparatuses that comprise the element, and that elements, features, or elements having the same designation in different embodiments of the application may or may not have the same meaning as that of the other elements in the embodiment illustrated and/or described in further detail in connection with the context of that embodiment.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. Depending on the context, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, steps, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, steps, operations, elements, components, items, species, and/or groups thereof. The terms "or" and/or "as used herein are to be construed as inclusive or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a; b; c; a and B; a and C; b and C; A. b and C ". An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some way.

The present application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles and spirit of the invention.

Claims

1. A pixel circuit, comprising a plurality of pixel units arranged in an array, each pixel unit comprising:

at least two pixels each including a photoelectric conversion element for generating a charge in response to incident light and a transfer transistor; the transfer transistor is coupled between the photoelectric conversion element and a floating diffusion node, and is used for transferring charges accumulated by the photoelectric conversion element in an exposure process to the floating diffusion node according to a transfer control signal;

wherein the transfer transistors of at least two of the pixels in at least one of the pixel units are connected to a corresponding first set of transfer control lines, the first set of transfer control lines including at least one transfer control line; the transfer transistors in the other pixel units are connected to the corresponding second group of transfer control lines.

2. The pixel circuit according to claim 1, wherein at least two of the pixels in a same one of the pixel units share an on-chip lens, and at least two of the pixels sharing the same on-chip lens are correspondingly connected to the first group of transmission control lines.

3. The pixel circuit according to claim 2, wherein all of the pixels in the same pixel cell share one of the on-chip lenses.

4. The pixel circuit according to claim 1, wherein the number of the transmission control lines in the first group of transmission control lines is greater than or less than or equal to the number of pixels in the corresponding pixel unit.

5. The pixel circuit according to claim 1, wherein, of the pixels of the pixel unit connected to the corresponding first group of the transfer control lines, remaining pixels other than the pixels connected to the first group of the transfer control lines are connected to the second group of the transfer control lines.

6. The pixel circuit according to claim 1, wherein each row of the pixel cells is provided with a corresponding first set of the transfer control lines and a corresponding second set of the transfer control lines.

7. The pixel circuit according to claim 1, wherein the pixel units of the nth row in the pixel circuit are circularly arranged according to the first green and blue color filters, and the pixel units of the (n + 1) th row are circularly arranged according to the red and second green color filters; or each pixel unit group comprises four pixel units arranged in an array, and the four pixel units in each pixel unit group respectively correspond to the first green color filter, the second green color filter, the first blue color filter, the second green color filter and the red color filter; and the pixel units connected with the first group of transmission control lines are correspondingly arranged at the positions corresponding to the first green or the second green.

8. The pixel circuit according to claim 1, wherein at least one pixel cell is spaced between two pixel cells connected to the first group of the transfer control lines in the same row of the pixel cells; and/or, in the same column of pixel units, at least one pixel unit is arranged between two pixel units connected with the first group of transmission control lines.

9. The pixel circuit according to claim 1, wherein each pixel cell includes four pixels, the first group of the transfer control lines each includes at least two transfer control lines;

the transmission transistors of the four pixels in the pixel unit connected with the first group of transmission control lines are respectively correspondingly connected with at least two transmission control lines in the corresponding first group of transmission control lines.

10. The pixel circuit according to claim 9, wherein when the phase focusing density is not one hundred percent, times at which a first sub-transmission control line and a second sub-transmission control line in the first group of transmission control lines receive the transmission control signal of the effective level are staggered from each other to acquire left-right phase information and/or up-down phase information, and four transmission control lines in the second group of transmission control lines receive the transmission control signal of the effective level to acquire image information;

the first sub-transmission control line comprises at least one transmission control line correspondingly connected with a first pair of adjacent pixels in the four pixels, and the second sub-transmission control line comprises at least one transmission control line correspondingly connected with a second pair of adjacent pixels except the first pair of adjacent pixels in the four pixels.

11. The pixel circuit of claim 1, wherein the pixel circuit further comprises:

a reset transistor coupled between a first voltage source and the floating diffusion node; and/or the presence of a gas in the atmosphere,

the amplification output unit is coupled to the floating diffusion node and is used for amplifying and outputting the voltage signal of the floating diffusion node; and/or the presence of a gas in the gas,

12. The pixel circuit according to claim 1, wherein the timing of the transmission control signals received by the first group of transmission control lines is the same as the timing of the transmission control signals received by the second group of transmission control lines at a phase focusing density of one hundred percent; when the phase focusing density is not one hundred percent, the time sequence of the transmission control signals received by the first group of transmission control lines is different from that of the transmission control signals received by the second group of transmission control lines.

13. The pixel circuit according to any of claims 1-12, wherein each pixel cell comprises four pixels, four of the pixels in the same pixel cell share an on-chip lens, and the first set of transmission control lines each comprises at least two transmission control lines;

wherein, in the pixel unit connected to the first group of transmission control lines, at least two of the pixels are connected to at least two of the transmission control lines in the first group of transmission control lines to acquire phase information.

14. An image sensor comprising the pixel circuit according to any one of claims 1 to 13.