CN217060793U - Intelligent gateway port multiplexing device - Google Patents

Abstract

The utility model discloses an intelligent gateway port multiplexing device, include: the system comprises a micro control unit, a plurality of optical relays and a physical port comprising a wiring terminal; the micro control unit comprises a functional circuit corresponding to a plurality of port types and a plurality of GPIO pins; the micro control unit is used for determining the levels corresponding to the GPIO pins according to the types of the ports to be gated; and the plurality of optical relays are connected with the plurality of GPIO pins and the wiring terminals and used for controlling the conduction of the functional circuits corresponding to the port types to be gated and the wiring terminals according to the levels corresponding to the plurality of GPIO pins and controlling the non-conduction of the functional circuits corresponding to other port types and the wiring terminals so as to enable the physical port to be used as the port corresponding to the port type to be gated. The scheme realizes multiplexing of a plurality of port types by using the same physical port, and effectively reduces the size, energy consumption and material cost of CPE equipment while meeting the multi-scene requirements.

Description

Intelligent gateway port multiplexing device

Technical Field

The utility model relates to a wireless data service transmission technology field, concretely relates to multiplexing device of intelligent gateway port.

Background

The 5G era is a world-wide interconnected era, and in order to adapt to the universal access requirement of a 5G industry private network on multidimensional terminal equipment, the high-reliability and low-delay characteristics of the 5G network are utilized, so that the high-reliability end-to-end data communication capability can be provided for users. The 5G intelligent CPE device (client provisioning Equipment, client device) is an indispensable device for solving 5G access, and the CPE device is a device that is placed on a client side (including an individual client and an enterprise client) to implement a communication function, and corresponds to a Provider side device (PE) to provide services such as networking, application, entertainment, and the like for a user. The types of the CPE equipment comprise a home gateway of a fixed network, a home access router, a television set top box, an optical network unit and the like. The basic requirements of industrial customers on 5G intelligent CPE equipment are mainly three points, one is that 5G full-band access is realized and 4G is compatible, the other is that strong edge computing capability is required, various VPNs and protocol conversion can be easily operated, even a lightweight database can be operated, end-to-end communication and edge computing capability are provided for the customers, and the third is that rich interfaces can be provided so as to be suitable for accessing various terminal equipment.

CPE equipment suppliers desire to keep the variety of end-point equipment as small as possible to reduce the cost of design, commissioning, testing and production. However, the demands of users are various, if a plurality of various ports are reserved in an independently designed mode, not only can the physical space of the interface of the CPE equipment be occupied, but also the CPE equipment cannot be miniaturized, the cost of power consumption and materials can be increased, and further waste is caused. Some CPE equipment providers also use a jumper or dial-up manner to improve the versatility of the CPE equipment, but this manner increases the number of reserved ports, increases the complexity of the equipment, and further increases the failure rate of the equipment. Therefore, how to effectively reduce the size, energy consumption and material cost of the CPE equipment while meeting the multi-scenario requirements becomes an urgent problem to be solved.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present invention has been made to provide an intelligent gateway port multiplexing device that overcomes or at least partially solves the above-mentioned problems.

The utility model provides an intelligent gateway port multiplexing device, the device includes: the system comprises a micro control unit, a plurality of optical relays and a physical port comprising a wiring terminal;

the micro control unit comprises a functional circuit corresponding to a plurality of port types and a plurality of GPIO pins, and the GPIO pins are used for controlling the gating state of the functional circuit corresponding to the plurality of port types; the micro control unit is used for determining the levels corresponding to the GPIO pins according to the types of the ports to be gated;

the plurality of optical relays are connected with the plurality of GPIO pins and the wiring terminals and used for controlling the functional circuits corresponding to the port types to be gated to be conducted with the wiring terminals according to the levels corresponding to the plurality of GPIO pins and controlling the functional circuits corresponding to other port types to be not conducted with the wiring terminals so as to enable the physical port to be used as the port corresponding to the port type to be gated.

Further, the plurality of GPIO pins include: the first pin is used for controlling the gating state of the functional circuit corresponding to the port type to be gated and the second pin is used for controlling the gating state of the functional circuit corresponding to other port types;

the micro control unit is further configured to: and determining the level corresponding to the first pin as a first level and determining the level corresponding to the second pin as a second level according to the type of the port to be gated.

Further, the first level is a low level, and the second level is a high level; alternatively, the first level is a high level and the second level is a low level.

Further, the plurality of port types includes: an analog input port type, an analog output port type, a digital input port type, and a digital output port type.

Further, the plurality of port types further includes: RS232 port type; the device also includes: 232 chip;

the 232 chip is connected with a sending pin and a receiving pin of a universal asynchronous receiver-transmitter in a plurality of GPIO pins and an optical relay for controlling and switching the 232 chip.

Further, the plurality of port types further includes: RS485 port type; the device also includes: 485 chips;

the 485 chip is connected with a transmitting pin and a receiving pin of the universal asynchronous receiving and transmitting transmitter in the GPIO pins and an optical relay for controlling and switching the 485 chip.

Further, the physical port further comprises: and a ground terminal.

According to the technical scheme provided by the utility model, utilize same physical port to realize multiplexing to a plurality of port types, can realize RS232 port type, RS485 port type, AI port type, DI port type, AO port type and DO port type's port is multiplexing conveniently, and the hardware switches over and uses electronic circuit as the settlement of multiplexing function, need not to unpack apart the casing can carry out the switching of function; the device does not need to adopt a configuration mode of a plectrum and a jumper wire, and can realize port multiplexing by configuring the levels corresponding to a plurality of GPIO pins according to the type of the port to be gated, so that the device not only can be remotely operated, but also is beneficial to reducing the failure rate; the device has higher multiplexing degree, has saved the space of CPE equipment effectively, has improved the compatibility again, can effectively reduce the size, energy consumption and the material cost of CPE equipment when satisfying the multi-scene demand. Meanwhile, the user can design the number of the physical ports according to the actual requirement of the user so as to increase the capacity of the access equipment; in addition, the use of the optical relay as a switching device has advantages of low power consumption and short switching time compared to an electromagnetic relay, and does not have a disadvantage of mechanical life.

The above description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented according to the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the present invention is given.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

fig. 1 shows a block diagram of an intelligent gateway port multiplexing device according to an embodiment of the present invention;

FIG. 2 shows a pin definition diagram for a set of GPIO pins;

fig. 3 shows a schematic circuit diagram corresponding to port multiplexing for an RS232 port type and an RS485 port type;

FIG. 4 is a circuit schematic diagram showing the port multiplexing correspondence for DI port types and AI port types;

FIG. 5 shows a circuit schematic corresponding to a port multiplexing of the AO port type;

fig. 6 shows a circuit schematic corresponding to port multiplexing for the DO port type.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

Fig. 1 shows a block diagram of an intelligent gateway port multiplexing apparatus according to an embodiment of the present invention, as shown in fig. 1, the intelligent gateway port multiplexing apparatus includes: a micro control unit 110, a plurality of photo relays 120, and a physical port 130 containing a wire connection terminal.

The micro control unit 110 includes a functional circuit corresponding to a plurality of port types and a plurality of GPIO (general purpose input/output) pins, wherein the micro control unit 110 may be an mcu (micro controller unit). The plurality of port types may specifically include: an analog input port type (i.e., AI port type), an analog output port type (i.e., AO port type), a digital input port type (i.e., DI port type), and a digital output port type (i.e., DO port type). Additionally, the plurality of port types may further include: RS232 port type and RS485 port type. In order to realize multiplexing of the RS232 port type and the RS485 port type, the intelligent gateway port multiplexing device further comprises a 232 chip and a 485 chip, wherein the 232 chip and the 485 chip are connected with the micro control unit 110, and the 232 chip and the 485 chip are further connected with the optical relay 120. Specifically, the 232 chip is connected to a transmitting pin and a receiving pin of the universal asynchronous receiver transmitter among the GPIO pins, and the optical relay 120 for controlling switching of the 232 chip; the 485 chip is connected with a sending pin and a receiving pin of a universal asynchronous receiving and sending transmitter in a plurality of GPIO pins and an optical relay 120 for controlling and switching the 485 chip. The 232 chip and the 485 chip can be the 232 chip and the 485 chip which can be obtained in the prior art, and a person skilled in the art can select the chip models and manufacturers of the 232 chip and the 485 chip according to actual needs, and no specific limitation is made here.

The multiple GPIO pins in the micro control unit 110 are used to control the gating states of the functional circuits corresponding to the multiple port types, such as controlling to open and close RS485 communication, controlling to open and close RS232 communication, controlling to open and close analog input, controlling to open and close analog output, controlling to open and close digital input, controlling to open and close digital output, and so on.

The hardware circuit board of the intelligent gateway port multiplexing device in this embodiment performs circuit switching through the optical relay 120 to realize port multiplexing. The switching is to switch the functional circuit corresponding to the port type to be gated to an ON state (i.e., a conducting state) and switch the functional circuits corresponding to other port types to an OFF state (i.e., a non-conducting state), so that the physical port in the intelligent gateway port multiplexing device can be used as the port corresponding to the port type to be gated, thereby realizing multiplexing of a plurality of port types by using the same physical port.

The micro control unit 110 is configured to determine levels corresponding to a plurality of GPIO pins according to types of ports to be gated. Wherein, include among a plurality of GPIO pins: the first pin is used for controlling the gating state of the functional circuit corresponding to the port type to be gated and the second pin is used for controlling the gating state of the functional circuit corresponding to other port types. In this embodiment, for convenience of description, a pin of the multiple GPIO pins, which is used to control the gating state of the functional circuit corresponding to the port type to be gated, is referred to as a first pin, and a pin of the multiple GPIO pins, which is used to control the gating state of the functional circuit corresponding to the other port type, is referred to as a second pin. The micro control unit 110 is further configured to: and determining the level corresponding to the first pin as a first level and determining the level corresponding to the second pin as a second level according to the type of the port to be gated.

The plurality of photo relays 120 are connected to the plurality of GPIO pins and the connection terminals, and are configured to control the functional circuits corresponding to the types of the ports to be gated to be connected to the connection terminals according to the levels corresponding to the plurality of GPIO pins, and control the functional circuits corresponding to the other types of the ports to be disconnected from the connection terminals, so that the physical port is used as the port corresponding to the type of the port to be gated. Specifically, a first pin is opened by a first level, and a functional circuit corresponding to the type of the port to be gated is conducted with a terminal through the optical relay 120 connected to the first pin; the second pin is turned off by the second level, and the optical relay 120 connected to the second pin disconnects the functional circuits corresponding to the other port types from the connection terminals. At this time, only the functional circuit corresponding to the port type to be gated is effective on the whole circuit, and the physical port can be used as the port corresponding to the port type to be gated and is communicated with the port corresponding to the port type to be gated of the external terminal equipment. Wherein the first level is a low level, and the second level is a high level; alternatively, the first level is a high level and the second level is a low level. The first level and the second level can be set by those skilled in the art according to actual needs, and are not limited in detail here. Preferably, for ease of control, the first level is selected to be low and the second level is selected to be high. In the present embodiment, the optical relay 120 is a semiconductor relay using both ac and dc, and is a device in which a light emitting device and a light receiving device are integrated, and the optical relay 120 is used as a switching device, which has advantages of low power consumption and short switching time, and does not have a disadvantage of mechanical life, as compared with an electromagnetic relay.

Specifically, in order to control the port multiplexing, a set of GPIO pins of the micro control unit 110 is required to implement the multiplexing control. Fig. 2 shows a pin definition diagram of a group of GPIO pins, and as shown in fig. 2, a group a of pins, denoted as PA, are used. The PA0 pin can be defined as an AI interface, specifically an AI or DI input interface, and the ADC acquires the voltage of the pin; defining a PA1 pin as a DO interface, specifically a digital output interface; defining a PA2 pin as a PWM (Pulse width modulation) interface; the PA3 pin is defined as an ON _ OFF _ DI _ AI interface, specifically, an interface for controlling the opening and closing of an analog input and a switch input (i.e., a digital input), the interface is opened by a first level, the ON _ OFF _ DI _ AI interface is connected with an optical relay for controlling DI and AI, and in the embodiment, one GPIO pin can be shared for the control of the analog input and the digital input; defining a pin PA4 as an ON _ OFF _ AO interface, specifically an interface for controlling the ON and OFF of analog output, and opening the interface through a first level, wherein the ON _ OFF _ AO interface is connected with an optical relay for controlling AO; defining a pin PA5 as an ON _ OFF _ DO interface, specifically an interface for controlling the opening and closing of digital quantity output, wherein the interface is opened through a first level, and the ON _ OFF _ DO interface is connected with an optical relay for controlling DO; defining a pin PA6 as an ON _ OFF _ RS interface, specifically, an interface used for controlling opening and closing of a serial port communication port, opening the interface through a first level, and connecting the ON _ OFF _ RS interface with an optical relay used for controlling a USART (Universal Asynchronous Receiver/Transmitter); a PA7 pin is defined as a SWITCH _ RS485 interface, specifically used for controlling opening and closing of an RS485 communication port, the interface is opened through a first level, and the SWITCH _ RS485 interface is connected with an optical relay used for controlling switching of a 485 chip; a PA8 pin is defined as a SWITCH _ RS232 pin, and is specifically used for controlling opening and closing of an RS232 communication port, the interface is opened through a first level, and the SWITCH _ RS232 interface is connected with an optical relay for controlling a switching 232 chip; a PA9 pin is defined as a USART _ TX interface, specifically a USART sending pin which is a TX serial communication interface of a micro control unit; a PA10 pin is defined as a USART _ RX interface, specifically a receiving pin of the USART, and is an RX serial communication interface of the micro control unit; a PA11 pin and a PA12 pin are respectively defined as a SWITCH _ AI1 interface and a SWITCH _ AI2 interface, and are specifically interfaces for controlling input interface modes, namely a level value 0-5V input mode, a level value 4-20mA input mode and a DI input mode; the SWITCH _ AI1 interface is connected with an optical relay for controlling and switching 4-20mA input modes; the SWITCH _ AI2 interface is connected to an optical relay for controlling the switching of DI input modes.

As shown in fig. 1, the physical port 130 may further include: and a ground terminal. The number of terminals in the physical port 130 may be 2, terminal 1 and terminal 2 respectively. The intelligent gateway port multiplexing apparatus provided in this embodiment may implement port multiplexing of an RS232 port type, an RS485 port type, an AI port type, a DI port type, an AO port type, and a DO port type. The wiring terminal of 2 lines and the common grounding terminal can realize the arbitrary switching multiplexing of 1-path RS232, 1-path RS485, 2-path AI (0-5V input mode), 2-path AI (4-20mA input mode), 2-path DI, 2-path AO (PWM) and 2-path DO. The intelligent gateway port multiplexing device of the embodiment has higher multiplexing degree, effectively saves the space of CPE equipment, improves compatibility, and can effectively reduce the size, energy consumption and material cost of the CPE equipment while meeting the multi-scene requirements. Meanwhile, the user can design the number of the physical ports 130 according to the actual requirement of the user so as to increase the capacity of the access device.

Specific description will be given below for the port multiplexing implementation manners of the RS232 port type, the RS485 port type, the AI port type, the DI port type, the AO port type, and the DO port type, respectively.

(1) Port multiplexing for RS232 port type and RS485 port type:

fig. 3 shows a circuit schematic diagram corresponding to port multiplexing of an RS232 port type and an RS485 port type, and as shown in fig. 3, the switching circuits of the 232 chip and the 485 chip are connected to GPIO pins of the micro control unit through a SWITCH _ RS485 interface, a SWITCH _ RS232 interface, and an ON _ OFF _ RS interface. And controlling the ON _ OFF _ RS interface to be at a low level, and setting the change-over switch of the functional circuit corresponding to the other port type to be at a high level. The definition of each pin on the 232 chip and the 485 chip can refer to the definition of each pin of the 232 chip and the 485 chip in the prior art, and is not described herein again.

And the level of the ON _ OFF _ RS interface is lowered, so that the connection between the serial port circuit and the wiring terminal is opened. The level of an ON _ OFF _ DI _ AI interface (sharing analog quantity and digital quantity), an ON _ OFF _ DO interface and an ON _ OFF _ AO interface of other circuits is pulled up, the connection with a wiring terminal is closed, meanwhile, the level of a SWITCH _ RS232 interface is pulled down, and the level of a SWITCH _ RS485 interface is pulled up, so that the functional circuit of the 485 chip is completely disconnected from a communication line. At the moment, only the RS232 functional circuit is effective on the whole circuit, and the wiring terminal is communicated with the RS232 port of the external terminal equipment.

The level of the ON _ OFF _ RS interface is lowered, and the connection between the serial port circuit and the wiring terminal is broken through. The level of the ON _ OFF _ DI _ AI interface, the ON _ OFF _ DO interface and the ON _ OFF _ AO interface of other circuits is pulled up, the connection with the wiring terminal is closed, meanwhile, the level of the SWITCH _ RS232 interface is pulled up, and the level of the SWITCH _ RS485 interface is pulled down, so that the functional circuit of the 232 chip is completely disconnected from the communication line. At the moment, only the RS485 functional circuit is effective on the whole circuit, and the wiring terminal is communicated with the RS485 port of the external terminal equipment.

(2) Port multiplexing for DI port type and AI port type:

fig. 4 shows a circuit schematic diagram corresponding to the port multiplexing of the DI port type and the AI port type, as shown in fig. 4, the micro control unit receives the signals to connect the DI circuit to the connection terminal 1 by pulling the level of the ON _ OFF _ DI _ AI interface low, and to pull the levels of the ON _ OFF _ RS interface, the ON _ OFF _ DO interface and the ON _ OFF _ AO interface high, so as to turn OFF the connection of other circuits to the connection terminal 1.

Setting for AI (0-5V) mode: the electrical levels of the SWITCH _ AI1 interface and the SWITCH _ AI2 interface are simultaneously pulled high, at the moment, the wiring terminal 1 is directly connected with an AI interface of the micro control unit, and the micro control unit directly carries out ADC conversion on 0-5V external voltage to calculate a 0-5V acquisition voltage value.

Setting for AI (4-20mA) mode: the level of the SWITCH _ AI1 interface is pulled down, the level of the SWITCH _ AI2 interface is pulled up, at the moment, the terminal 1 is connected with an external 4-20mA power supply, constant 4-20mA current passes through a resistor R2(249 ohm), and the voltage is R2I. At the moment, the micro control unit directly measures the voltage of R2 to perform ADC conversion, and calculates the magnitude of current transmitted by the external sensor.

Setting for the DI mode: the level of the SWITCH _ AI1 interface is pulled high and the level of the SWITCH _ AI2 interface is pulled low, at which time the optical relay U3 and the optical relay U4 are connected together. The external access sensor is in an open circuit state or is not accessed. The ADC pin of the mcu is now at 5V maximum. The external access sensor is in a short circuit state, and values acquired by the ADC are scores of R1 and R3. The software judges that an intermediate value is used as a judgment threshold for AI on-off, and AI value calculation of 0 and 1 can be carried out.

Fig. 4 only shows the circuit connection mode for the connection terminal 1, and the circuit arrangement for the connection terminal 2 can also be performed in a similar manner, which is not described again here.

(3) Port multiplexing for AO port type:

fig. 5 shows a circuit schematic diagram corresponding to port multiplexing of an AO port type, as shown in fig. 5, AO (pwm) mode output, and a voltage value of 0-5V or a current of 4-20mA is output externally for external control or digital output as a slave device.

The micro control unit pulls down the level of the ON _ OFF _ AO interface, so that the AO circuit is connected with the wiring terminal 1. And the level of the ON _ OFF _ RS interface, the ON _ OFF _ DI _ AI interface and the ON _ OFF _ DO interface is pulled high, and the connection between other circuits and the wiring terminal 1 is turned OFF. And the pins of the micro control unit are subjected to PWM configuration. The terminal 1 is subjected to an adjustable PWM AO output by programmed configured frequency division and duty cycle.

Fig. 5 only shows the circuit connection mode for the connection terminal 1, and the circuit arrangement for the connection terminal 2 can also be performed in a similar manner, which is not described again here.

(4) Port multiplexing for DO port type:

fig. 6 shows a circuit schematic diagram corresponding to port multiplexing of the DO port type, and as shown in fig. 6, the micro control unit pulls down the level of the ON _ OFF _ DO interface, so that the DO circuit is connected to the connection terminal 1. And the level of the ON _ OFF _ RS interface, the ON _ OFF _ DI _ AI interface and the ON _ OFF _ AO interface is pulled up, and the connection between other circuits and the wiring terminal 1 is turned OFF. The DO interface of the micro control unit directly operates to level out the bond wire terminal 1.

Fig. 6 only shows the circuit connection mode for the connection terminal 1, and the circuit arrangement for the connection terminal 2 can also be performed in a similar manner, which is not described again here.

In the above fig. 3 to 6, the same interface marks indicate the connection relationship of the connection.

According to the intelligent gateway port multiplexing device provided by the embodiment, multiplexing of a plurality of port types is realized by using the same physical port, port multiplexing of an RS232 port type, an RS485 port type, an AI port type, a DI port type, an AO port type and a DO port type can be conveniently realized, an electronic circuit is used for setting a multiplexing function in hardware switching, and the function switching can be carried out without disassembling a shell; the device does not need to adopt a configuration mode of a shifting sheet and a jumper wire, and can realize port multiplexing by configuring the levels corresponding to a plurality of GPIO pins according to the types of the ports to be gated, so that the device not only can be remotely operated, but also is beneficial to reducing the failure rate; the device has higher multiplexing degree, has saved the space of CPE equipment effectively, has improved the compatibility again, can effectively reduce the size, energy consumption and the material cost of CPE equipment when satisfying the multi-scene demand. Meanwhile, the user can design the number of the physical ports according to the actual requirement of the user so as to increase the capacity of the access equipment; in addition, the use of an optical relay as a switching device has the advantages of low power consumption and short switching time, compared with an electromagnetic relay, and does not have the disadvantage of mechanical life.

The utility model discloses in the little the control unit who mentions, 232 chips, 485 chips etc. be by hardware realization, for example, little the control unit can include operational amplifier, functional circuit etc.. Although some of the modules or chips are integrated with software, the present invention is intended to protect hardware circuits that integrate the corresponding functions of software, not just software itself.

It should be noted that although several components of the intelligent gateway port multiplexing device are described in detail in the above description, such division is merely exemplary and not mandatory. Those skilled in the art will appreciate that the components of the embodiments may be adaptively changed, that a plurality of components in the embodiments may be combined into one component, or that one component may be divided into a plurality of components. It will be appreciated by those skilled in the art that the arrangement of devices shown in the figures or embodiments is merely schematic and represents a logical arrangement. Where components displayed as separate components may or may not be physically separate, components displayed as components may or may not be physical modules.

Finally, it should be noted that: the above list is only the concrete implementation example of the present invention, and of course those skilled in the art can make modifications and variations to the present invention, and if these modifications and variations fall within the scope of the claims of the present invention and their equivalent technology, they should be considered as the protection scope of the present invention.

Claims (7)

1. An intelligent gateway port multiplexing device, the device comprising: the system comprises a micro control unit, a plurality of optical relays and a physical port comprising a wiring terminal;

the micro control unit comprises a functional circuit corresponding to a plurality of port types and a plurality of GPIO pins, and the GPIO pins are used for controlling the gating state of the functional circuit corresponding to the plurality of port types; the micro control unit is used for determining the levels corresponding to the GPIO pins according to the types of the ports to be gated;

and the plurality of optical relays are connected with the plurality of GPIO pins and the wiring terminal and used for controlling the conduction of the functional circuit corresponding to the port type to be gated and the wiring terminal according to the levels corresponding to the plurality of GPIO pins and controlling the non-conduction of the functional circuits corresponding to other port types and the wiring terminal so as to enable the physical port to be used as the port corresponding to the port type to be gated.

2. The apparatus of claim 1, wherein the plurality of GPIO pins comprise: the first pin is used for controlling the gating state of the functional circuit corresponding to the port type to be gated and the second pin is used for controlling the gating state of the functional circuit corresponding to other port types;

the micro control unit is further configured to: and determining the level corresponding to the first pin as a first level and determining the level corresponding to the second pin as a second level according to the type of the port to be gated.

3. The apparatus of claim 2, wherein the first level is a low level and the second level is a high level; or, the first level is a high level, and the second level is a low level.

4. The apparatus of claim 1, wherein the plurality of port types comprise: an analog input port type, an analog output port type, a digital input port type, and a digital output port type.

5. The apparatus of claim 1, wherein the plurality of port types further comprise: RS232 port type; the device further comprises: 232 chip;

the 232 chip is connected with a sending pin and a receiving pin of a universal asynchronous receiver-transmitter in a plurality of GPIO pins and an optical relay for controlling and switching the 232 chip.

6. The apparatus of any of claims 1-5, wherein the plurality of port types further comprise: RS485 port type; the device further comprises: 485 chips;

the 485 chip is connected with a transmitting pin and a receiving pin of the universal asynchronous receiving and transmitting transmitter in the GPIO pins and an optical relay for controlling and switching the 485 chip.

7. The apparatus of any of claims 1-5, wherein the physical port further comprises: and a ground terminal.

Images