CN217037140U - Power control circuit and system - Google Patents
Power control circuit and system Download PDFInfo
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- CN217037140U CN217037140U CN202220339434.4U CN202220339434U CN217037140U CN 217037140 U CN217037140 U CN 217037140U CN 202220339434 U CN202220339434 U CN 202220339434U CN 217037140 U CN217037140 U CN 217037140U
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Abstract
The utility model provides a power control circuit, comprising: the output end of the shift register is connected with the preamplifier, and the output end of the preamplifier is connected with the post-stage audio processing circuit; the first comparison branch is set to be connected with the output end of the preamplifier, when the output signal of the preamplifier is greater than a preset compression threshold value, a first comparison signal is output to control the shift register to move right so as to reduce the gain, and otherwise, a second comparison signal is output; the second comparison branch is set to be connected with the output end of the preamplifier, when the output signal of the preamplifier is smaller than a preset release threshold value, a third comparison signal is output to control the shift register to move left to increase the gain, and otherwise, a fourth comparison signal is output; the gain holding branch is set to be connected with the first comparison branch and the second comparison branch respectively, and controls the shift register to keep the gain unchanged when the second comparison signal and the fourth comparison signal are input.
Description
Technical Field
The utility model relates to the technical field of audio power amplifier electronics, in particular to a power control circuit and a power control system.
Background
In the application of audio power amplification, the amplitude of an input signal is suddenly increased, so that the output stage is conducted for a long time to burn out a chip or a loudspeaker; or a large volume output causing a short time overload. Therefore, it is necessary to automatically control the gain of the power amplifier.
The general automatic gain control technology compares the output signal of an input preamplifier in a power amplifier with a preset potential value, and when the output exceeds the preset potential, a counter is triggered to increase, so that the gain of the preamplifier is reduced; when the output is lower than the preset potential, the counter is decreased, and the gain of the preamplifier is increased, and the typical scheme is shown in a figure 1 in a reference specification.
However, the prior art circuit system of the type shown in fig. 1 has the following drawbacks:
1) by adopting single threshold detection, the output is not low or high, the gain value is not stable in practice and is changed all the time, and noise caused by gain change can exist all the time;
2) to prevent false triggering at the comparison threshold, a certain amount of hysteresis is typically added to the comparator, which results in a fixed comparison bias;
3) the increase or decrease gain mode (release/attack) is susceptible to short-time peaks, valleys and unnecessary gain change actions.
SUMMERY OF THE UTILITY MODEL
The utility model provides a power control circuit and a power control system, which are used for solving the problems of no steady state, noise, fixed comparison deviation and false triggering of an automatic control circuit in the conventional audio power amplifier.
According to a first aspect of the present invention, there is provided a power control circuit comprising: the gain control circuit comprises a first comparison branch, a second comparison branch, a gain holding branch and a shift register, wherein the output end of the shift register is connected with a preamplifier, and the output end of the preamplifier is connected with a rear-stage audio processing circuit;
the input end of the first comparison branch is connected with the output end of the preamplifier, and the output end of the first comparison branch is connected with the first end of the shift register; when the output signal of the preamplifier is greater than a preset compression threshold value, the first comparison branch outputs a first comparison signal to the shift register so that the shift register moves to the right to reduce the gain, otherwise, a second comparison signal is output;
the input end of the second comparison branch is connected with the output end of the preamplifier, and the output end of the second comparison branch is connected with the second end of the shift register; when the output signal of the preamplifier is smaller than a preset release threshold value, the second comparison branch outputs a third comparison signal to the shift register so that the shift register moves leftwards to increase the gain, otherwise, a fourth comparison signal is output;
the gain holding branch is configured to be connected to the first comparing branch and the second comparing branch, and configured to receive output signals of the first comparing branch and the second comparing branch, and output a control signal to the shift register when receiving the second comparing signal and the fourth comparing signal, so that the shift register keeps the gain unchanged.
Optionally, the first comparing branch includes: a first comparator, wherein when the output signal of the preamplifier is greater than the compression threshold, the first comparator outputs a first high level, otherwise, the first comparator outputs a first low level, and when the first high level is output, the first comparison branch outputs the first comparison signal;
the second comparison branch comprises: the second comparator outputs a second low level when the output signal of the preamplifier is smaller than the release threshold, otherwise, the second comparator outputs a second high level, wherein the second low level is input into the first inverter for inversion, and then the third comparison signal is output;
the gain holding branch includes: the second inverter is arranged to be connected with the output end of the second comparator, and the gain holding branch circuit outputs a first enable signal when the first low level is input into the second inverter and then outputs a high level and the second comparator outputs a second low level;
the two input ends of the AND gate circuit are respectively connected with the output ends of the first comparison branch and the gain holding branch, and the output end of the AND gate circuit is connected with the right shift trigger end of the shift register; when the first enable signal and the first comparison signal are simultaneously input into the AND gate circuit, the AND gate circuit outputs a high level to the right shift trigger end of the shift register to trigger the right shift trigger end to reduce the gain, otherwise, the AND gate circuit outputs a low level to the right shift trigger end of the shift register to keep the right shift trigger end in a holding state and keep the gain unchanged.
Optionally, the first comparing branch further includes: the first counter is connected with the first comparator to count a first high level, and outputs a first comparison signal when the high level pulse count reaches a first preset threshold value;
the gain holding branch includes: and the second counter is set to count a second low level output by the second comparator when the second inverter outputs a high level, and outputs the first enabling signal when the low level pulse count reaches a second preset threshold value.
Optionally, the first comparing branch further includes: a first D flip-flop configured to connect the first comparator and the first counter; the second comparison branch further comprises: a second D flip-flop configured to connect the second comparator and the first inverter;
the first D flip-flop and the second D flip-flop are set as: resampling an input signal by adopting a high-speed clock;
the second inverter in the gain holding branch is set to be connected with the output end of the first D flip-flop 13, and the first D flip-flop inverts the first low level output by the first comparator and inputs the inverted first low level into the second counter; and the second comparator outputs a second low level, the second low level is resampled by the second D trigger, and the second counter counts.
Optionally, the first comparing branch further includes: the first delay unit circuit is connected with the first counter, and outputs the first comparison signal after delaying for a preset time after the high-level pulse count reaches a first preset threshold;
the second comparing branch comprises: and the second delay unit circuit is arranged to be connected with the second D trigger, and outputs the output of the second D trigger to the first inverter after delaying for a preset time.
Optionally, the high-speed clock is 500 KHz.
Optionally, the values of the first preset threshold and the second preset threshold are 2.
Optionally, the first comparator and the second comparator are configured to output a high level if the input signal of the measured potential end is greater than the input signal of the reference end, and otherwise output a low level; the preamplifier outputs signals to be measured of the first comparator, the compression threshold is input to the reference end of the first comparator, the preamplifier outputs signals to be input to the reference end of the second comparator, and the release threshold is input to the measured potential end of the second comparator; or
The first comparator and the second comparator are configured to output a high level if the input signal of the tested potential end is smaller than the input signal of the reference end, otherwise, output a low level; the preamplifier output signal is input into the reference end of the first comparator, the compression threshold is input into the measured potential end of the first comparator, the preamplifier output signal is input into the measured potential end of the second comparator, and the release threshold is input into the reference end of the second comparator.
Optionally, when the first comparison branch is configured to output a first comparison signal, the shift register is controlled to shift right and the gain is reduced at a preset rate until a peak value of an output signal of the preamplifier is located between the compression threshold and the release threshold;
and the second comparison branch circuit is set to control the shift register to move left and increase the gain at a preset speed when outputting a third comparison signal until the peak value of the output signal of the preamplifier is positioned between the compression threshold value and the release threshold value.
According to a second aspect of the present invention, there is provided a power control system, comprising the power control circuit as described in any one of the above, and further comprising a preamplifier and a post-stage audio processing circuit, wherein the power control circuit is configured to be connected to an output terminal of the preamplifier, so as to make the preamplifier output an adjusted signal to the post-stage audio processing circuit after gain adjustment is performed on an output signal of the preamplifier.
The power control circuit provided by the utility model respectively compares the output of the preamplifier with the compression threshold and the release threshold, realizes the detection of the double thresholds, and simultaneously performs power control of three modes, namely an increase and decrease mode and a holding mode of the gain according to the result of the double thresholds, so that the output of the preamplifier in a steady state avoids additional noise caused by continuous adjustment.
Meanwhile, the utility model uses the high-speed clock resampling of the D trigger through the comparison result, thereby avoiding the false triggering burr at the threshold value position, and ensuring that the comparator does not need to add the delay quantity causing deviation.
In addition, the counter is adopted to enable the pulses to reach the preset number, so that the false triggering of the response mode is prevented.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional power control circuit;
FIG. 2 is a schematic diagram of a power control circuit according to an embodiment of the present invention;
FIG. 3 is a power control circuit diagram according to an embodiment of the present invention;
FIG. 4 is a timing diagram of signals of an exemplary application of a power control circuit according to an embodiment of the present invention.
Description of reference numerals:
10-a first comparison branch;
11-a first comparator;
12-a first counter;
13-a first D flip-flop;
14-a first delay cell circuit;
20-a second comparison branch;
21-a second comparator;
22-a first inverter;
23-a second D flip-flop;
24-a second delay cell circuit;
30-a gain-hold branch;
31-a second inverter;
32-a second counter;
40-a shift register;
50-AND gate circuit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the utility model described herein are capable of operation in other sequences than those illustrated or described herein. Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Referring to fig. 2, the present embodiment provides a power control circuit, including: the audio signal processing circuit comprises a first comparison branch 10, a second comparison branch 20, a gain holding branch 30 and a shift register 40, wherein the input end of the shift register 40 is respectively connected with the output ends of the first comparison branch 10, the second comparison branch 20 and the gain holding branch 30, the output end of the shift register 40 is connected with a preamplifier, and the output end of the preamplifier is connected with a post-stage audio processing circuit;
the input end of the first comparing branch 10 is set to be connected with the output end of the preamplifier, the output end of the first comparing branch 10 is connected with the first end of the shift register 40, when the output signal of the preamplifier is greater than the preset compression threshold, the first comparing branch 10 outputs the first comparing signal to the shift register 40 so that the shift register 40 moves to the right to reduce the gain, otherwise, the second comparing signal is output;
the input end of the second comparing branch 20 is set to be connected with the output end of the preamplifier, and the output end of the second comparing branch 20 is connected with the second end of the shift register 40; when the output signal of the preamplifier is less than the preset release threshold, the second comparing branch 20 outputs a third comparing signal to the shift register 40 to make the shift register 40 move left to increase the gain, otherwise, outputs a fourth comparing signal;
the gain holding branch 30 is configured to be connected to the first comparing branch 10 and the second comparing branch 20, and controls the shift register 40 to keep the gain unchanged when the second comparing signal of the first comparing branch 10 and the fourth comparing signal of the second comparing branch 20 are simultaneously input to the gain holding branch 30.
The power control circuit is provided with two comparison branches, and two comparison thresholds (respectively corresponding to a compression threshold needing to reduce the gain and a release threshold needing to increase the gain) are respectively and correspondingly detected, so that double-threshold detection is realized, the output signal of a preamplifier between the two thresholds can be screened out, and a shift register is controlled to be kept still through a gain maintaining branch, so that the gain value of the circuit is in a stable state, and extra noise generated by continuous conversion of the gain in the stable state is avoided. The power control circuit in this embodiment controls the gain of the preamplifier through the shift register, so that the signal output by the preamplifier controls the operating state of the post-stage audio processing circuit (modulator + output stage) in the audio chip, thereby controlling the power of the speaker.
Further, referring to fig. 3, the first comparing branch 10 in the present embodiment includes: a first Comparator 11(CMP-Comparator), wherein the preamplifier output signal (Vout _ amp) and the compression threshold (ATT _ VTH) are respectively inputted to two input terminals of the first Comparator 11, when the preamplifier output signal is greater than the compression threshold, the first Comparator 11 outputs a first high level, otherwise, the first Comparator 11 outputs a first low level, and when the first high level is outputted, the first comparing branch 10 outputs the first comparing signal, so that the shift register 40 (shift) is shifted to the right;
and the second comparison branch 20 comprises: the second comparator 21(CMP), the first inverter 22(INV), the preamplifier output signal (Vout _ amp) and the release threshold (REL _ VTH) are respectively input to two input terminals of the second comparator 21, when the preamplifier output signal is less than the release threshold, the second comparator 21 outputs a second low level, otherwise, the second high level is output, wherein the second low level is input to the first inverter 22(INV) for outputting a third comparison signal after inversion, and the third comparison signal is input to the left shift trigger terminal of the shift register, so that the shift register 40 is shifted to the left;
the gain holding branch 30 includes: a second inverter 31(INV) configured to be connected to an output terminal of the first comparator 11, wherein when a first LOW level of the first comparator 11 is input to the second inverter 31 and then outputs a high level, and when the second comparator 21 outputs a second LOW Level (LOW), the gain holding branch 30 outputs a first enable signal;
the two input ends of the and circuit 50 are respectively connected with the output ends of the first comparing branch 10 and the gain holding branch 30, and the output end of the and circuit 50 is connected with the right shift trigger end of the shift register 40; when the first enable signal and the first comparison signal are simultaneously input to the and circuit 50, the and circuit 50 outputs a high level to the right shift trigger terminal of the shift register 40 to trigger the right shift trigger terminal to reduce the gain, otherwise, outputs a low level to the right shift trigger terminal of the shift register 40 to keep the right shift trigger terminal in a hold state and maintain the gain unchanged.
Further, referring to fig. 3 again, the first comparing branch 10 in this embodiment further includes: a first Counter 12(CTR-Counter) configured to be connected to the first comparator 11 to perform a first high level count, and to output a first comparison signal when the high level pulse count reaches a first preset threshold;
the gain holding branch 30 includes: and a second counter 32(CTR) configured to count a second low level output from the second comparator 21 when the second inverter 31 outputs a high level, and to output the first enable signal when the low level pulse count reaches a second preset threshold.
In this embodiment, the values of the first preset threshold and the second preset threshold are both set to 2. The first preset threshold and the second preset threshold are set, so that pulses of output results of the comparator are counted, the preset number is reached, then the enabling is carried out, and mode false triggering is prevented. The values of the first preset threshold and the second preset threshold may also be set to any other values suitable for the specific gain amplification adjustment circuit as required.
Further, in this embodiment, the first comparing branch 10 further includes: a first D Flip-Flop 13(DFF, D Flip-Flop) configured to connect the first comparator and the first counter; the second comparison branch 20 further comprises: a second D flip-flop 23(DFF) provided to connect the second comparator 21 and the first inverter 22;
the first D flip-flop 13 and the second D flip-flop 23 are configured to: the input signal is resampled (i.e., Re-Timing) using a high speed clock. Here, the high speed clock CK is set to 500 KHz. Here the circuit can filter out glitches triggered at the comparison threshold by resampling the outputs of the two comparators with the high speed clock CK of the first D flip-flop 13 and the second D flip-flop 23 respectively, and make the comparators unnecessary to add hysteresis causing the deviation.
The second inverter 31 in the gain holding branch 30 in this embodiment is set to be connected to the output end of the first D flip-flop 13, so that the second inverter inverts the first low level output by the first comparator 11 after being resampled by the first D flip-flop 13, and outputs a high level, and then the second counter 32(CTR) starts to count; meanwhile, the second LOW Level (LOW) output by the second comparator 21 in this embodiment is also resampled by the second D flip-flop 23, and then counted by the subsequent second counter 32 (CTR). After the count reaches the second preset threshold, the gain holding branch 30 outputs the first enable signal.
In a further preferred embodiment, the first comparing branch 10 further comprises: a first DELAY unit circuit 14(DELAY) configured to be connected to the first counter 12, and output a first comparison signal after delaying for a predetermined time after the count of the high level pulses reaches a first predetermined threshold; the second comparison branch 20 comprises: and a second DELAY unit circuit 24(DELAY) connected to the second D flip-flop 23, for delaying an output of the second D flip-flop 23 by a predetermined time and outputting the delayed output to the first inverter 22. The first delay cell circuit 14 and the second delay cell circuit 24 are provided to delay the level signals in the first comparison branch 10 and the second comparison branch 20 by a certain amount, so that the sound volume change corresponding to the output signal after gain adjustment is more natural and smooth in hearing.
Referring to fig. 3, the first counter 12 in the present embodiment is set to be triggered when the second comparing branch 20 outputs a high level signal, so as to avoid misoperation. Specifically, after the second comparator outputs a high level, the high level is resampled by the second D flip-flop 23 and is delayed by the second DELAY unit circuit 24(DELAY), the output ATT _ EN is used as an ENABLE signal to trigger the counting function of the first counter 12, and then the signal ENABLE _2 is output as the first comparison signal by the first DELAY unit circuit 14 (DELAY).
In a further preferred embodiment, the first comparator 11 and the second comparator 21 are configured to output a high level if the input signal of the terminal of the measured voltage is greater than the input signal of the reference terminal, and otherwise output a low level; the output signal of the preamplifier is input into the measured potential end of the first comparator 11, the compression threshold is input into the reference end of the first comparator 11, the output signal of the preamplifier is input into the reference end of the second comparator 21, and the release threshold is input into the measured potential end of the second comparator 21.
In another variant, the first comparator 11 and the second comparator 21 are configured to output a high level if the input signal of the terminal to be measured is smaller than the input signal of the reference terminal, and otherwise output a low level; the output signal of the preamplifier is input to the reference terminal of the first comparator 11, the compression threshold is input to the measured voltage terminal of the first comparator 11, the output signal of the preamplifier is input to the measured voltage terminal of the second comparator 21, and the release threshold is input to the reference terminal of the second comparator 21. The specific working modes of the two comparators can be selected or set by a person skilled in the art according to needs, so that the working modes of the comparators can meet the requirements of selecting the compression threshold and the release threshold, and after the working modes are compared with the input signal, the corresponding comparison result is output to complete the interval selection function.
Further preferably, when the first comparison branch 10 is configured to output the first comparison signal, the shift register 40 is controlled to shift right and the gain is reduced at a preset rate until the peak value of the output signal of the preamplifier is located between the compression threshold and the release threshold;
the second comparing branch 20 is configured to control the shift register 40 to shift left and increase the gain at a predetermined rate when outputting the third comparing signal, until the peak value of the output signal of the preamplifier is between the compression threshold and the release threshold.
Referring again to fig. 3, when the power control circuit of the present invention is operating, the output peak of the current amplifier is greater than the compression threshold (ATT _ VTH), the shift register shifts right, and the gain begins to decrease (attack); when the peak value of the current amplifier is smaller than the release threshold value (REL _ VTH), the shift register moves left, and the gain begins to rise (release); when the current amplifier peak is between the compression threshold and the release threshold, the shift register is stationary and the gain remains constant (hold). If the input range is normal, the output peak value of the amplifier is finally controlled by the system between the compression threshold (ATT _ VTH) and the release threshold (REL _ VTH), and at this time, the gain control circuit is in a hold state, namely, the control system is in a steady state, has no action of gain change, and has no noise generation. The power control circuit is in an attack mode or a release mode, finally, the proper output power is achieved through gain adjustment, the gain is stabilized, the power control circuit enters a holding mode until the input changes, and the power control circuit enters the next stable period.
In a specific application example, an example of the operating waveform of the power control circuit is shown in fig. 4. In this example, 0 to 4 ms: the output amplitude is between a compression threshold (ATT _ VTH) and a release threshold (REL _ VTH), the control circuit is in a hold mode, and the gain is maintained; 4 ms-18 ms: the output amplitude starts to be greater than the compression threshold (ATT _ VTH), the nth (in this case n ═ 2) pulse starts and is delayed by the DELAY controlled by the first DELAY unit circuit 14(DELAY), ENABLE _2 is high, and the decreasing gain of the stabilization rate (rate determined by CLK _ AT) starts until the output peak value enters the interval of the compression threshold (ATT _ VTH) and the release threshold (REL _ VTH) to stabilize; the low level output by the first counter 12 is not reset by the PULSE signal by this time; after 18 ms: since the input amplitude of the gain-adjusted signal (INP) decreases, the output peak value is smaller than REL _ VTH, the control circuit starts to enter the release mode, and the gain increases until the output peak value enters the compression threshold (ATT _ VTH) and release threshold (REL _ VTH) intervals. The power control circuit system can output the set power which is stable in the set interval in a certain input amplitude range.
This embodiment further provides a power control system, which includes the power control circuit as described in any of the above embodiments, and further includes a pre-amplifier and a post-stage audio processing circuit, where the power control circuit is configured to be connected to an output terminal of the pre-amplifier, so as to make the pre-amplifier output an adjusted signal after performing gain adjustment on an output signal of the pre-amplifier, and then make the pre-amplifier output the adjusted signal to the post-stage audio processing circuit (modulator + output stage) of the audio chip, so as to control a speaker to perform audio output. The gain adjustment includes the above-mentioned attack mode (shift register right shift, gain step down), release mode (shift register left shift, gain step up) and hold mode (gain remains unchanged). The post-stage audio processing circuit can be arranged in an audio chip independent of the loudspeaker according to the requirement, or other common arrangement modes can be changed according to the requirement by a person skilled in the art.
In summary, the power control circuit provided by the utility model uses the interval control of the dual threshold for the output amplitude detection, so that the output amplitude finally enters the desired interval, the amplification gain is stable and does not change any more, and noise generated by the gain change action during the single threshold is avoided.
Meanwhile, the power control circuit provided by the utility model respectively resamples the output of the two comparators through the high-speed clock CK, filters out the false triggering burrs at the two comparison threshold values, and enables the comparators not to add the hysteresis quantity causing deviation, thereby enabling the gain adjustment process to be more stable and reliable.
In addition, the gain increasing or decreasing mode of the power control circuit triggers in a triggering mode of a plurality of pulses, so that a triggering threshold is improved, and unnecessary false triggering is avoided.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the utility model has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A power control circuit, comprising: the gain control circuit comprises a first comparison branch, a second comparison branch, a gain holding branch and a shift register, wherein the output end of the shift register is connected with a preamplifier, and the output end of the preamplifier is connected with a rear-stage audio processing circuit;
the input end of the first comparison branch is connected with the output end of the preamplifier, and the output end of the first comparison branch is connected with the first end of the shift register; when the output signal of the preamplifier is greater than a preset compression threshold value, the first comparison branch outputs a first comparison signal to the shift register so that the shift register moves to the right to reduce the gain, otherwise, a second comparison signal is output;
the input end of the second comparison branch circuit is connected with the output end of the preamplifier, and the output end of the second comparison branch circuit is connected with the second end of the shift register; when the output signal of the preamplifier is smaller than a preset release threshold value, the second comparison branch outputs a third comparison signal to the shift register so that the shift register is shifted left to increase the gain, otherwise, a fourth comparison signal is output;
the gain holding branch is configured to be connected to the first comparing branch and the second comparing branch, and configured to receive output signals of the first comparing branch and the second comparing branch, and output a control signal to the shift register when receiving the second comparing signal and the fourth comparing signal, so that the gain of the shift register is kept unchanged.
2. The power control circuit of claim 1, wherein the first comparison branch comprises: a first comparator, wherein when the output signal of the preamplifier is greater than the compression threshold, the first comparator outputs a first high level, otherwise, the first comparator outputs a first low level, and when the first high level is output, the first comparison branch outputs the first comparison signal;
the second comparison branch comprises: the second comparator outputs a second low level when the output signal of the preamplifier is smaller than the release threshold, otherwise, the second comparator outputs a second high level, wherein the second low level is input into the first inverter for inversion, and then the third comparison signal is output;
the gain holding branch includes: the second inverter is arranged to be connected with the output end of the second comparator, and the gain holding branch circuit outputs a first enable signal when the first low level is input into the second inverter and then outputs a high level and the second comparator outputs a second low level;
the two input ends of the AND gate circuit are respectively connected with the output ends of the first comparison branch and the gain holding branch, and the output end of the AND gate circuit is connected with the right shift trigger end of the shift register; when the first enabling signal and the first comparison signal are input into the AND gate circuit at the same time, the AND gate circuit outputs a high level to the right shift trigger end of the shift register to trigger the right shift trigger end to reduce the gain, otherwise, the AND gate circuit outputs a low level to the right shift trigger end of the shift register to keep the right shift trigger end in a holding state and maintain the gain unchanged.
3. The power control circuit of claim 2, wherein the first comparison branch further comprises: the first counter is connected with the first comparator to count a first high level, and outputs a first comparison signal when the high level pulse count reaches a first preset threshold value;
the gain holding branch includes: and the second counter is set to count a second low level output by the second comparator when the second inverter outputs a high level, and outputs the first enabling signal when the low level pulse count reaches a second preset threshold value.
4. The power control circuit of claim 3, wherein the first comparison branch further comprises: a first D flip-flop configured to connect the first comparator and the first counter; the second comparing branch further comprises: a second D flip-flop configured to connect the second comparator and the first inverter;
the first D flip-flop and the second D flip-flop are set as: resampling an input signal by adopting a high-speed clock;
the second inverter in the gain holding branch is set to be connected with the output end of the first D flip-flop, and the first D flip-flop inputs the first low level output by the first comparator into the second counter after inverting the first low level; and the second comparator outputs a second low level, the second low level is resampled by the second D trigger, and the second counter counts.
5. The power control circuit of claim 4, wherein the first comparison branch further comprises: the first delay unit circuit is connected with the first counter, and outputs the first comparison signal after delaying for a preset time after the high-level pulse count reaches a first preset threshold;
the second comparing branch comprises: and the second delay unit circuit is connected with the second D trigger, and outputs the output of the second D trigger to the first inverter after delaying for a preset time.
6. The power control circuit of claim 4, wherein the high speed clock is 500 KHz.
7. The power control circuit of claim 3, wherein the first and second predetermined thresholds have a value of 2.
8. The power control circuit of claim 2, wherein the first comparator and the second comparator are configured to output a high level if the input signal at the measured potential terminal is greater than the input signal at the reference terminal, and otherwise output a low level; the preamplifier outputs signals to be measured of the first comparator, the compression threshold is input to the reference end of the first comparator, the preamplifier outputs signals to be input to the reference end of the second comparator, and the release threshold is input to the measured potential end of the second comparator; or
The first comparator and the second comparator are configured to output a high level if the input signal of the tested potential end is smaller than the input signal of the reference end, otherwise, output a low level; the preamplifier output signal is input into the reference end of the first comparator, the compression threshold is input into the measured potential end of the first comparator, the preamplifier output signal is input into the measured potential end of the second comparator, and the release threshold is input into the reference end of the second comparator.
9. The power control circuit according to claim 1 or 2, wherein the first comparing branch controls the shift register to shift right and decrease the gain at a preset rate until the peak value of the output signal of the preamplifier is between the compression threshold and the release threshold when the first comparing branch is configured to output the first comparing signal;
and the second comparison branch is set to control the shift register to move left and increase the gain at a preset speed when outputting a third comparison signal until the peak value of the output signal of the preamplifier is positioned between the compression threshold and the release threshold.
10. A power control system comprising the power control circuit of any of claims 1 to 9, and further comprising a preamplifier and a post-stage audio processing circuit, the power control circuit being configured to be connected to an output of the preamplifier to cause the preamplifier to output an adjusted signal to the post-stage audio processing circuit after gain adjustment of the preamplifier output signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220339434.4U CN217037140U (en) | 2022-02-18 | 2022-02-18 | Power control circuit and system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220339434.4U CN217037140U (en) | 2022-02-18 | 2022-02-18 | Power control circuit and system |
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