CN217035637U

CN217035637U - High-voltage ESD protection layout structure, integrated circuit and memory

Info

Publication number: CN217035637U
Application number: CN202123386658.5U
Authority: CN
Inventors: 张登军; 马亮; 安友伟; 伍惠瑜; 刘大海
Original assignee: Hefei Boya Semiconductor Co ltd
Current assignee: Hefei Boya Semiconductor Co ltd
Priority date: 2021-12-29
Filing date: 2021-12-29
Publication date: 2022-07-22
Anticipated expiration: 2031-12-29

Abstract

The utility model discloses a high-voltage ESD protection layout structure, an integrated circuit and a memory, which comprise a P well region, an N well region, a source injection region, a drain injection region and a gate region, wherein the P well region is arranged on a substrate, the N well region is arranged in the P well region, the source injection region is arranged in the P well region and is positioned at one side of the N well region, the drain injection region is arranged in the N well region, and the gate region is arranged above the P well region and is respectively connected with the source injection region and the drain injection region. When the memory is used, the grounding end of the P well region and the N well region are connected with the power supply end, and reverse-biased PN junctions are formed between the P well region and the N well region and have higher impedance, so that the high-voltage resistance degree of the memory is improved.

Description

High-voltage ESD protection layout structure, integrated circuit and memory

Technical Field

The utility model relates to the technical field of integrated circuits, in particular to a high-voltage ESD protection layout structure, an integrated circuit and a memory.

Background

In the field of integrated circuits, electrostatic discharge (ESD) has become a serious problem affecting chip reliability. When an ESD event occurs on a chip, a large amount of static charges accumulated in the external environment and the chip can instantly flow through the chip through pins of the chip, so that the problems of PN junction breakdown, metal fusing, gate oxide breakdown and the like are caused. In order to realize the ESD protection, most of MOS transistors in the existing ESD protection device are formed by injecting N-type impurities into a P-well to form a source and a drain of the MOS transistor, however, the ESD protection device with such a structure has a limited high voltage tolerance, and is not suitable for the application in the high voltage electrostatic discharge.

SUMMERY OF THE UTILITY MODEL

The present invention is directed to solving at least one of the problems of the prior art. Therefore, the utility model provides a high-voltage ESD protection layout structure, an integrated circuit and a memory, which can improve the high-voltage resistance of the memory.

On the first hand, the high-voltage ESD protection layout structure comprises a P well region, a P well region and a P well region, wherein the P well region is arranged on a substrate; an N well region disposed within the P well region; the source electrode injection region is arranged in the P well region and is positioned on one side of the N well region; the drain electrode injection region is arranged in the N well region; and the gate region is arranged above the P well region and is respectively connected with the source electrode injection region and the drain electrode injection region.

The high-voltage ESD protection layout structure provided by the embodiment of the utility model at least has the following beneficial effects:

when the memory is used, the P well region grounding end and the N well region are connected with the power supply end, reverse-biased PN junctions are formed between the P well region and the N well region, and the memory has higher impedance, so that the high-voltage resistance degree of the memory is improved.

According to some embodiments of the utility model, the source implant region is an N-type implant region.

According to some embodiments of the utility model, the drain implant region is an N-type implant region.

According to some embodiments of the utility model, the drain implant region comprises a first implant region connected to the gate region and a second implant region having a via region disposed thereon.

In a second aspect, an integrated circuit according to an embodiment of the present invention includes the above-mentioned high-voltage ESD protection layout structure.

In a third aspect, a memory according to an embodiment of the present invention includes one or more of the integrated circuits described above.

Additional aspects and advantages of the utility model will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the utility model.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic longitudinal cross-sectional view of a high-voltage ESD protection layout structure according to an embodiment of the present invention;

fig. 2 is a schematic top view of the high-voltage ESD protection layout structure shown in fig. 1.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

In the description of the present invention, "a plurality" means one or more, "a plurality" means two or more, and greater than, less than, more than, etc. are understood as excluding the present number, and "greater than", "lower than", "inner", etc. are understood as including the present number. If the description of "first", "second", etc. is used for the purpose of distinguishing technical features, it is not intended to indicate or imply relative importance or to implicitly indicate the number of indicated technical features or to implicitly indicate the precedence of the indicated technical features.

In the description of the present invention, unless otherwise explicitly limited, terms such as "disposed," "mounted," "connected," and the like are to be understood in a broad sense, and those skilled in the art can reasonably determine the specific meaning of the terms in the present invention by combining the specific contents of the technical solutions.

Referring to fig. 1 and fig. 2, the present embodiment discloses a high-voltage ESD protection layout structure, which includes a P-well region 100, an N-well region 200, a source injection region 300, a drain injection region 400, and a gate region 500, where the P-well region 100 is disposed on a substrate (not shown), the N-well region 200 is disposed in the P-well region 100, the source injection region 300 is disposed in the P-well region 100 and located at one side of the N-well region 200, the drain injection region 400 is disposed in the N-well region 200, and the gate region 500 is disposed above the P-well region 100 and connected to the source injection region 300 and the drain injection region 400, respectively. When the memory is used, the P-well region 100 is grounded, the N-well region 200 is grounded, and a reverse-biased PN junction is formed between the P-well region 100 and the N-well region 200, so that the resistance is high, and the high voltage resistance of the memory is improved. It should be noted that, the nwell region 200 of the present embodiment is disposed at the drain implantation region 400, so that the nwell region 200 and the drain implantation region 400 can share a conductive via, thereby avoiding additional conductive vias from being disposed in the nwell region 200, which is beneficial to saving the wiring area.

In this embodiment, the structure of an NMOS transistor is taken as an example for description. For an NMOS transistor, the source implant region 300 is an N-type implant region, and the drain implant region 400 is an N-type implant region. Specifically, the drain implant region 400 includes a first implant region 410 and a second implant region 420, the first implant region 410 is connected to the gate region 500, the second implant region 420 is provided with a via region 600, and the via region 600 is used for processing a conductive via, so that the second implant region 420 is electrically connected to a subsequent metal layer.

The embodiment further provides an integrated circuit, which includes the high-voltage ESD protection layout structure, and a reverse-biased PN junction is formed between the P-well region 100 and the N-well region 200, so that the integrated circuit has higher impedance, and thus the high-voltage resistance of the memory is improved.

The embodiment also provides a memory, which comprises one or more integrated circuits. In the memory, an ESD protection circuit may be formed by a combination of a plurality of MOS devices. In the embodiment, the memory is formed by using the integrated circuit, so that the high voltage endurance of the memory can be enhanced.

The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.

Claims

1. A high-voltage ESD protection layout structure is characterized by comprising:

a P-well region (100) disposed on the substrate;

an N-well region (200) disposed within the P-well region (100);

a source implant region (300) disposed within the P-well region (100) and on one side of the N-well region (200);

a drain implant region (400) disposed within the N-well region (200);

a gate region (500) disposed above the P-well region (100) and connected to the source implant region (300) and the drain implant region (400), respectively.

2. The high-voltage ESD protection layout structure according to claim 1, wherein the source implant region (300) is an N-type implant region.

3. The high-voltage ESD protection layout structure according to claim 1 or 2, wherein the drain implant region (400) is an N-type implant region.

4. The high-voltage ESD protection layout structure according to claim 3, wherein the drain implant region (400) comprises a first implant region (410) and a second implant region (420), the first implant region (410) is connected with the gate region (500), and the second implant region (420) is provided with a via region (600).

5. An integrated circuit comprising a high voltage ESD protection layout structure according to any of claims 1 to 4.

6. A memory comprising one or more integrated circuits according to claim 5.