CN216980097U

CN216980097U - Shift register circuit, grid driving circuit and display panel

Info

Publication number: CN216980097U
Application number: CN202220440022.XU
Authority: CN
Inventors: 胡芳; 李荣荣
Original assignee: HKC Co Ltd; Changsha HKC Optoelectronics Co Ltd
Current assignee: HKC Co Ltd; Changsha HKC Optoelectronics Co Ltd
Priority date: 2022-03-01
Filing date: 2022-03-01
Publication date: 2022-07-15
Anticipated expiration: 2032-03-01

Abstract

The application discloses shift register circuit, grid drive circuit and display panel, the embodiment of the application utilizes existing first clock signal end and second clock signal end at the pull-down maintaining module, and the level of the signal in the second node is alternately pulled up and pulled down at the non-output stage of the shift register, so that the level of the signal in the second node is alternately changed at the non-output stage at less transformation cost, and the influence of the second pull-down module on the long-time direct current stress is avoided, and the service life of the shift register is influenced.

Description

Shift register circuit, grid driving circuit and display panel

Technical Field

The application relates to the technical field of display, in particular to a shift register circuit, a grid driving circuit and a display panel.

Background

With the continuous development of Display technology, Liquid Crystal Displays (LCDs) and OLED displays are currently in the market, and have the advantages of thin body, power saving, no radiation and the like, and are widely applied. Such as: televisions, mobile phones, Personal Digital Assistants (PDAs), digital cameras, computer screens or notebook computer screens, etc., are dominant in the field of flat panel displays. In recent years, it has been developed to directly fabricate a shift register circuit structure on a display panel, that is, to supply scan signals to a plurality of rows of pixels through a shift register circuit including a plurality of shift register circuits.

At present, a shift register circuit including a plurality of cascade connections is often used to supply scan signals to pixels of different rows. In the output stage of the shift register circuit, the Q point is at a high level, the output scanning signal is at a high level, the TFT connected to the scanning line is turned on, and the pixel is charged to enable the pixel voltage to be equal to the data voltage so as to ensure that correct gray scale is displayed. When the shift register is in a non-output stage, the Q point is at a low level, the P point which is mutually conjugated with the voltage of the Q point is kept at a high level state for a long time, and the TFT is easy to generate a serious threshold voltage drift phenomenon under long-time voltage stress bias, so that the characteristic degradation of a device is caused, and the service life of the shift register is influenced.

Disclosure of Invention

The embodiment of the application provides a shift register circuit, a grid driving circuit and a display panel, and the problem of reliable usability of the existing shift register is solved by modifying a pull-down maintaining module, so that the influence of direct-current voltage stress on a second pull-down module for a long time is avoided while the number of switching tubes of the shift register is reduced.

Other features and advantages of the present application will be apparent from the following detailed description, or may be learned by practice of the application.

According to a first aspect of the embodiments of the present application, there is provided a shift register circuit, including a first pull-up control module, connected to a first signal terminal and a first node, and configured to provide a signal of the first signal terminal to the first node in response to a signal of the first signal terminal; the first pull-up module is connected with the first node, the first scanning signal output end and the first clock signal end and is used for responding to the signal of the first node and providing the signal of the first clock signal end to the first scanning signal output end; the first pull-down module is connected with a second signal end, a third signal end and the first node and used for responding to the signal of the second signal end and providing the signal of the third signal end to the first node; a second pull-down module, connected to the first node, the second node, the first scanning signal output terminal, the third signal terminal, and the fourth signal terminal, for providing a signal of the third signal terminal to the first node in response to a signal of the second node, and providing a signal of the fourth signal terminal to the first scanning signal output terminal in response to a signal of the second node; a first pull-down maintaining module, connected to the first node, the second node, and the third signal terminal, for providing the signal of the third signal terminal to the second node in response to the signal of the first node, the first pull-down maintaining module being further connected to the first clock signal terminal and the second clock signal terminal, for providing the signal of the first clock signal terminal to the second node in response to the signal of the first clock signal terminal, and for providing the signal of the third signal terminal to the second node in response to the signal of the second clock signal terminal, so that the signal of the second node is alternately changed in a non-output stage of the shift register.

In some embodiments of the present application, based on the above solution, the first pull-down maintaining module is further connected to a fifth signal terminal, and configured to provide a signal of the fifth signal terminal to the second node in response to the signal of the first clock signal terminal.

In some embodiments of the present application, based on the above solution, the first pull-down maintaining module is further connected to the first signal terminal, and configured to provide a signal of the fifth signal terminal to the second node in response to the signal of the first signal terminal.

In some embodiments of the present application, based on the above scheme, the first pull-up control module is further connected to the fifth signal terminal, and configured to provide a signal of the fifth signal terminal to the first node in response to the signal of the first signal terminal.

In some embodiments of the present application, based on the above scheme, the first pull-up control module includes a first switching element, the first pull-up module includes a second switching element, the first pull-down module includes a third switching element, the second pull-down module includes a fourth switching element, a fifth switching element, the first pull-down maintaining module includes a sixth switching element, a seventh switching element, and an eighth switching element; wherein,

the first switch element is turned on by a signal of the first signal terminal to provide a signal of the fifth signal terminal to the first node;

the second switching element is turned on by a signal of the first node to provide a signal of the first clock signal terminal to the first scan signal output terminal;

the third switching element is turned on by a signal of the second signal terminal to provide a signal of the third signal terminal to the first node;

the fourth switching element is turned on by the signal of the second node to provide the signal of the third signal terminal to the first node;

the fifth switching element is turned on by the signal of the second node to provide the signal of the fourth signal terminal to the first scan signal output terminal;

the sixth switching element is turned on by the signal of the first node to provide the signal of the third signal terminal to the second node;

the seventh switching element is turned on by a signal of the first clock signal terminal to provide a signal of the fifth signal terminal to the second node;

the eighth switching element is turned on by a signal of the second clock signal terminal to provide a signal of the third signal terminal to the second node.

In some embodiments of the present application, based on the above scheme, the first pull-down maintaining module further comprises:

a ninth switching element, configured to be turned on by a signal of the second signal terminal, so as to provide a signal of the fifth signal terminal to the second node.

In some embodiments of the present application, based on the above scheme, the first pull-up module further includes:

a tenth switching element, configured to turn on in response to the signal of the first node to provide the signal of the first clock signal terminal to the first cascade signal output terminal.

and the first end of the first capacitor is connected with the first node, and the second end of the first capacitor is connected with the first scanning signal output end and used for charging and discharging.

According to a second aspect of embodiments of the present application, there is provided a gate driving circuit, the gate driving circuit including a plurality of shift register circuits according to the first aspect, the plurality of shift register circuits being cascaded;

the difference between the first clock signal end of the nth stage shift register circuit and the first clock signal end of the (n + m) th stage shift register circuit is half clock period, m is more than 2, and n is more than m;

the first signal end of the nth stage shift register circuit is connected with the first scanning signal output end of the nth-m stage shift register circuit, the second signal end of the nth stage shift register circuit is connected with the first scanning signal output end of the (n + m) th stage shift register circuit, and the second clock signal end of the nth stage shift register circuit is connected with the first clock signal end of the nth-m stage shift register circuit.

According to a third aspect of the embodiments of the present application, there is provided a display panel including a pixel circuit including a plurality of gate lines and a plurality of data lines which are staggered horizontally and vertically; a source driving circuit connected to the plurality of data lines in the pixel circuit; and a gate driving circuit as described in the second aspect, connected to the plurality of gate lines in the pixel circuit.

According to the embodiment of the application, the pull-down maintaining module is improved, the problem of reliable usability of the existing shift register is solved, the number of switching tubes of the shift register is reduced, and meanwhile the second pull-down module is prevented from being influenced by direct-current voltage stress for a long time.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

fig. 1 is a schematic structural diagram of a shift register circuit according to an embodiment of the present disclosure.

Fig. 2 is a driving timing diagram and signal waveform diagram of a shift register circuit according to an embodiment of the present application.

Fig. 3 is a schematic structural diagram of a shift register circuit according to a first embodiment.

Fig. 4 is a schematic structural diagram of a shift register circuit according to a second embodiment.

Fig. 5 is a schematic structural diagram of a shift register circuit according to a third embodiment.

Fig. 6 is a schematic structural diagram of a shift register circuit according to a fourth embodiment.

Fig. 7 is a schematic structural diagram of a shift register circuit according to a fifth embodiment.

Fig. 8 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.

Fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present application.

The reference numbers illustrate:

110: first pull-up control module

120: first upward drawing module

130: first pull-down module

140: second pull-down module

150: first pull-down maintaining module

S1-S10: first to tenth switching elements

An INPUT: a first signal terminal

Feeding: second signal terminal

VSS 1: third signal terminal

VSS 2: a fourth signal terminal

VGH fifth signal terminal

CARRY is a first cascade signal output end

CLK 1: first clock signal terminal

CLK 2: second clock signal terminal

GOUT: output signal terminal

Q: first node

P: second node

C: first capacitor

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the application.

The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. I.e. these functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor means and/or microcontroller means.

The flow charts shown in the drawings are merely illustrative and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.

In the description of the present application, it is to be understood that the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or as implying that the number of indicated technical features is indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.

A shift register circuit generally applied by those skilled in the art includes 16 Thin Film Transistors (TFTs) and 1 capacitor, and the main driving process of the conventional shift register is divided into the following four stages, stage 1: the pull-up control module acts on the Q node to enable the Q node to be at a high level; and (2) stage: under the coupling action of a capacitor in the shift register, the level of a Q node is raised, and at the moment, the pull-up module acts on the output end of the shift register, so that the scan signal output by the shift register is high level, namely the scan signal is output at the output stage in one frame; and (3) stage: the first pull-down module pulls down the level of the Q node, so that the shift register outputs a low level; and (4) stage: the pull-down sustain module and other pull-down modules of the shift register come into play to ensure that the Q point is always guaranteed low during other times of a frame (non-output phase).

It should be noted that, in order to avoid that the P node conjugated with the voltage of the Q node is kept at a high level for a long time in the non-output stage, which causes elements in the pull-down maintaining module to be affected by a long-time direct current stress, so that the elements have a severe threshold voltage drift phenomenon under a long-time voltage stress bias, which causes device characteristic degradation, the shift register uses a plurality of switching elements to form three pull-down modules and two pull-down maintaining modules, which realizes that the Q node is kept at a low level in the non-output stage, the P node is at an alternating current level in the non-output stage, and the shift register and the next shift register need to introduce low-frequency signal lines respectively. The existing shift register introduces more signal lines and utilizes more TFTs, which is not beneficial to realizing the narrow frame design of the display panel.

In order to improve the above situation, an embodiment of the present application provides a shift register circuit. As shown in fig. 1, the shift register circuit at least includes a first pull-up control module 110, a first pull-up module 120, a first pull-down module 130, a second pull-down module 140 and a first pull-down maintaining module 150.

A first pull-up control module 110 connected to the first signal terminal INPUT and the first node Q, for providing a signal of the first signal terminal INPUT to the first node Q in response to the signal of the first signal terminal INPUT;

a first pull-up module 120 connected to the first node Q, the first scan signal output terminal GOUT, and the first clock signal terminal CLK1, for providing the signal of the first clock signal terminal CLK1 to the first scan signal output terminal GOUT in response to the signal of the first node Q;

a first pull-down module 130 connected to the second signal terminal fed, the third signal terminal VSS1, and the first node Q, for providing a signal of the third signal terminal VSS1 to the first node Q in response to a signal of the second signal terminal fed;

a second pull-down module 140, connected to the first node Q, the second node P, the first scan signal output terminal GOUT, the third signal terminal VSS1 and the fourth signal terminal VSS2, for providing a signal of the third signal terminal VSS1 to the first node Q in response to a signal of the second node P, and providing a signal of the fourth signal terminal VSS2 to the first scan signal output terminal GOUT in response to a signal of the second node P;

the first pull-down sustain module 150, which is connected to the first node Q, the second node P, the first clock terminal CLK1, the second clock terminal CLK2, and the third signal terminal VSS1, is used for providing the signal of the third signal terminal VSS1 to the second node P in response to the signal of the first node Q, providing the signal of the first clock terminal CLK1 to the second node P in response to the signal of the first clock terminal CLK1, and providing the signal of the third signal terminal VSS1 to the second node P in response to the signal of the second clock terminal CLK 2.

The operation of the shift register circuit in fig. 1 will be described with reference to the driving timing chart in fig. 2. The duty ratio of the high level of the signal at the clock signal terminal in this example implementation is 50%. The third signal terminal VSS1 and the fourth signal terminal VSS2 are continuously low signals. The signal of the first signal terminal INPUT has the same waveform as the signal of the second clock signal terminal CLK 2. The first clock signal terminal CLK1 differs from the second clock signal terminal CLK2 by half a clock cycle. The signal of the second signal terminal fed differs from the signal of the second clock signal terminal CLK2 by one clock cycle. The signal voltages of the first node Q and the third node P are throttled from each other.

At the first period T1: the signal of the first signal terminal INPUT is a high level signal, and the first pull-up control module 110 pulls up the first node Q to a high level in response to the signal of the first signal terminal INPUT; the first pull-down maintaining module 150 pulls down the signal of the second node P to a low level in response to the signal of the first node Q.

During the second period T2: the first clock signal terminal CLK1 changes from low level to high level, and the first pull-up module 120 pulls up the signal of the first scan signal output terminal GOUT to high level in response to the signal of the first node Q, i.e., outputs the scan signal; the first pull-down maintaining module 150 pulls down the signal of the second node P to a low level in response to the signal of the first node Q.

During the third period T3: the signal of the second signal terminal fed is at a high level, the first pull-down module 130 pulls down the signal of the first node Q point to a low level in response to the signal of the second signal terminal fed, the first pull-up module 120 outputs a low level in response to the signal of the first node Q, and the first scan signal output terminal GOUT outputs a low level; the signal at the second clock terminal CLK2 goes high and the first pull-down sustain module 150 asserts the signal at the second node P low in response to the signal at the second clock terminal CLK 2.

At a fourth time period T4: the first clock terminal CLK1 is high, and the first pull-down maintaining module 150 pulls up the signal at the second node P to a high level in response to the signal at the first clock terminal CLK 1; the second pull-down module 140 pulls down the signal of the first node Q to a low level in response to the signal of the second node P.

At the fifth period T5: the signal at the second clock terminal CLK2 is high, and the signal at the second clock terminal CLK2 of the first pull-down maintaining module 150 pulls down the signal at the second node P to low; the signal of the second signal terminal fed is high level, and the first pull-down module 130 pulls down the signal of the first node Q point to low level in response to the signal of the second signal terminal fed.

As shown in fig. 2, unlike the above-mentioned conventional shift register in which the level of the signal at the second node P is always kept at a high level in the non-output stage, the pull-down maintaining module in the embodiment of the present application enables the level of the signal at the second node to be alternately changed in the non-output stage.

According to the embodiment of the application, under the action of one pull-down maintaining module, the level of the signal in the second node P is alternately pulled up and pulled down in the non-output stage of the shift register by using the existing first clock signal terminal CLK1 and second clock signal terminal CLK2, so that the level of the signal in the second node P is alternately changed in the non-output stage by using fewer signal lines and TFTs (thin film transistors), the influence of direct current stress on the second pull-down module for a long time is avoided, the service life of the shift register is influenced, and meanwhile, the shift register is convenient to realize narrow-frame design.

Next, the specific structure and connection mode of each block in the shift register circuit will be described in detail with reference to first, second, third, fourth, and fifth embodiments.

Example one

In order to pull up the signals of the first node P and the second node Q better at a specific time, as shown in fig. 3, the present embodiment introduces a signal of the fifth signal terminal VGH, which is a continuously high signal, into the shift register on the basis of the above scheme, and replaces the first clock signal terminal CLK1 with the signal of the fifth signal terminal VGH as the input signal of the first pull-down maintaining module.

The first pull-down maintaining module 150 is further connected to the fifth signal terminal VGH for providing the signal of the fifth signal terminal VGH to the second node P in response to the signal of the first clock signal terminal CLK 1.

The first pull-up control module 110 is further connected to the fifth signal terminal VGH for providing the signal of the fifth signal terminal VGH to the first node Q in response to the signal of the first signal terminal INPUT.

The driving process of the present embodiment in the second time period T2, the third time period T3, and the fifth time period T5 is similar to that of the above embodiment, and is not repeated herein.

During the first period T1: the first pull-up control module 210 pulls up the first node Q to a high level in response to a signal of the first signal terminal INPUT; the first pull-down maintaining module 250 pulls up the signal of the second node P to a high level in response to the signal of the first clock signal terminal CLK1 during the fourth period T4.

In this embodiment, on the basis of the shift register, the signal of the fifth signal terminal VGH is introduced, and the signals of the first node Q and the second node P are pulled up at a specific time better through the stable high-level signal, so as to improve the performance of the shift register.

Example two

In order to reduce the falling delay of the output scan signal, as shown in fig. 4, on the basis of the first embodiment, the first pull-down maintaining module 150 in this embodiment is further connected to the first signal terminal INPUT for providing the signal VGH of the fifth signal terminal to the second node in response to the signal of the first signal terminal INPUT.

The driving process of the embodiment in the first period T1, the first period T2, the fourth period T4 and the fifth period T5 is similar to the driving process of the above embodiment, and is not repeated herein.

In the third period T3, the signal of the first signal terminal INPUT is at a high level, the first pull-down module 230 pulls down the signal of the point Q of the first node to a low level in response to the signal of the first signal terminal INPUT, and on the basis, the first pull-down maintaining module 150 pulls up the signal of the second node P to a high level in response to the signal of the first signal terminal INPUT, the second pull-down module 140 pulls down the signal of the first node Q to a low level in response to the signal of the second node P, the first pull-up module 220 outputs a low level in response to the signal of the first node Q, and the first scanning signal output terminal GOUT outputs a low level.

As can be seen, in the third period T3, under the action of the first pull-down maintaining module 150, the first pull-down module 230 and the second pull-down module 140 pull down the first node Q together, so that the scan signal changes to a low level quickly, and the falling delay of the scan signal is further reduced.

EXAMPLE III

As shown in fig. 5, in the present embodiment, the first pull-up control module 110 includes a first switch element S1, the first pull-up module 120 includes a second switch element S2, the first pull-down module 130 includes a third switch element S3, the second pull-down module 140 includes a fourth switch element S4 and a fifth switch element S5, and the first pull-down maintaining module 150 includes a sixth switch element S6, a seventh switch element S7 and an eighth switch element S8; wherein,

a first switching element S1, which is turned on by the signal of the first signal terminal INPUT to provide the signal of the fifth signal terminal VGH to the first node Q;

a second switching element S2, turned on by the signal at the first node Q, for providing the signal at the first clock signal terminal CLK1 to the first scan signal output terminal GOUT;

a third switching element S3 turned on by the signal of the second signal terminal fed to provide the signal of the third signal terminal VSS1 to the first node Q;

a fourth switching element S4, turned on by the signal at the second node P, for providing the signal at the third signal terminal VSS1 to the first node Q;

a fifth switching element S5, turned on by the signal at the second node P, for providing the signal at the fourth signal terminal VSS2 to the first scan signal output terminal GOUT;

a sixth switching element S6, turned on by the signal at the first node Q, for providing the signal at the third signal terminal VSS1 to the second node P;

a seventh switching element S7 turned on by the signal of the first clock signal terminal CLK1 to supply the signal of the fifth signal terminal VGH to the second node P;

the eighth switching element S8 is turned on by the signal of the second clock signal terminal CLK2 to provide the signal of the third signal terminal VSS1 to the second node P.

In the present exemplary embodiment, the first to eighth switching elements (S1 to S8) may correspond to first to eighth switching transistors, respectively, each having a control terminal, a first terminal, and a second terminal. Specifically, the control terminal of each switching transistor may be a gate, the first terminal may be a source, and the second terminal may be a drain; or the control terminal of each switching transistor may be a gate, the first terminal may be a drain, and the second terminal may be a source. In addition, each of the switching transistors may be an enhancement transistor or a depletion transistor, and this exemplary embodiment is not particularly limited thereto. In addition, each switch transistor may be an N-type transistor or a P-type transistor, which is not particularly limited in the present exemplary embodiment.

The operation of the shift register circuit in fig. 5 will be described with reference to the driving timing diagram in fig. 2 by taking an example in which all the switching elements are N-type thin film transistors. Since the switching elements are all N-type thin film transistors, on signals of all the switching elements are high level signals, and off signals of all the switching elements are low level signals.

At the first period T1: the signal of the first signal terminal INPUT is a high level signal, the signal of the fifth signal terminal VGH is a high level, and the first switching element S1 is turned on by the signal of the first signal terminal INPUT to pull up the first node Q to a high level; the sixth switching element S6 is turned on by the signal of the first node Q to pull down the signal of the second node P to a low level.

During the second period T2: the first clock signal terminal CLK1 changes from low level to high level, and the second switch element S2 is turned on by the signal at the first node Q, so as to pull up the signal at the first scan signal output terminal GOUT to high level, i.e., output the scan signal; the sixth switching element S6 is turned on by the signal of the first node Q to pull down the signal of the second node P to a low level.

During the third period T3: the signal of the second signal terminal fed is at a high level, the third switching element S3 is turned on by the signal of the second signal terminal fed to pull down the signal at the point Q of the first node to a low level, the second switching element S2 is turned on by the signal at the point Q of the first node, and the first scanning signal output terminal GOUT outputs a low level; the signal at the second clock terminal CLK2 is high, and the eighth switching element S8 is turned on by the signal at the second clock terminal CLK2 to keep the signal at the second node P low.

At a fourth time period T4: the first clock terminal CLK1 is at high level, and the seventh switching element S7 is turned on by the signal at the first clock terminal CLK1 to pull up the signal at the second node P to high level; the fourth switching element S4 is turned on by the signal of the second node P to pull down the signal of the first node Q to a low level.

At the fifth period T5: the signal at the second clock signal terminal CLK2 is at a high level, and the eighth switching element S8 is turned on by the signal at the second clock signal terminal CLK2 to pull down the signal at the second node P to a low level; the signal at the second signal terminal fed is at a high level, and the third switching element S3 is turned on by the signal at the second signal terminal fed, thereby pulling down the signal at the point Q of the first node to a low level.

In the embodiment of the present application, the seventh switching element S7 and the eighth switching element S8 are disposed at the pull-down maintaining module, and the existing first clock signal terminal CLK1 and second clock signal terminal CLK2 are utilized to alternately pull up and pull down the level of the signal in the second node P in the non-output stage of the shift register, so that the level of the signal in the second node P is alternately changed in the non-output stage, and the fourth switching element S4 and the fifth switching element S5 are prevented from being affected by the dc stress for a long time, so that the fourth switching element S4 and the fifth switching element S5 are deteriorated, which affects the service life of the shift register.

Example four

As shown in fig. 6, in the present embodiment, on the basis of the third embodiment, the first pull-down maintaining module 150 further includes:

the ninth switching element S9 is turned on by the signal of the first signal terminal INPUT to provide the signal of the fifth signal terminal VGH to the second node P.

In the third period T3, the signal of the first signal terminal INPUT is at a high level, the ninth switching element S9 is turned on by the signal of the first signal terminal INPUT, and pulls up the signal of the second node P to a high level, so that the third switching element S3 and the fifth switching element S5 are both turned on by the signal of the second node P, and the first node Q is pulled down jointly, so that the scan signal is changed to a low level quickly, and the falling delay of the scan signal is further reduced.

EXAMPLE five

As shown in fig. 7, in this embodiment, on the basis of the fourth embodiment, the first pull-down module 120 further includes:

and a tenth switching element S10, which is turned on by the signal at the first node Q to provide the signal at the first clock signal terminal CLK1 to the first cascade signal output terminal CARRY.

And a first end of the first capacitor C is connected with the first node Q, and a second end of the first capacitor C is connected with the first scanning signal output end GOUT and is used for charging and discharging.

In the second period T2, due to the coupling effect of the first capacitor C, the voltage of the signal at the first node Q is increased, so that the second switch element S2 is turned on more fully, and the high level of the signal at the first scan signal output terminal GOUT, i.e., the scan signal, is output.

The present embodiment is turned on by the tenth switching element S10 under the action of the signal at the first node Q, so as to provide the signal at the first clock signal terminal CLK1 to the first cascade signal output terminal CARRY, which can be used as the input signal of the shift register of other stages.

On the basis of the shift register circuit, the embodiment of the application also provides a gate driving circuit, wherein the gate driving circuit comprises a plurality of cascaded shift register circuits;

the first signal terminal INPUT of the nth stage shift register circuit is connected to the first scanning signal output terminal GOUT of the nth-m stage shift register circuit, the second signal terminal fed of the nth stage shift register circuit is connected to the first scanning signal output terminal GOUT of the (n + m) th stage shift register circuit, and the second clock signal terminal CLK2 of the nth stage shift register circuit is connected to the first clock signal terminal CLK1 of the nth-m stage shift register circuit.

Taking m ═ 4 as an example, as shown in fig. 8, the first signal terminal INPUT of the 5 th stage shift register circuit is connected to the first scanning signal output terminal GOUT of the 1 st stage shift register circuit, the second signal terminal FEED of the 5 th stage shift register circuit is connected to the first scanning signal output terminal GOUT of the 9 th stage shift register circuit, and the second clock signal terminal CLK2 of the 5 th stage shift register circuit is connected to the first clock signal terminal CLK1 of the 1 st stage shift register circuit.

It should be noted that, when the shift register circuit is the shift register circuit of the fourth embodiment, and the shift register circuit includes the first cascade signal output terminal CARRY, the first signal terminal INPUT of the nth stage shift register circuit is connected to the first cascade signal output terminal CARRY of the n-m stage shift register circuit, and the second signal terminal fed of the nth stage shift register circuit is connected to the first cascade signal output terminal CARRY of the n + m stage shift register circuit.

In the shift register in the gate driving circuit of the embodiment of the application, the existing first clock signal terminal CLK1 and second clock signal terminal CLK2 are used in the pull-down maintaining module, and the level of the signal in the second node P is alternately pulled up and pulled down in the non-output stage of the shift register, so that the level of the signal in the second node P is alternately changed in the non-output stage at a low modification cost, and the influence of the second pull-down module on the long-time direct-current stress and the influence on the service life of the shift register are avoided.

On the basis of the gate driving circuit, an embodiment of the present application further provides a display panel, where the display panel includes a pixel circuit, a source driving circuit, and a gate driving circuit.

As shown in fig. 9, the pixel circuit may include a plurality of gate lines (G1, G2, G3, G4 … …) and a plurality of data lines (D1, D2, D3, D4 … …) which are staggered laterally and longitudinally, and a plurality of pixel cells defined by adjacent gate lines and adjacent data lines: the gate lines are used for transmitting scanning signals provided by shift register circuits at all levels in the gate driving circuit, the data lines are used for transmitting data signals provided by a source driver, and a first scanning signal output end GOUT of the shift register unit is connected with a corresponding scanning line in the pixel circuit so as to provide scanning signals into the pixel circuit through the gate lines to turn on the TFT, thereby providing pixel gray scales to charge the pixels, enabling the pixel voltage to be equal to the data voltage, and ensuring that correct gray scales are displayed.

The display panel of the application can comprise any product or component with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator and the like.

It should be noted that although in the above detailed description several modules or circuits of the device for action execution are mentioned, such division is not mandatory. Indeed, the features and functions of two or more modules or circuits described above may be embodied in one module or circuit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or circuit described above may be further divided into embodiments by a plurality of modules or circuits.

Moreover, although the steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A shift register circuit comprises a first pull-up control module, a first node and a second pull-up control module, wherein the first pull-up control module is connected with a first signal end and the first node and is used for responding to a signal of the first signal end and providing a signal of the first signal end to the first node; the first pull-up module is connected with the first node, the first scanning signal output end and the first clock signal end and is used for responding to the signal of the first node and providing the signal of the first clock signal end to the first scanning signal output end; the first pull-down module is connected with a second signal end, a third signal end and the first node and used for responding to a signal of the second signal end and providing a signal of the third signal end to the first node; a second pull-down module, connected to the first node, the second node, the first scanning signal output terminal, the third signal terminal, and the fourth signal terminal, for providing a signal of the third signal terminal to the first node in response to a signal of the second node, and providing a signal of the fourth signal terminal to the first scanning signal output terminal in response to a signal of the second node; a first pull-down maintaining module connected to the first node, the second node, and the third signal terminal for providing a signal of the third signal terminal to the second node in response to a signal of the first node,

the first pull-down maintaining module is further connected to the first clock signal terminal, the second clock signal terminal, and configured to provide the signal of the first clock signal terminal to the second node in response to the signal of the first clock signal terminal, and provide the signal of the third signal terminal to the second node in response to the signal of the second clock signal terminal, so that the signal of the second node is changed alternately in the non-output stage of the shift register.

2. The shift register circuit of claim 1, wherein the first pull-down sustain module is further coupled to a fifth signal terminal for providing a signal of the fifth signal terminal to the second node in response to the signal of the first clock signal terminal.

3. The shift register circuit of claim 2, wherein the first pull-down maintaining module is further coupled to the first signal terminal for providing the signal of the fifth signal terminal to the second node in response to the signal of the first signal terminal.

4. The shift register circuit according to claim 2, wherein the first pull-up control block is further coupled to the fifth signal terminal for providing a signal of the fifth signal terminal to the first node in response to the signal of the first signal terminal.

5. The shift register circuit according to claim 2, wherein the first pull-up control block includes a first switching element, the first pull-up block includes a second switching element, the first pull-down block includes a third switching element, the second pull-down block includes a fourth switching element, a fifth switching element, the first pull-down maintaining block includes a sixth switching element, a seventh switching element, and an eighth switching element; wherein,

the second switching element is turned on by the signal of the first node to provide the signal of the first clock signal terminal to the first scan signal output terminal;

the eighth switch element is configured to be turned on by a signal of the second clock signal terminal, so as to provide a signal of the third signal terminal to the second node.

6. The shift register circuit according to claim 5, wherein the first pull-down sustaining module further comprises:

a ninth switching element, configured to be turned on by a signal of the second signal terminal to provide a signal of the fifth signal terminal to the second node.

7. The shift register circuit of claim 5, wherein the first pull-up module further comprises:

8. The shift register circuit of claim 5, wherein the first pull-up module further comprises:

9. A gate driver circuit, characterized in that the gate driver circuit comprises a plurality of shift register circuits according to any one of claims 1 to 8, the plurality of shift register circuits being cascaded;

10. The display panel is characterized by comprising a pixel circuit, wherein the pixel circuit comprises a plurality of grid lines and a plurality of data lines which are staggered transversely and longitudinally; a source driving circuit connected to the plurality of data lines in the pixel circuit; and a gate driving circuit as claimed in claim 9, connected to the plurality of gate lines in the pixel circuit.