CN216956764U

CN216956764U - Pin switching circuit and fault diagnosis device of OBD interface

Info

Publication number: CN216956764U
Application number: CN202122724105.XU
Authority: CN
Inventors: 马欢; 刘润泽; 马朔
Original assignee: Guangzhou Yousheng Automobile Technology Co ltd
Current assignee: Guangzhou Yousheng Automobile Technology Co ltd
Priority date: 2021-11-08
Filing date: 2021-11-08
Publication date: 2022-07-12
Anticipated expiration: 2031-11-08

Abstract

The embodiment of the application relates to a pin switching circuit and a fault diagnosis device of an OBD interface, which comprise a signal bus, wherein the signal bus is connected with a pin of the OBD interface; the first signal transceiver group is connected with the signal bus; the pin configuration array comprises a plurality of configuration bit groups, each configuration bit group comprises a plurality of configuration bits, and one end of each configuration bit in each configuration bit group is connected with a pin of the same OBD interface; and the other end of each configuration bit in each configuration bit group is connected with the second signal transceiver group so as to control whether signals are transmitted between the pins of the OBD interface and the second signal transceiver group. The vehicle fault diagnosis system can adapt to various vehicle fault diagnosis protocols and support simultaneous transmission of various different types of diagnosis signals to communicate with an OBD system of a vehicle.

Description

Pin switching circuit and fault diagnosis device of OBD interface

Technical Field

The utility model relates to the technical field of vehicle fault diagnosis, in particular to a pin switching circuit of an OBD (on-board diagnostics) interface and a fault diagnosis device.

Background

An On Board Diagnostics (OBD) is a detection system for monitoring whether an automobile has a fault or exhaust gas exceeds a standard. The vehicle-mounted diagnosis system is connected to an automobile Electronic Control Unit (ECU) through various emission-related component information, and the ECU has the function of detecting and analyzing emission-related faults. When an emission failure occurs, the ECU records failure information and related codes and gives a warning through a failure lamp to inform the driver.

"OBD II" is an abbreviation for "on Board diagnostics II", a type II on-Board diagnostic system. To standardize the diagnosis of vehicle emissions and driveability related failures, from 1996 on, all new vehicles sold in the united states had to comply with obdii procedures for diagnostic instrumentation, fault coding and repair procedures. With the increasing degree of economic globalization and automobile internationalization, the obdii system will be more and more widely implemented and applied as a driving and emission diagnosis basis.

The automobile OBD interface, namely the automobile diagnosis seat is an interface for connecting a decoder (a vehicle fault diagnosis device) with an ECU (electronic control unit) of the automobile, the automobile fault diagnosis device can check whether the automobile has a fault code and a fault record after being connected with the automobile diagnosis seat, and the automobile fault diagnosis device is connected with the automobile diagnosis seat to enable maintenance personnel to quickly judge the automobile fault and improve the maintenance efficiency.

However, in a practical situation, diagnostic protocols used by OBD systems of different vehicle types may be different, and pins of OBD interfaces corresponding to the protocols defined by different manufacturers using the same diagnostic protocol are also different, and when a vehicle needs to be repaired and diagnosed, the pins of the OBD interfaces corresponding to the diagnostic protocols used by the vehicle manufacturers need to be queried first, which increases the complexity of the work of maintenance personnel. In addition, some older models of OBD systems may use multiple different diagnostic protocols for communication, or the ECUs in the same OBD system may also use multiple different diagnostic protocols. The prior art OBD diagnostic connectors typically only support the use of one diagnostic protocol transceiver to communicate with the vehicle's OBD system, thereby providing inconvenience to the vehicle's diagnosis and repair.

SUMMERY OF THE UTILITY MODEL

Therefore, the utility model provides the pin switching circuit of the OBD interface and the fault diagnosis device, which can be adapted to various vehicle fault diagnosis protocols and provide convenience for diagnosis and maintenance of vehicles.

The utility model is realized by the following scheme:

a first aspect of an embodiment of the present invention provides a pin switching circuit of an OBD interface, including:

the signal bus is used for transmitting signals and is connected with pins of the OBD interface;

a first signal transceiver group for receiving or transmitting signals, the first signal transceiver group being connected to the signal bus;

a pin configuration array, wherein the pin configuration array comprises a plurality of configuration bit groups, each configuration bit group comprises a plurality of configuration bits, and one end of each configuration bit in each configuration bit group is connected with a pin of the same OBD interface; and

and the second signal transceiver group is used for receiving or sending signals, the other end of each configuration bit in each configuration bit group is connected with the second signal transceiver group, and each configuration bit is switched between on or off states so as to control whether signals are transmitted between the pins of the OBD interface and the second signal transceiver group.

The OBD interface further comprises a signal on-off module, wherein the signal on-off module is connected between a pin of the OBD interface and the signal bus; the signal on-off module switches between the on state and the off state to control whether a signal is transmitted between a pin of the OBD interface and the signal bus.

The first signal transceiver group is connected with the signal bus; the first channel on-off module is switched between an on state and an off state to control whether signals are transmitted between the first signal transceiver group and the signal bus.

Further, the signal bus comprises a first signal bus and a second signal bus;

the first channel on-off module is respectively connected with the first signal bus and the second signal bus;

the signal on-off module comprises a first signal on-off module and a second signal on-off module, the first signal on-off module comprises m first controlled switches, the m first controlled switches are respectively connected with pins of the m OBD interfaces, each first controlled switch is further connected with the first signal bus, and the first controlled switches are switched between on states and off states; the second signal on-off module comprises m second controlled switches, the m second controlled switches are respectively connected with the m pins of the OBD interface, each second controlled switch is further connected with the second signal bus, and m is larger than or equal to 1.

Further, the first signal transceiver group includes n first signal transceivers, each of which is connected to the first signal bus and the second signal bus, where n is greater than or equal to 1;

the first channel on-off module comprises 2n third controlled switches, and the third controlled switches are connected between the first signal bus and the first signal transceiver and/or the third controlled switches are connected between the second signal bus and the first signal transceiver; or the first channel on-off module comprises n two-way controlled switches, the two-way controlled switches are connected with the first signal bus and the second signal bus, the two-way controlled switches are further connected with the first signal transceiver, and the two-way controlled switches are switched between on states and off states.

Further, a second channel switching module, connected between the pin configuration array and the second signal transceiver group, switches between an on state and an off state to control whether a signal is transmitted between the pin configuration array and the second signal transceiver group.

Further, each of the configuration bit groups comprises x pairs of the configuration bits,

the second channel on-off module comprises x pairs of fourth controlled switches, the x pairs of fourth controlled switches are connected with the second signal transceiver group, and each pair of fourth controlled switches is also connected with the other end of one pair of configuration bits in each configuration bit group; or the second channel on-off module comprises x fifth controlled switches, the x fifth controlled switches are connected with the second signal transceiver group, each fifth controlled switch is also connected with the other end of one pair of configuration bits in each configuration bit group, and x is greater than or equal to 1.

Further, the second signal transceiver group comprises x second signal transceivers, wherein x is greater than or equal to 1;

the x pairs of fourth controlled switches are respectively connected with the x second signal transceivers in sequence; or the x fifth controlled switches are respectively connected with the x second signal transceivers in sequence.

Furthermore, the device also comprises a terminal resistance loading unit, wherein the terminal resistance loading unit comprises a switch unit and a terminal resistance connected with the switch unit; the terminal resistance loading unit is connected between the first signal transceiver group and the first channel on-off module, or the terminal resistance loading unit is connected between the first channel on-off module and the signal bus; and/or the terminal resistance loading unit is connected between the second signal transceiver group and the second channel on-off module, or the terminal resistance loading unit is connected between the second channel on-off module and the pin configuration array;

the switch unit is used for controlling the terminal resistor to be connected between the pin of the OBD interface and the first signal transceiver group so as to match signal transmission impedance; and/or the switch unit is used for controlling the terminal resistor to be connected between the pin of the OBD interface and the second signal transceiver group so as to match signal transmission impedance.

Further, the OBD interface device further comprises a single-wire CAN transceiver and a sixth controlled switch, wherein the single-wire CAN transceiver is connected to the corresponding pin of the OBD interface through the sixth controlled switch.

The control unit is used for sending a control signal to at least one of the first channel on-off module, the second channel on-off module, the signal on-off module, the terminal resistor loading unit and the multiplexer;

the multiplexer is connected with at least one of the first signal transceiver group, the second signal transceiver group and the single-wire CAN transceiver.

Further, a first power supply unit is also included; the first power supply unit comprises a first power supply voltage input end, a first power supply voltage output end and a first power supply control signal input end, and the first power supply control signal input end is connected with the control unit;

the first power supply voltage input end is connected with a first preset voltage, the first power supply voltage output end is connected with the second signal transceiver group and/or the multiplexer, and the first power supply voltage output end is used for outputting a second voltage.

Further, the first power supply unit further includes a first triode, a first MOS transistor, a first resistor and a first buck chip, the base of the first triode and the first power control signal input terminal are electrically connected, the collector of the first triode passes through the first resistor and the first power voltage input terminal are electrically connected, the collector of the first triode is further electrically connected with the gate of the first MOS transistor, the emitter of the first triode is electrically connected with the grounding terminal, the source of the first MOS transistor is electrically connected with the first power voltage input terminal, the drain of the first MOS transistor is electrically connected with the input terminal of the first buck chip, and the output terminal of the first buck chip is electrically connected with the first power voltage output terminal.

Further, a second power supply unit is also included; the second power supply unit comprises a second power supply voltage input end, a second power supply voltage output end and a second power supply control signal input end, and the second power supply control signal input end is connected with the control unit;

the second power supply voltage input end is connected with a third preset voltage, the second power supply voltage output end is connected with the first signal transceiver group and/or the second signal transceiver group, and the second power supply voltage output end is used for outputting a fourth voltage.

Further, the second power supply unit further includes a second triode, a second MOS transistor and a second resistor, the base of the second triode is electrically connected to the second power control signal input terminal, the collector of the second triode passes through the second resistor and the second power voltage input terminal, the collector of the second triode is also electrically connected to the gate of the second MOS transistor, the emitter of the second triode is electrically connected to the ground terminal, the source of the second MOS transistor is electrically connected to the second power voltage input terminal, and the drain of the second MOS transistor is connected to the second power voltage output terminal.

Furthermore, the second power supply unit further comprises a third MOS transistor, a gate of the third MOS transistor is electrically connected to a gate of the second MOS transistor, a source of the third MOS transistor is electrically connected to a source of the second MOS transistor, and a drain of the third MOS transistor is electrically connected to a drain of the second MOS transistor.

Further, the second power supply unit further comprises a third power supply voltage output end, the third power supply voltage output end is connected with the single-wire CAN transceiver and/or the terminal resistor loading unit, and the third power supply voltage output end is used for outputting a fifth voltage.

Furthermore, the second power supply unit further comprises a boost chip, an input end of the boost chip is electrically connected with a drain electrode of the second MOS transistor, and an output end of the boost chip is electrically connected with the third power supply voltage output end.

Further, the device also comprises a connecting element, wherein the connecting element is loaded on the configuration position so that two ends of the configuration position are communicated.

Further, the connection element is a resistor or a switch.

Further, the controlled switch includes an optocoupler.

Further, the first signal transceiver and/or the second signal transceiver comprises at least one of:

the CAN signal transceiver comprises a common CAN signal transceiver, a high-speed CAN signal transceiver, a medium-speed CAN signal transceiver and a low-speed CAN signal transceiver.

Furthermore, the device also comprises a CAN signal extension chip; the CAN signal extension chip is connected with the corresponding common CAN signal transceiver, and receives or processes signals sent by the common CAN signal transceiver.

A second aspect of the embodiments of the present invention provides a fault diagnosis device, including an OBD interface and a pin switching circuit of the OBD interface according to the first aspect of the embodiments of the present invention, where the OBD interface is connected to the pin switching circuit of the OBD interface.

According to the pin switching circuit of the OBD interface provided by the embodiment of the utility model, the configuration bits on the pin configuration array are preset to be in the on or off state, so that the on configuration bits can transmit vehicle signals. According to different signal transmission pins defined by different diagnostic protocols, configuration bits corresponding to the pins are conducted, and the pin configuration array can transmit different types of vehicle signals. Or the plurality of configuration bits on the pin configuration array are conducted to enable the pin configuration array to be connected with a plurality of signal transmission pins meeting the definition of different diagnostic protocol specifications, so that the pin configuration array can simultaneously transmit different types of vehicle signals. The pin configuration array may transmit the vehicle signals obtained from the pins to a second signal transceiver group, which may process the vehicle signals. The second signal transceiver group may also transmit the vehicle signal to the pins through the pin configuration array.

Based on the above beneficial effects, when manufacturing/testing/debugging/using the pin switching circuit of the OBD interface according to the embodiment of the present invention, a user or an employee may set one or some configuration bits on the pin configuration array to be in an on or off state according to different manufacturing/diagnostic/testing requirements, so as to meet different manufacturing/testing/debugging requirements, and enhance the flexibility of manufacturing/testing/debugging.

In addition, the vehicle signal output by the pin can be transmitted to the first signal transceiver group through the signal bus, and the first signal transceiver group can also transmit the vehicle signal to the pin through the signal bus. That is, in the pin switching circuit of the OBD interface according to the embodiment of the present invention, the vehicle signal acquired by the pin may be transmitted to the second signal transceiver group or the vehicle signal output by the second signal transceiver group may be transmitted to the pin through the pin configuration array connected to the pin of the OBD interface. Or the vehicle signal acquired by the pin can be sent to the first signal transceiver group through a signal bus connected with the pin of the OBD interface, or the vehicle signal output by the first signal transceiver group is transmitted to the pin. Or the vehicle signals output by the first signal transceiver group and/or the second signal transceiver group can be transmitted to the pins through the pin configuration array connection and the signal bus which are connected with the pins of the OBD interface in common, or the vehicle signals acquired by the pins are sent to the first signal transceiver group and/or the second signal transceiver group. That is, in other embodiments of the present invention, vehicle signals may be transmitted on both the pin configuration array and the signal bus simultaneously, and the first signal transceiver group and the second signal transceiver group may receive/transmit/process vehicle signals simultaneously. Therefore, when vehicle diagnosis or maintenance is carried out, the operation of a user is facilitated.

In another embodiment of the present invention, the pin switching circuit may further include a plurality of pairs of signal buses, the plurality of signal transceivers may communicate with different vehicle OBD systems through the plurality of pairs of signal buses, or the plurality of signal transceivers may communicate with a plurality of electronic control units applying different diagnostic protocols on the same vehicle through the plurality of pairs of signal buses, and communication transmission lines corresponding to each signal transceiver do not interfere with each other, which provides convenience for diagnosis and maintenance of the vehicle.

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Drawings

Fig. 1 is a schematic layout diagram of pins of an OBD interface in the prior art;

fig. 2 is a schematic structural diagram of a pin switching circuit of an OBD interface according to the present invention;

fig. 3 is a schematic structural diagram of a pin configuration array in a pin switching circuit of an OBD interface according to the present invention;

fig. 4 is a schematic circuit diagram of a terminal resistor loading unit of a pin switching circuit of an OBD interface according to the present invention;

fig. 5 is a schematic circuit diagram of a first power supply unit of a pin switching circuit of an OBD interface according to the present invention;

fig. 6 is a schematic circuit diagram of a second power supply unit of the pin switching circuit of the OBD interface according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be understood that the embodiments described are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the embodiments in the present application.

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the present application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the application, as detailed in the claims that follow. In the description of the present application, it is to be understood that the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not necessarily used to describe a particular order or sequence, nor are they to be construed as indicating or implying relative importance. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

Further, in the description of the present application, "a plurality" means two or more unless otherwise specified. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

As shown in fig. 1, fig. 1 is a schematic layout diagram of pins of an OBD interface in the prior art, where the

pins

1, 3, 6, 8, 9, 11, 12, 13, and 14 can be customized according to the actual conditions of a manufacturer; pin 2 is SAE J1850 signal bus positive pole; pin 10 is SAE J1850 signal bus negative pole; the pin 4 is grounded for the chassis; the pin 5 is grounded; the pin 7 is a K line; the pin 15 is an L line; the 16-pin is a constant power positive electrode.

The utility model provides a pin switching circuit of an OBD (on-board diagnostics) interface, which is applied to a vehicle fault diagnosis device. The vehicle fault diagnosis device can obtain fault codes, fault records and the like of the vehicle from the automobile diagnosis seat. In some embodiments, the vehicle fault diagnosis device may further provide a fault code query function, or the vehicle fault diagnosis device may further be in signal connection with an intelligent terminal such as a mobile phone or a tablet, so as to implement the above function under remote control of the intelligent terminal, and send the acquired diagnosis data to the intelligent terminal.

As shown in fig. 2, fig. 2 is a schematic structural diagram of a pin switching circuit of an OBD interface according to an embodiment of the present invention. The pin switching circuit comprises a first signal transceiver group, a second signal transceiver group, a first channel on-off module, a second channel on-off module, a pin configuration array, a first signal on-off module, a second signal on-off module, a first signal bus 146, a second signal bus 132, a terminal resistance loading unit U22, a multiplexing module, a control unit A, a first power supply unit 30 and a second power supply unit 40.

Specifically, the first signal transceiver group includes n first signal transceivers, and in fig. 2, the first signal transceiver group includes 3 first signal transceivers, including a high-speed CAN transceiver U26, a low-speed CAN signal transceiver U25, and a single-wire CAN transceiver U24, respectively. Wherein the first signal transceiver may receive/transmit vehicle data complying with a preset vehicle diagnostic protocol specification. The pin switching circuit can read the diagnostic information of the ECU of the automobile or write the information such as configuration or parameters into the automobile diagnostic seat.

In particular, the first signal transceiver will typically comprise two signal lines for transmitting vehicle signals, which are connected to two signal buses one by one, respectively, or which may each be connected to two signal buses one by one via a third controlled switch or a two-way controlled switch. After the vehicle signal is output to the pin switching circuit of the embodiment of the utility model by the vehicle-mounted system of the vehicle, the pin of the OBD interface can output the vehicle signal to the first signal transceiver through the first controlled switch, the second controlled switch, the signal bus and the third controlled switch, and vice versa. In the process, in the process that the vehicle signal is output from one of the first signal transceivers to the pin of the OBD interface, or in the process that the vehicle signal is output from the pin of the OBD interface to one of the first signal transceivers, transmission lines through which the vehicle signal passes, and the pin of the OBD interface, the first controlled switch, the second controlled switch, the third controlled switch, the first signal transceiver, and the like distributed on the transmission lines form channels, wherein each channel comprises two signal transmission lines.

In an embodiment of the present invention, each of the first signal transceivers in the first signal transceiver group is connected to its corresponding channel, and each channel includes two differential signal transmission lines of a high level and a low level. Each second signal transceiver in the second signal transceiver group is connected with a corresponding channel, and each channel also comprises two differential signal transmission lines of high level and low level. In the embodiment of the present invention, taking the high-speed CAN transceiver U26 as an example, two signal lines thereof are respectively connected to the first signal bus 146 and the second signal bus 132; and may be connected to corresponding pins on OBD interface 10 via first signal bus 146 and second signal bus 132.

The channel on-off module comprises a first channel on-off module and a second channel on-off module. The first channel switching module is used to control whether the first signal transceiver set is connected to both the first signal bus 146 and the second signal bus 132, and the second channel switching module is used to control whether the second signal transceiver set is connected to the pin configuration array 50. In this embodiment, the first channel switching module is used to control whether each signal transceiver in the first signal transceiver group is connected to the first signal bus 146 and the second signal bus 132, and the second channel switching module is used to control whether each signal transceiver in the second signal transceiver group is connected to the corresponding configuration bit in the pin configuration array 50.

In fig. 2, the first channel switching module and the second channel switching module each comprise a plurality of two-way relays. Specifically, the first channel on-off module comprises a relay K51 and a relay K53, and the second channel on-off module comprises a relay K55, a relay K57 and a relay K59, wherein each relay independently controls on-off between a channel of a signal transceiver correspondingly connected with the relay and a signal bus. In other embodiments, the channel switching module may further include 2n or 2x controlled switches, and the pair of controlled switches respectively controls the switching of the corresponding signal lines, or the channel switching module may also be formed by combining the controlled switches and the relays.

In the embodiment of the present invention, each pin of the OBD interface 10 is connected to the first signal bus 146 through a first signal switching module, and each pin of the OBD interface 10 is further connected to the second signal bus 132 through a second signal switching module, where the first signal switching module can respectively control switching of connection between each pin of the OBD interface 10 and the first signal bus 146, and the second signal switching module can respectively control switching of connection between each pin of the OBD interface 10 and the second signal bus 132.

Specifically, the first signal on-off module includes m first controlled switches, which respectively control on-off of pins of corresponding m OBD interfaces and the first signal bus 146, and the second signal on-off module also includes m second controlled switches, which respectively control on-off of pins of corresponding m OBD interfaces and the second signal bus 132, where m is greater than 1.

The first channel on-off module comprises 2n third controlled switches, the third controlled switches are connected between the first signal bus 146 and the first signal transceiver group, and/or the third controlled switches are connected between the second signal bus 132 and the first signal transceiver group; or the first channel on-off module comprises n two-way controlled switches, the two-way controlled switches are connected with the first signal bus 146 and the second signal bus 132, the two-way controlled switches are further connected with the first signal transceiver, and the two-way controlled switches are switched between an on state and an off state.

The second signal transceiver group comprises x second signal transceivers, and in fig. 2, the second signal transceiver group comprises 3 second signal transceivers, namely a normal CAN transceiver U20, a normal CAN transceiver U21, and a normal CAN transceiver U23. Different from the connection mode of the first signal transceiver with the corresponding pin on the OBD interface 10 through the signal bus, the second signal transceiver is connected with the corresponding pin on the OBD interface 10 through the pin configuration array.

Referring specifically to fig. 3, an exemplary circuit schematic of the pin array 50 is shown. The pin configuration array 50 includes a plurality of configuration bit groups, each configured bit group including x pairs of configuration bits.

The second channel on-off module comprises x pairs of fourth controlled switches, the x pairs of fourth controlled switches are connected with the second signal transceiver group, and each pair of controlled switches is also connected with the other end of one pair of configuration bits in each configuration bit group; or the second channel on-off module comprises x fifth controlled switches, the x fifth controlled switches are connected with the second signal transceiver group, each fifth controlled switch is also connected with the other end of one pair of configuration bits in each configuration bit group, and x is greater than or equal to 1. The one end of each configuration bit communicates with a pin that the OBD interface corresponds jointly, and the other end communicates with second signal transceiver group respectively, and the configuration bit is used for installing connecting element, install connecting element back OBD interface the pin will with signal line intercommunication, in concrete implementation connecting element can choose for use resistance, switch etc. can switch on the electronic component of circuit.

Specifically, the pin configuration array 50 enables the vehicle fault diagnosis device to perform diagnosis communication with the OBD system according to the required OBD diagnosis protocol only by determining the pins of the OBD interface 10 and the signal lines of the corresponding channels according to the type of the required OBD diagnosis protocol and then placing the connection element device on the configuration bit where the determined OBD pins and the signal lines are connected together.

In fig. 2, the second signal transceiver group specifically includes a normal CAN signal transceiver U20, a normal CAN signal transceiver U21, and a normal CAN signal transceiver U23; the first signal transceiver group includes a high speed CAN signal transceiver U26 and a low speed CAN signal transceiver U25. In addition, a single-wire CAN transceiver U24 is also included, wherein the single-wire CAN transceiver U24 is not connected to the signal bus, but is directly connected to the corresponding pin of the OBD interface 10, and in fig. 2, the single-wire CAN transceiver U24 is specifically connected to pin 1.

In the embodiments of the present invention, the type and number of signal transceivers are not limited, and in some other embodiments, the signal transceivers include, but are not limited to: high-speed CAN signal transceiver, medium-speed CAN signal transceiver, low-speed/fault-tolerant CAN signal transceiver, Kwp Protocol transceiver (ISO14230), SAE J1708 Protocol transceiver, SAE J1850-PWM Protocol transceiver, SAE J1850-VPW Protocol transceiver, FlexRay Protocol transceiver, SAE J2284 Protocol transceiver, ISO9141Ford Protocol transceiver, UART Protocol transceiver, ISO 9141-2 Protocol transceiver, CARB Protocol transceiver, DCL UART Protocol transceiver, UBP Protocol transceiver, DDL UART Protocol transceiver, SCP Protocol transceiver, General Motors (GM)8192 Protocol transceiver, etc.

In the embodiment of fig. 2, the m first controlled switches of the first signal switching module are specifically optical couplers 21, the m second controlled switches of the second signal switching module are specifically optical couplers 22, and in fig. 2, the single-wire CAN transceiver U24 is also connected to the corresponding pin 1 of the OBD interface 10 through an optical coupler 23. The optical coupler can be electrically controlled, the input and the output are mutually isolated, and the electrical signal transmission has the characteristics of unidirectionality and the like, so that the optical coupler has good electrical insulation capacity and interference resistance. In other embodiments, the controlled switch may also be a relay, a switch chip, or the like.

In the embodiment of the present invention, the signal bus is illustrated by taking CAN signal bus as an example, for example, the first signal bus 146 and the second signal bus 132 may be a 132 signal bus and a 146 signal bus of the CAN signal bus, respectively. In some other embodiments, the signaling bus types include, but are not limited to, a CAN signaling bus, a LIN signaling bus, and a VAN signaling bus, which may be determined according to the particular diagnostic protocol transmitted in the line.

In some preferred embodiments, the number of the signal buses may also be not limited to two, and the signal switching modules may also be not limited to two, and there may be more than two switching modules corresponding to more than two signal buses, so as to implement signal transmission of more diagnostic protocols.

In the example of fig. 2, the termination resistance loading unit U22 is further connected to channels of the normal CAN signal transceiver U20, the normal CAN signal transceiver U21, the normal CAN signal transceiver U23 and the high-speed CAN signal transceiver U26, respectively, and the termination resistance loading unit U22 CAN control two ends of the termination resistance to be connected across two transmission lines of the corresponding channel. In addition, the relay K1 CAN control the two ends of the terminal resistor to be connected across two transmission lines in the channel of the low-speed CAN transceiver U26.

Specifically, the signal transceiver includes two signal lines for transmitting vehicle signals, and the two signal lines are connected to two signal buses one by one, or the two signal lines can be connected to the two signal buses one by one through a third controlled switch or a two-way controlled switch. After the vehicle signal is output to the pin switching circuit of the embodiment of the utility model by the vehicle-mounted system of the vehicle, the pin of the OBD interface can output the vehicle signal to the signal transceiver through the first controlled switch, the second controlled switch, the signal bus, the third controlled switch or the two-way controlled switch, and vice versa. In the process, transmission lines through which the vehicle signals pass in the process of outputting the vehicle signals from one of the signal transceivers to the pins of the OBD interface or in the process of outputting the vehicle signals from the pins of the OBD interface to one of the signal transceivers form channels, wherein each channel comprises two signal transmission lines, and the pins of the OBD interface, the first controlled switch, the second controlled switch, the third controlled switch or the two-way controlled switch, the signal transceivers and the like distributed on the transmission lines form the channels.

Specifically, as shown in fig. 4, fig. 4 is a schematic circuit structure diagram of the termination resistance loading unit, the termination resistance loading unit U22 includes a switch chip KN1 and a plurality of termination resistors connected thereto, and the number of the termination resistors is the same as the number of the signal transceivers connected thereto. The switch chip KN1 includes a plurality of sub-switch circuits each including two input/output terminals. Optionally, in each sub-switch circuit, one of the input/output terminals is connected to a terminating resistor, which is further connected to one of the transmission lines of one of the channels, and the other input/output terminal is connected to another transmission line of the same channel.

When the sub-switch circuit is conducted, two ends of the terminal resistor connected with the sub-switch circuit are respectively connected with two transmission lines in a channel connected with the sub-switch circuit. Therefore, the terminal resistor can absorb signal reflection and echo, eliminate interference in the signal transmission process, realize impedance matching of a channel and improve the anti-interference performance and reliability of signal transmission.

In this embodiment, the normal CAN transceiver U20, the normal CAN transceiver U21, the normal CAN transceiver U23, and the high-speed CAN transceiver U26 are connected to the terminating resistor loading unit U22, and the terminating resistor loading unit U22 is further connected to the relay K53, the relay K55, the relay K57, and the relay K59, respectively. In order to implement normal diagnostic communication (usually communication in the CAN protocol), the termination resistor loading unit U22 may connect a termination resistor to two communication lines of the channel where the transceiver is located, so as to implement normal communication. If the pin switching circuit of this embodiment is applied to the diagnostic device, the switch chip KN1 is switched to an off state or an on state, and two ends of the termination resistor may be connected to two transmission lines of corresponding channels, respectively, so as to meet the requirements on the physical layer bus in the diagnostic protocol specification. If the other circuits of the diagnostic device have a terminating resistor, the switching chip KN1 can be switched off, and the terminating resistor is not connected to the corresponding channel. The termination resistance loading unit U22 enables the OBD pin switching circuit to be adapted to a variety of diagnostic equipment.

As shown in fig. 2, the channel of the low-speed CAN transceiver U25 is connected to the first signal bus 146 and the second signal bus 132 through the relay K51, respectively. The terminating resistance loading unit U22 further includes a relay K1 and a terminating resistance connected to the relay K1. The relay includes two input/output terminals, one of which is connected to one end of a terminating resistor (not shown), the other end of which is connected to one of the transmission lines in the channel in which the low-speed CAN transceiver U25 is located, and the other input/output terminal is connected to the other transmission line in the channel in which the low-speed CAN transceiver U25 is located. By controlling the switching of the relay K1 between the on state and the off state, whether the terminal resistor is connected in two transmission lines of the channel where the low-speed CAN transceiver U25 is located CAN be controlled, and therefore whether the impedance matching function of the channel where the low-speed CAN transceiver U25 is located needs to be achieved CAN be controlled.

As shown in fig. 2, in the present embodiment, the CAN signal extension chip further includes a CAN signal extension chip U16 and a CAN signal extension chip U18; the CAN signal expansion chip U16 is connected with a common CAN signal transceiver U20, and the CAN signal expansion chip U18 is connected with a common CAN signal transceiver U21.

In fig. 2, the multiplexing module includes a multiplexer U17 and a multiplexer U19, the multiplexer U17 is connected to the normal CAN transceiver U23 and the single-wire CAN transceiver U24, and the multiplexer U19 is connected to the high-speed CAN transceiver U26 and the low-speed CAN transceiver U25.

The multiplexer U17 and the multiplexer U19 are further connected with the control unit A respectively, and the CAN signal extension chip U16 and the CAN signal extension chip U18 are further connected with the control unit A respectively.

The control unit a serves as a control core of the vehicle failure diagnosis device, and is used for driving the signal transceiver in the above embodiment to communicate with an on-board system on the vehicle, and acquiring a vehicle failure diagnosis code from an ECU of the vehicle. In this embodiment, the control unit a is also configured to turn on and off the above-described components such as the switch chip KN1, the optocoupler, and the relay. The control unit A can also output control signals to the relay and the optical coupler through the FPGA, the register, the latch and the like. The control unit A includes but is not limited to one or any combination of MCU, MPU, DPU, CPU, ASIC, etc.

The pin switching circuit of the present invention further includes a first power supply unit 30 and a second power supply unit 40, as shown in fig. 2, the first power supply unit 30 includes a first power supply voltage input terminal 31, a first power supply voltage output terminal 33, and a first power supply control signal input terminal 32, wherein the first power supply control signal input terminal 32 is connected to the control unit a.

The first power voltage input terminal 31 is connected to a first preset voltage, optionally, the first power voltage input terminal 31 is connected to a 5V regulated power supply, where the 5V regulated power supply may be a power supply generated inside the vehicle fault diagnosis device itself, and may also be a power supply converted from a 12V power supply obtained by an OBD interface from a vehicle diagnosis seat, in the embodiment of fig. 2, the first power voltage output terminal 33 is used to output a 3.3V voltage, and the first power voltage output terminal 33 is electrically connected to the U16 CAN signal expansion chip, the U18 CAN signal expansion chip, the U17 multiplexer, and the U19 multiplexer, respectively, and supplies power to the above components.

As shown in fig. 2 and 5, the first power unit 30 further includes a first transistor Q3, a first MOS transistor Q2, a first resistor R41, a resistor R42 and a first buck chip U11, a base of the first transistor Q3 is electrically connected to the first power control signal input terminal 32, a collector of the first transistor Q3 is electrically connected to the first power voltage input terminal 31 through the first resistor R41 and the resistor R42, a collector of the first transistor Q3 is also electrically connected to a gate of the first MOS transistor Q2 through the resistor R42, an emitter of the first transistor Q3 is electrically connected to a ground terminal, a source of the first MOS transistor Q2 is electrically connected to the first power voltage input terminal 31, a drain of the first MOS transistor Q2 is electrically connected to an input terminal of the first buck chip U11, and an output terminal of the first buck chip U11 is electrically connected to the first power voltage output terminal 33.

In the embodiment of the present invention, the first power control signal input terminal 32 is controlled by a GPIO of the MPU of the control unit a, and is used for controlling whether the first power unit 30 outputs the voltage or not by controlling the first MOS transistor Q2 and the first transistor Q3, when the first power control signal input terminal 32 is at a high level, the emitter and the collector of the first transistor Q3 are turned on, so that the source and the drain of the first MOS transistor Q2 are turned on, the first power voltage output terminal 33 outputs the second voltage, and specifically, the first power voltage output terminal 33 outputs the 5V voltage. When the first power control signal input terminal 32 is at a low level, the first transistor Q3 is turned off, such that the first MOS transistor Q2 is turned off, and the first power voltage output terminal 33 stops outputting the 5V voltage.

As shown in fig. 2, the second power supply unit 40 includes a second power supply voltage input terminal 41, a second power supply voltage output terminal 43, and a second power supply control signal input terminal 42, and the second power supply control signal input terminal 42 is connected to the control unit a.

The second power voltage input terminal 41 is connected to a third preset voltage, optionally, the second power voltage input terminal 41 is connected to a 5V regulated power supply, and the second power voltage output terminal 43 is configured to output a fourth voltage, specifically, the second power voltage output terminal 43 is configured to output a 5V voltage. The second power voltage output end 43 is connected with a U20 common CAN signal transceiver, a U21 common CAN signal transceiver, a U23 common CAN signal transceiver, a U26 high-speed CAN signal transceiver and a U25 low-speed CAN signal transceiver, and is used for providing power for the above components.

As shown in fig. 2 and 6, the second power unit 40 further includes a second transistor Q5, a second MOS transistor Q4 and a second resistor R46, wherein a base of the second transistor Q5 is electrically connected to the second power control signal input terminal 42, a collector of the second transistor Q5 is electrically connected to the second power voltage input terminal 41 through a second resistor R46, a collector of the second transistor Q5 is further electrically connected to a gate of the second MOS transistor Q4, an emitter of the second transistor Q5 is electrically connected to a ground terminal, a source of the second MOS transistor Q6 is electrically connected to the second power voltage input terminal 41, and a drain of the second MOS transistor Q4 is connected to the second power voltage output terminal 43.

Preferably, in order to increase the redundancy of the second power supply unit, the second power supply unit further includes a third MOS transistor Q6 connected in parallel with the second MOS transistor Q4, a gate of the third MOS transistor Q6 is electrically connected to a gate of the second MOS transistor Q5, a source of the third MOS transistor Q6 is electrically connected to a source of the second MOS transistor Q5, and a drain of the third MOS transistor Q6 is electrically connected to a drain of the second MOS transistor Q5.

The second power supply unit 40 further comprises a third supply voltage output 44, the third supply voltage output 44 being connected to the single-wire CAN transceiver U24 and the termination resistance loading unit U22, the third supply voltage output 44 being for outputting a fifth voltage, optionally the third supply voltage output 44 being for outputting a voltage of 8V.

The second power unit 40 further includes a boost chip U12, an input terminal of the boost chip U12 is electrically connected to the drain of the second MOS transistor Q5, and an output terminal of the boost chip U12 is electrically connected to the third power voltage output terminal 44.

In the embodiment of the present invention, the second power control signal input terminal 42 is also controlled by a GPIO of the MPU of the control unit a, and is configured to control the output voltages of the second power voltage output terminal 43 and the third power voltage output terminal 44 of the second power unit 40 by controlling the first transistor Q5, the second MOS transistor Q4, and the third MOS transistor Q6, when the second power control signal input terminal 42 is at a high level, the emitter and the collector of the second transistor Q5 are turned on, so that the source and the drain of the second MOS transistor Q4 are turned on, the source and the drain of the third MOS transistor Q6 are turned on, the second power voltage output terminal 43 outputs a 5V voltage, and the third power voltage output terminal 44 outputs an 8V voltage; when the second power control signal input terminal 42 is at a low level, the second transistor Q5 is turned off, so that the second MOS transistor Q4 and the third MOS transistor Q6 are turned off, the second power voltage output terminal 43 stops outputting the 5V voltage, and the third power voltage output terminal 44 stops outputting the 8V voltage.

Taking the pin 11 and the pin 3 as examples, the working principle of the pin switching circuit of the OBD interface according to the embodiment of the present invention is described: the control unit A respectively controls the conduction of the optical coupler 22 of the pin 11 connected with the second signal bus 132, the conduction of the optical coupler 21 of the pin 3 connected with the first signal bus 146, the conduction of the relay K53 and the control of the U22 terminal resistance loading unit to be connected with the terminal resistance connected with the relay K53 and the U26 high-speed CAN transceiver in parallel. The electrical signals at the

pins

11 and 3 CAN be transmitted to the multiplexer U19 along the channel connecting the relay K53, the U22 terminal resistor loading unit, and the U26 high-speed CAN transceiver, and then transmitted to the control unit a.

In a specific application scenario, if three different diagnostic protocols are applied to the on-board OBD system of the vehicle, in order to communicate with the on-board OBD system for reading and writing data, the diagnostic device is required to support the three or more different diagnostic protocols to communicate with the on-board OBD system, or to support the simultaneous use of multiple different diagnostic protocols to communicate with the on-board OBD system. One diagnostic protocol typically uses two signal lines, and three different diagnostic protocols typically require six signal lines. Therefore, the relay K1 and the optical coupler in the embodiment of the present invention may conduct the corresponding diagnostic signal channels according to the diagnostic requirement, and the OBD pins used by each diagnostic signal channel are different. Taking the simultaneous transmission of three diagnostic signals as an example, in six signal lines of the three diagnostic signals, the transmission of the multiple diagnostic signals can be realized without using the same OBD pin for any two lines or multiple lines.

If 3 channels need to be communicated simultaneously, the mutual occupation of 6 pins corresponding to 3 diagnostic protocols in the OBD interface should not exist. After the conditions are met, the optical couplers of 6 lines of 3 diagnosis protocols are conducted or the corresponding relays K1 are conducted, 3 paths of diagnosis signals can further enter the signal transceiver for processing, and the signal transceiver sends the processed signals to the control unit.

Corresponding to the pin switching circuit of an OBD interface, an embodiment of the present application further provides a vehicle fault diagnosis device, including an OBD interface, and the pin switching circuit of an OBD interface as in any of the above embodiments, where the OBD interface is connected with the pin switching circuit of the OBD interface.

According to the pin switching circuit of the OBD interface provided by the embodiment of the utility model, the configuration bits on the pin configuration array are preset to be in the on or off state, so that the on configuration bits can transmit vehicle signals. According to different signal transmission pins defined by different diagnostic protocols, configuration bits corresponding to the pins are conducted, and the pin configuration array can transmit different types of vehicle signals. Or the plurality of configuration bits on the pin configuration array are conducted to be connected with a plurality of signal transmission pins meeting the definition of different diagnostic protocol specifications, so that the pin configuration array can simultaneously transmit different types of vehicle signals. The pin configuration array may transmit the vehicle signals obtained from the pins to a second signal transceiver group, which may process the vehicle signals. The second signal transceiver group may also transmit the vehicle signal to the pins through the pin configuration array.

In addition, the vehicle signal output by the pin can be transmitted to the first signal transceiver group through the signal bus, and the first signal transceiver group can also transmit the vehicle signal to the pin through the signal bus. That is, in the pin switching circuit of the OBD interface according to the embodiment of the present invention, the vehicle signal output from the pin may be transmitted to the second signal transceiver group or the vehicle signal output from the second signal transceiver group may be transmitted to the pin through the pin arrangement array connected to the pin of the OBD interface. Or the vehicle signal output by the pin can be sent to the first signal transceiver group through a signal bus connected with the pin of the OBD interface, or the vehicle signal output by the first signal transceiver group is transmitted to the pin. Or the vehicle signal output by the first signal transceiver group and/or the second signal transceiver group may be transmitted to the pins or the vehicle signal output by the pins may be transmitted to the first signal transceiver group and/or the second signal transceiver group through the pin configuration array connection and the signal bus which are commonly connected with the pins of the OBD interface. Therefore, when vehicle diagnosis or maintenance is carried out, the operation of a user is facilitated.

It is to be understood that the embodiments of the present application are not limited to the precise arrangements described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the embodiments of the present application is limited only by the following claims.

The above-mentioned embodiments only express a few embodiments of the present application, and the description thereof is specific and detailed, but not construed as limiting the scope of the utility model. It should be noted that, for those skilled in the art, variations and modifications can be made without departing from the concept of the embodiments of the present application, and these embodiments are within the scope of the present application.

Claims

1. A pin switching circuit of an OBD interface, comprising:

2. The pin switching circuit of the OBD interface of claim 1, wherein:

the OBD interface further comprises a signal on-off module, wherein the signal on-off module is connected between the pins of the OBD interface and the signal bus; the signal on-off module switches between on or off states to control whether signals are transmitted between the pins of the OBD interface and the signal bus.

3. The pin switching circuit of the OBD interface of claim 2, wherein:

the first channel on-off module is connected between the signal bus connection and the first signal transceiver group; the first channel on-off module is switched between an on state and an off state to control whether signals are transmitted between the first signal transceiver group and the signal bus.

4. The pin switching circuit of the OBD interface of claim 3, wherein:

the signal buses comprise a first signal bus and a second signal bus;

the signal on-off module comprises a first signal on-off module and a second signal on-off module, the first signal on-off module comprises m first controlled switches, the m first controlled switches are respectively connected with pins of the m OBD interfaces, each first controlled switch is further connected with the first signal bus, and the first controlled switches are switched between on or off states; the second signal on-off module comprises m second controlled switches, m second controlled switches are respectively connected with m pins of the OBD interface, each second controlled switch is also connected with the second signal bus, and m is larger than or equal to 1.

5. The pin switching circuit of the OBD interface of claim 4, wherein:

the first signal transceiver group comprises n first signal transceivers, each of the first signal transceivers is connected with the first signal bus and the second signal bus, wherein n is greater than or equal to 1;

the first channel on-off module comprises 2n third controlled switches, and the third controlled switches are connected between the first signal bus and the first signal transceiver and/or the third controlled switches are connected between the second signal bus and the first signal transceiver; or the first channel on-off module comprises n two-way controlled switches, the two-way controlled switches are connected with the first signal bus and the second signal bus, the two-way controlled switches are also connected with the first signal transceiver, and the two-way controlled switches are switched between on states and off states.

6. The pin switching circuit of the OBD interface of claim 4, further comprising:

and the second channel on-off module is connected between the pin configuration array and the second signal transceiver group and is switched between an on state and an off state so as to control whether a signal is transmitted between the pin configuration array and the second signal transceiver.

7. The pin switching circuit of the OBD interface of claim 6, wherein:

each of said configuration bit groups comprising x pairs of said configuration bits,

8. The pin switching circuit of the OBD interface of claim 7,

the second signal transceiver group comprises x second signal transceivers, wherein x is greater than or equal to 1;

9. The pin switching circuit of the OBD interface of claim 6, wherein:

the terminal resistor loading unit comprises a switch unit and a terminal resistor connected with the switch unit; the terminal resistance loading unit is connected between the first signal transceiver group and the first channel on-off module, or the terminal resistance loading unit is connected between the first channel on-off module and the signal bus; and/or the terminal resistance loading unit is connected between the second signal transceiver group and the second channel on-off module, or the terminal resistance loading unit is connected between the second channel on-off module and the pin configuration array;

10. The pin switching circuit of the OBD interface of claim 9, wherein:

still include single-wire CAN transceiver and sixth controlled switch, the single-wire CAN transceiver passes through the sixth controlled switch is connected to corresponding the pin of OBD interface.

11. The pin switching circuit of the OBD interface of claim 10, wherein:

12. The pin switching circuit of the OBD interface of claim 11, wherein:

further comprising a first power supply unit; the first power supply unit comprises a first power supply voltage input end, a first power supply voltage output end and a first power supply control signal input end, and the first power supply control signal input end is connected with the control unit;

13. The pin switching circuit of the OBD interface of claim 12, wherein:

the first power supply unit further comprises a first triode, a first MOS (metal oxide semiconductor) tube, a first resistor and a first voltage reduction chip, the base of the first triode is electrically connected with the first power control signal input end, the collector of the first triode passes through the first resistor and the first power voltage input end, the collector of the first triode is also electrically connected with the grid of the first MOS tube, the emitter of the first triode is electrically connected with the grounding end, the source of the first MOS tube is electrically connected with the first power voltage input end, the drain of the first MOS tube is electrically connected with the input end of the first voltage reduction chip, and the output end of the first voltage reduction chip is electrically connected with the first power voltage output end.

14. The pin switching circuit of the OBD interface of claim 11, wherein:

further comprising a second power supply unit; the second power supply unit comprises a second power supply voltage input end, a second power supply voltage output end and a second power supply control signal input end, and the second power supply control signal input end is connected with the control unit;

15. The pin switching circuit of the OBD interface of claim 14, wherein:

the second power supply unit further comprises a second triode, a second MOS (metal oxide semiconductor) tube and a second resistor, the base of the second triode is electrically connected with the second power supply control signal input end, the collector of the second triode passes through the second resistor and the second power supply voltage input end, the collector of the second triode is also electrically connected with the grid electrode of the second MOS tube, the emitter of the second triode is electrically connected with the grounding end, the source of the second MOS tube is electrically connected with the second power supply voltage input end, and the drain of the second MOS tube is connected with the second power supply voltage output end.

16. The pin switching circuit of the OBD interface of claim 15, wherein:

the second power supply unit further comprises a third MOS tube, the grid electrode of the third MOS tube is electrically connected with the grid electrode of the second MOS tube, the source electrode of the third MOS tube is electrically connected with the source electrode of the second MOS tube, and the drain electrode of the third MOS tube is electrically connected with the drain electrode of the second MOS tube.

17. The pin switching circuit of the OBD interface of claim 16, wherein:

the second power supply unit further comprises a third power supply voltage output end, the third power supply voltage output end is connected with the single-wire CAN transceiver and/or the terminal resistor loading unit, and the third power supply voltage output end is used for outputting a fifth voltage.

18. The pin switching circuit of the OBD interface of claim 17, wherein:

the second power supply unit further comprises a boosting chip, the input end of the boosting chip is electrically connected with the drain electrode of the second MOS tube, and the output end of the boosting chip is electrically connected with the third power supply voltage output end.

19. The pin switching circuit of the OBD interface of any of claims 1-18, wherein:

the connecting element is loaded on the configuration position, so that two ends of the configuration position are communicated.

20. The pin switching circuit of the OBD interface of claim 19, wherein:

the connecting element is a resistor or a switch.

21. The pin switching circuit of the OBD interface of any of claims 4-18, wherein:

the controlled switch includes an optocoupler.

22. The pin switching circuit of the OBD interface of any of claims 1-18, wherein:

the first signal transceiver and/or the second signal transceiver comprises at least one of:

23. The pin switching circuit of the OBD interface of claim 22, wherein:

the CAN signal extension chip is also included; the CAN signal extension chip is connected with the corresponding common CAN signal transceiver, and receives or processes signals sent by the common CAN signal transceiver.

24. A failure diagnosis device characterized by comprising:

an OBD interface;

and pin switching circuitry of an OBD interface according to any of claims 1-23, the OBD interface being connected to the pin switching circuitry of the OBD interface.