CN216929562U - Digital power failure self-locking protection circuit - Google Patents
Digital power failure self-locking protection circuit Download PDFInfo
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- CN216929562U CN216929562U CN202220223017.3U CN202220223017U CN216929562U CN 216929562 U CN216929562 U CN 216929562U CN 202220223017 U CN202220223017 U CN 202220223017U CN 216929562 U CN216929562 U CN 216929562U
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Abstract
The utility model provides a digital power supply fault self-locking protection circuit which comprises a fault detection unit, a reset unit and a fault processing unit, wherein the fault detection unit is used for acquiring and processing the voltage of a digital power supply and obtaining a voltage comparison result according to a processed voltage signal; and the fault processing unit is used for receiving the voltage comparison result and the reset signal and outputting an enable signal to enable ends of the plurality of control lines according to the voltage comparison result or the voltage comparison result and the reset signal. The digital power supply fault self-locking protection circuit provided by the utility model can quickly and accurately lock the fault state of the digital power supply and control each element in a subsequent control circuit to stop working, and each element in the protection circuit and the digital power supply are not damaged.
Description
Technical Field
The utility model relates to the technical field of circuits, in particular to a digital power supply fault self-locking protection circuit.
Background
When the digital power supply fails, elements in the control circuit, such as elements in a hardware circuit and a single chip microcomputer, can be damaged if the failure cannot be quickly and accurately identified and each element in a subsequent control circuit is controlled to stop working, and even the digital power supply can be damaged.
Therefore, how to improve the above disadvantages and shortcomings to better meet the needs of usage is a technical problem to be solved by those skilled in the art.
SUMMERY OF THE UTILITY MODEL
The utility model mainly aims to solve the problems and the defects and provides a digital power supply fault self-locking protection circuit which can quickly lock the fault state of a digital power supply and control each element in a subsequent control circuit to stop working, can be reset after the fault is eliminated and has high reliability.
In order to achieve the purpose, the utility model provides a digital power failure self-locking protection circuit, which adopts the technical scheme that:
a digital power supply fault self-locking protection circuit comprises a fault detection unit, a reset unit and a fault processing unit, wherein the fault detection unit is used for acquiring and processing the voltage of a digital power supply and obtaining a voltage comparison result according to a processed voltage signal; and the fault processing unit is used for receiving the voltage comparison result and the reset signal and outputting an enable signal to enable ends of a plurality of control lines according to the voltage comparison result or the voltage comparison result and the reset signal.
Further, the fault detection unit comprises a voltage processing unit and a comparator, wherein the voltage processing unit is used for acquiring and processing the voltage of the digital power supply, the output end of the voltage processing unit is connected with the non-inverting input end of the comparator, the voltage processing unit is used for inputting the processed voltage signal into the comparator, the comparator is used for receiving the voltage signal, obtaining a voltage comparison result according to the received voltage signal, and inputting the voltage comparison result into the fault processing unit.
Furthermore, the fault processing unit comprises a JK trigger and a multi-path enabling circuit, wherein a J input end of the JK trigger is connected with an output end of the comparator, a K input end of the JK trigger is connected with an output end of the reset unit, a Q output end of the JK trigger is connected with the multi-path enabling circuit, an output end of the multi-path enabling circuit is connected with enabling ends of the control lines, and the multi-path enabling circuit outputs enabling signals according to the level of the input end.
Further, the comparator compares the voltage signal input by the non-inverting input terminal with the reference voltage input by the inverting input terminal, determines whether the digital power supply has a fault according to the level output by the comparator, and correspondingly outputs a high/low level to the J input terminal.
Further, when the voltage signal is greater than the reference voltage, a digital power failure is judged, the comparator outputs a high level, the Q output end outputs a high level, the JK trigger latches the output state of the Q output end into a high level state, and the output ends of the plurality of paths of enable circuits output low levels.
Further, when the K input end receives a high level input by the reset unit and the J input end is a low level, the output state of the Q output end is reset to a low level state, and the output ends of the plurality of paths of enable circuits output a high level.
Furthermore, the enabling circuit at least comprises a hardware enabling circuit and/or a singlechip enabling circuit, the hardware enabling circuit comprises a first triode, a first current limiting resistor and a first pull-up resistor, and the singlechip enabling circuit comprises a second triode, a second current limiting resistor and a second pull-up resistor; one path of a Q output end of the JK trigger is connected with a base electrode of a first triode through a first current limiting resistor, a collector electrode of the first triode is connected with a first high potential through a first pull-up resistor, and an emitting electrode of the first triode is grounded; the other path of the Q output end of the JK trigger is connected with a base electrode of a second triode through a second current limiting resistor, a collector electrode of the second triode is connected with a second high potential through a second pull-up resistor, and an emitter electrode of the second triode is grounded; the output end of the first high potential is connected with the enabling end of the hardware circuit through a first pull-up resistor, and the output end of the second high potential is connected with the enabling end of the single chip microcomputer through a second pull-up resistor.
Furthermore, the reset unit includes an or gate, and a hardware reset signal and a single chip microcomputer reset signal are respectively input to two input ends of the or gate.
Further, the voltage processing unit comprises a voltage acquisition module for acquiring digital power supply voltage, a compensation voltage module for outputting compensation voltage and an in-phase adder which are connected in parallel; the voltage acquisition module and the voltage compensation module are respectively connected with the in-phase input end of the in-phase adder through a first resistor and a second resistor, the output end of the in-phase adder is connected with the in-phase input end of the comparator, and the output voltage of the voltage acquisition module and a voltage signal generated after the compensation voltage is processed are output to the comparator.
Furthermore, the output end of the in-phase adder is connected with the inverting input end of the in-phase adder through a third resistor, and the inverting input end of the in-phase adder is grounded through a fourth resistor.
In summary, compared with the prior art, the digital power failure self-locking protection circuit provided by the utility model has the following technical advantages:
(1) the voltage of the digital power supply is collected and processed through the voltage processing unit, the processed voltage signal is input into the comparator, the voltage signal is compared with the reference voltage through the comparator to obtain a voltage comparison result, the voltage comparison result is input into the fault processing unit, the fault processing unit outputs an enabling signal according to the received voltage comparison result and the reset signal, so that fault information is detected quickly and accurately, the on-off of the digital power supply, the control circuit and the singlechip are controlled, and elements in the control circuit, the singlechip and the digital power supply are protected from being damaged when the digital power supply fails;
(2) when a digital power supply fails, the input level of the J input end of the JK trigger is high level, the output state of the Q output end of the JK trigger is latched to be high level state through the JK trigger, the hardware enabling signal and the single chip enable signal are both low level, each element of the hardware circuit and the single chip stop working, the elements in the hardware circuit and the single chip are prevented from continuously running under the condition that the digital power supply fails, the safety of the hardware circuit and the single chip is ensured, and the reliability of the digital power supply in application is improved;
(3) when the fault is cleared, the input level of the J input terminal of the JK flip-flop is switched to the low level, but before the arrival of the reset signal, that is, before the high level signal is not received by the K input terminal of the JK flip-flop, the Q output terminal of the JK flip-flop still outputs the high level, each element of the hardware circuit and the single chip microcomputer still are in the state of stopping working, only when one or both of the hardware reset signal and the single chip microcomputer reset signal are output in the high level, the output state of the Q output end of the JK trigger is reset to be in a low level state, the enable signals output by the hardware enable circuit and the single chip enable circuit are in a high level state, all elements in the hardware circuit and the single chip start to work, and when the digital power supply fault is not completely eliminated or other problems exist, the potential safety hazard brought by directly starting each element and the single chip microcomputer further improves the reliability of the digital power supply in application.
Description of the drawings:
FIG. 1: the utility model discloses a schematic diagram of a digital power failure self-locking protection circuit;
FIG. 2: the utility model relates to a circuit diagram of a digital power failure self-locking protection circuit
The fault detection circuit comprises a fault detection unit 1, a voltage acquisition module 101, a compensation voltage module 102, a fault processing unit 2, a hardware enabling circuit 201, a single-chip microcomputer enabling circuit 202, a reset unit 3, an in-phase adder U1, a comparator U2, an OR gate U3, a JK trigger U4, an output voltage V1 of the voltage acquisition module, a compensation voltage V2, a voltage signal V3, a reference voltage Vref, a first high-potential VDD1, a second high-potential VDD2, a hardware reset signal EL1, a single-chip microcomputer reset signal EL2, a hardware enabling signal EL3, a single-chip microcomputer enabling signal EL4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first pull-up resistor R5, a first pull-up resistor R6, a second current-limiting resistor R7, a second pull-up resistor R8, a first triode Q1 and a second triode Q2.
Detailed Description
The utility model is described in further detail below with reference to the following figures and detailed description.
The utility model provides a digital power supply fault self-locking protection circuit, which comprises a fault detection unit 1, a reset unit 3 and a fault processing unit 2, wherein the fault detection unit 1 is used for acquiring and processing the voltage of a digital power supply and obtaining a voltage comparison result according to a processed voltage signal, the reset unit 3 is used for acquiring a reset signal, the fault processing unit 2 is connected with the output end of the fault detection unit 1, the output end of the reset unit 3 is connected with the second input end of the fault processing unit 2, and the output end of the fault processing unit 2 is connected with the enabling ends of a plurality of control lines; and the fault processing unit 2 is used for receiving the voltage comparison result and the reset signal and outputting an enable signal to enable ends of the plurality of control lines according to the voltage comparison result or the voltage comparison result and the reset signal.
The embodiment provides a digital power supply fault self-locking protection circuit, which reflects whether a digital power supply has a fault or not through the voltage of the digital power supply, so that the on-off of the digital power supply and a plurality of control circuits is controlled, the start/stop of each element and a single chip microcomputer in the control circuits is controlled, and the safe operation of each element and the single chip microcomputer in the control circuits is ensured.
As shown in fig. 1 and fig. 2, the digital power failure self-locking protection circuit provided by this embodiment includes a failure detection unit 1, where the failure detection unit 1 includes a voltage acquisition module 101, a compensation voltage module 102, and an in-phase adder U1, the voltage acquisition module 101 acquires voltage of a digital power supply, an output end of the voltage acquisition module 101 is connected with a non-inverting input end of a non-inverting adder U1 through a first resistor R1, the compensation voltage module 102 is used for calculating and outputting a compensation voltage V2, an output end of the compensation voltage module 102 is connected with a non-inverting input end of a non-inverting adder U1 through a second resistor R2, an output end of a non-inverting adder U1 is connected with an inverting input end of the non-inverting adder U1 through a third resistor R3, an inverting input end of the non-inverting adder U1 is grounded through a fourth resistor, and an output voltage V1 and a compensation voltage V2 of the voltage acquisition module are processed by the non-inverting adder U1 to obtain a voltage signal V3 input to the non-inverting input end of the comparator U2. In this embodiment, the voltage acquisition module 101 may adopt a hall sensor to acquire the voltage of the digital power supply, the output voltage of the hall sensor is the acquired current digital power supply voltage, and in practical application, any other existing or future voltage acquisition device may be adopted to acquire the digital power supply voltage. The comparator U2 compares the value of the voltage signal V3 with the value of the reference voltage Vref input from the inverting input terminal of the comparator U2 after receiving the voltage signal V3, and outputs the comparison result, when the voltage signal V3 is greater than the reference voltage Vref, the digital power supply voltage fault is determined, and the output terminal of the comparator U2 outputs a high level; when the voltage signal V3 is smaller than the reference voltage Vref, it is determined that the digital power supply voltage is normal, the output terminal of the comparator U2 outputs a low level, and the comparator U2 outputs the comparison result to the first input terminal of the fault handling unit 2.
The fault processing unit 2 comprises a JK trigger U4, a hardware enabling circuit 201 and a single chip enable circuit 202, an output end of a comparator U2 is connected with a J input end of a JK trigger U4, a Q output end of the JK trigger U4 is divided into two paths which are respectively connected with an input end of the hardware enabling circuit 201 and an input end of the single chip enable circuit 202, an output end of the hardware enabling circuit 201 and an output end of the single chip enable circuit 202 are respectively connected with an enabling end of a hardware circuit and an enabling end of a single chip, the hardware enabling circuit 201 and the single chip enable circuit 202 output a hardware enabling signal EL3 and a single chip enable signal EL4 according to the level of the respective input ends, the hardware enabling signal EL3 is output to the enabling end of the hardware circuit, the single chip enable signal EL4 is output to the enabling end of the single chip, wherein the enabling end of the hardware circuit is arranged on a controller of the hardware circuit, and the controller controls the start/stop of each element in the hardware circuit according to the level received by the controller And the singlechip controls the singlechip to start/stop working according to the level received by the enable end of the singlechip. When the hardware enable signal EL3 is in a high level, each element in the hardware circuit starts to work, and when the hardware enable signal EL3 is in a low level, each element in the hardware circuit stops working; when the single-chip enable signal EL4 is at low level, the single-chip starts working, and when the single-chip enable signal EL4 is at low level, the single-chip stops working.
It should be noted that, in practical application, the fault processing unit 2 may set multiple enabling circuits as required, an input end of the enabling circuit is connected to a Q output end of the JK flip-flop, an output end of the enabling circuit is connected to an enabling end of a circuit to be controlled, and the enabling circuit may output an enabling signal for controlling a component to start/stop working according to a level of the input end, so as to control on/off between the digital power supply and a line to be controlled by the enabling circuit, and ensure safety of each component in the line.
Further, the hardware enabling circuit 201 includes a first triode Q1, a first current-limiting resistor R5 and a first pull-up resistor R6, one path of the Q output terminal of the JK flip-flop U4 is connected to the base of the first triode Q1 through the first current-limiting resistor R5, the collector of the first triode Q1 is connected to the first high-potential VDD1 through the first pull-up resistor R6, the emitter of the first triode Q1 is grounded, and the output terminal of the first high-potential VDD1 is connected to the enabling terminal of the hardware circuit through the first pull-up resistor R6; the single chip enabling circuit 202 comprises a second triode Q2, a second current limiting resistor R7 and a second pull-up resistor R8, the other path of the Q output end of the JK trigger is connected with the base of a second triode Q2 through a second current limiting resistor R7, the collector of the second triode Q2 is connected with a second high potential VDD2 through the second pull-up resistor R8, the emitter of the second triode Q2 is grounded, and the output end of the second high potential VDD2 is connected with the enabling end of the single chip through the second pull-up resistor R8. When the Q output end of the JK trigger U4 is at a low level, the first triode Q1 and the second triode Q2 are both in a cut-off state, and the hardware enabling signal EL3 and the single-chip microcomputer enabling signal EL4 are both at a high level; when the Q output end of the JK flip-flop U4 is at a high level, the first transistor Q1 and the second transistor Q2 are both in a conducting state, the first high potential VDD1 flows into the collector of the first transistor Q1 through the first pull-up resistor R6, and is grounded through the emitter of the first transistor Q1, at this time, the hardware enable signal EL3 is at a low level, the second high potential VDD2 flows into the collector of the second transistor Q2 through the second pull-up resistor R8, and is grounded through the emitter of the second transistor Q2, and at this time, the one-chip enable signal EL4 is at a low level.
Further, the digital power failure self-locking protection circuit provided by this embodiment further includes a reset unit 3, the reset unit 3 includes an or gate U3, two input terminals of the or gate respectively input a hardware reset signal EL1 and a single chip microcomputer reset signal EL2, an output terminal of the or gate U3 is connected to a K input terminal of the JK flip-flop U4, after the digital power failure is eliminated, a reset signal may be sent to the K input terminal of the JK flip-flop U4, one of the hardware reset signal EL1 and the single chip microcomputer reset signal EL2 is at a high level, or both the two reset signals are at a high level, the or gate U3 outputs a high level to the K input terminal of the JK flip-flop U4, and when the J input terminal of the JK flip-flop U4 is at a low level and the K input terminal of the JK flip-flop U4 is at a high level, the JK flip-flop U4 resets an output state of the Q output terminal to a low level state.
When the digital power supply works, the digital power supply fault self-locking protection circuit provided by the embodiment detects the voltage of the digital power supply in real time, and outputs a hardware enable signal EL3 and a single-chip enable signal EL4 according to the detection result, so that the start/stop work of each element and the single-chip in a hardware circuit is controlled.
When the voltage of the digital power supply is normal, the output voltage V1 of the voltage acquisition module and the compensation voltage V2 are processed by the in-phase adder U1 to obtain a voltage signal V3, and the voltage signal V3 is input to the in-phase input end of the comparator U2, at this time, the voltage signal V3 at the in-phase input end of the comparator U2 is smaller than the reference voltage Vref at the anti-phase input end, the output end of the comparator U2 outputs a low level, the J input end of the JK flip-flop U4 receives a low level signal, the Q output end of the JK flip-flop U4 outputs a low level, and transmits the low level signal to the hardware enabling circuit 201 and the single chip enable circuit 202, at this time, the first triode Q1 and the second triode Q2 are both in a cut-off state, the hardware enabling signal EL3 and the single chip enable signal EL4 are both at a high level, after the enable end of the hardware circuit receives the high level signal, the controller of the hardware circuit controls each element in the hardware circuit to start up, and after the enable end of the singlechip receives the high-level signal, the singlechip starts to work.
When a voltage signal V3 of a non-inverting input end of a comparator U2 is larger than a reference voltage Vref of an inverting input end, a digital power supply voltage fails, an output end of a comparator U2 outputs a high level, a J input end of a JK trigger U4 receives a high level signal, a Q output end of a JK trigger U4 outputs a high level, and a JK trigger U4 latches the output state of the Q output end into a high level state, at the moment, a first triode Q1 and a second triode Q2 are both in a conducting state, a hardware enabling signal EL3 and a single chip enable signal EL4 are both in a low level, after the enabling end of a hardware circuit receives the low level signal, a controller of the hardware circuit controls elements in the hardware circuit to stop working, after the enabling end of the single chip receives the low level signal, the single chip also stops working, and the elements in the hardware circuit are prevented from continuing to operate under the state of the digital power supply failure, the safety of hardware circuits and the single chip microcomputer is guaranteed, and the reliability of the digital power supply in application is improved.
When the digital power supply fault is eliminated, the output voltage V1 of the voltage acquisition module is recovered to be normal, the voltage signal V3 of the non-inverting input end of the comparator U2 is smaller than the reference voltage Vref of the inverting input end, the output end of the comparator U2 outputs a low level, the J input end of the JK trigger U4 receives a low level signal, but when the digital power supply fault occurs, the JK trigger U4 latches the output state of the Q output end to be a high level state, if the reset unit 3 does not acquire any reset signal at the moment, the Q output end of the JK trigger U4 still outputs a high level, the hardware enable signal EL3 and the single chip enable signal EL4 are both low levels, and all elements of a hardware circuit and the single chip are still in a state of stopping working. At this time, the digital power supply needs to be manually checked, when it is determined that the digital power supply fault is indeed eliminated and no other problem exists, the hardware enable signal EL3 and the single chip enable signal EL4 are manually input, when the reset unit 3 acquires a reset signal, namely one or both of the hardware enable signal EL3 and the single chip enable signal EL4 are at a high level, the or gate U3 outputs a high level signal to the K input terminal of the JK flip-flop U4, the Q output terminal of the JK flip-flop U4 is reset to a low level state, the hardware enable signal EL3 output by the hardware enable circuit 201 is restored to a high level, the single chip enable signal EL4 output by the single chip enable circuit 202 is also restored to a high level, after the enable terminal of the hardware circuit receives the high level signal, the controller of the hardware circuit controls each element in the hardware circuit to start working, and after the enable terminal of the single chip receives the high level signal, the singlechip starts to work. After the digital power supply fault is eliminated, a hardware enabling signal EL3 and a single chip microcomputer enabling signal EL4 are not directly turned to be high level, manual check is needed to be carried out on the digital power supply again, only after the fact that the digital power supply fault is eliminated really is confirmed, the Q output end of the JK trigger U4 is reset to be low level through inputting a reset signal, therefore, the hardware enabling signal EL3 and the single chip microcomputer enabling signal EL4 are controlled to be turned to be high level, all elements and the single chip microcomputer in a hardware circuit are started, potential safety hazards caused by directly starting all the elements and the single chip microcomputer when the digital power supply fault is not completely eliminated or other problems exist are avoided, and the reliability of the digital power supply in application is further improved.
In summary, compared with the prior art, the digital power failure self-locking protection circuit provided by the utility model has the following technical advantages:
(1) the voltage of the digital power supply is collected and processed through the voltage processing unit, the processed voltage signal is input into the comparator, the voltage signal is compared with the reference voltage through the comparator to obtain a voltage comparison result, the voltage comparison result is input into the fault processing unit, the fault processing unit outputs an enabling signal according to the received voltage comparison result and the reset signal, so that fault information is detected quickly and accurately, the on-off of the digital power supply, the control circuit and the singlechip are controlled, and elements in the control circuit, the singlechip and the digital power supply are protected from being damaged when the digital power supply fails;
(2) when a digital power supply fails, the input level of the J input end of the JK trigger is high level, the output state of the Q output end of the JK trigger is latched to be high level state through the JK trigger, the hardware enabling signal and the single chip enable signal are both low level, each element of the hardware circuit and the single chip stop working, the elements in the hardware circuit and the single chip are prevented from continuously running under the condition that the digital power supply fails, the safety of the hardware circuit and the single chip is ensured, and the reliability of the digital power supply in application is improved;
(3) when the fault is cleared, the input level of the J input terminal of the JK flip-flop is switched to the low level, but before the arrival of the reset signal, that is, before the high level signal is not received by the K input terminal of the JK flip-flop, the Q output terminal of the JK flip-flop still outputs the high level, each element of the hardware circuit and the single chip microcomputer still are in the state of stopping working, only when one or both of the hardware reset signal and the single chip microcomputer reset signal are output in the high level, the output state of the Q output end of the JK trigger is reset to be in a low level state, the enable signals output by the hardware enable circuit and the single chip enable circuit are in a high level state, all elements in the hardware circuit and the single chip start to work, and when the digital power supply fault is not completely eliminated or other problems exist, the potential safety hazard brought by directly starting each element and the single chip microcomputer further improves the reliability of the digital power supply in application.
Similar solutions can be derived as described above in connection with the given solution content. However, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the present invention are within the scope of the technical solution of the present invention.
Claims (10)
1. A digital power failure self-locking protection circuit is characterized in that: the digital power supply voltage monitoring system comprises a fault detection unit, a reset unit and a fault processing unit, wherein the fault detection unit is used for acquiring and processing the voltage of a digital power supply and obtaining a voltage comparison result according to a processed voltage signal; and the fault processing unit is used for receiving the voltage comparison result and the reset signal and outputting an enable signal to enable ends of a plurality of control lines according to the voltage comparison result or the voltage comparison result and the reset signal.
2. The digital power failure self-locking protection circuit as claimed in claim 1, wherein: the fault detection unit comprises a voltage processing unit and a comparator, wherein the voltage processing unit is used for acquiring and processing the voltage of a digital power supply, the output end of the voltage processing unit is connected with the non-inverting input end of the comparator, the voltage processing unit inputs a processed voltage signal into the comparator, the comparator is used for receiving the voltage signal, obtaining a voltage comparison result according to the received voltage signal and inputting the voltage comparison result into the fault processing unit.
3. The digital power failure self-locking protection circuit as claimed in claim 2, wherein: the fault processing unit comprises a JK trigger and a multi-path enabling circuit, wherein the J input end of the JK trigger is connected with the output end of the comparator, the K input end of the JK trigger is connected with the output end of the reset unit, the Q output end of the JK trigger is connected with the multi-path enabling circuit, the multi-path enabling circuit is connected with the multiple enabling ends of the control circuit, and the multiple enabling circuits output enabling signals according to the level of the input end.
4. A digital power failure self-locking protection circuit as claimed in claim 3, wherein: the comparator compares the voltage signal input by the non-inverting input end with the reference voltage input by the inverting input end, judges whether the digital power supply has faults or not according to the level output by the comparator, and correspondingly outputs high/low level to the J input end.
5. The digital power failure self-locking protection circuit as claimed in claim 4, wherein: when the voltage signal is greater than the reference voltage, a digital power supply fault is judged, the comparator outputs a high level, the Q output end outputs a high level, the JK trigger latches the output state of the Q output end into a high level state, and the output ends of the plurality of paths of enabling circuits output low levels.
6. The digital power failure self-locking protection circuit as claimed in claim 4, wherein: when the K input end receives a high level input by the reset unit and the J input end is a low level, the output state of the Q output end is reset to be a low level state, and the output ends of the multiple paths of enable circuits output high levels.
7. A digital power failure self-locking protection circuit as claimed in claim 3, wherein: the enabling circuit at least comprises a hardware enabling circuit and/or a singlechip enabling circuit, the hardware enabling circuit comprises a first triode, a first current limiting resistor and a first pull-up resistor, and the singlechip enabling circuit comprises a second triode, a second current limiting resistor and a second pull-up resistor;
one path of a Q output end of the JK trigger is connected with a base electrode of a first triode through a first current limiting resistor, a collector electrode of the first triode is connected with a first high potential through a first pull-up resistor, and an emitting electrode of the first triode is grounded; the other path of the Q output end of the JK trigger is connected with a base electrode of a second triode through a second current limiting resistor, a collector electrode of the second triode is connected with a second high potential through a second pull-up resistor, and an emitter electrode of the second triode is grounded;
the output end of the first high potential is connected with the enabling end of the hardware circuit through a first pull-up resistor, and the output end of the second high potential is connected with the enabling end of the single chip microcomputer through a second pull-up resistor.
8. The digital power failure self-locking protection circuit as claimed in claim 7, wherein: the reset unit comprises an OR gate, and a hardware reset signal and a singlechip reset signal are respectively input into two input ends of the OR gate.
9. The digital power failure self-locking protection circuit as claimed in claim 2, wherein: the voltage processing unit comprises a voltage acquisition module for acquiring digital power supply voltage, a compensation voltage module for outputting compensation voltage and an in-phase adder which are connected in parallel; the voltage acquisition module and the voltage compensation module are respectively connected with the in-phase input end of the in-phase adder through a first resistor and a second resistor, the output end of the in-phase adder is connected with the in-phase input end of the comparator, and the output voltage of the voltage acquisition module and a voltage signal generated after the compensation voltage is processed are output to the comparator.
10. The digital power failure self-locking protection circuit as claimed in claim 9, wherein: the output end of the in-phase adder is connected with the inverting input end of the in-phase adder through a third resistor, and the inverting input end of the in-phase adder is grounded through a fourth resistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220223017.3U CN216929562U (en) | 2022-01-27 | 2022-01-27 | Digital power failure self-locking protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220223017.3U CN216929562U (en) | 2022-01-27 | 2022-01-27 | Digital power failure self-locking protection circuit |
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| CN216929562U true CN216929562U (en) | 2022-07-08 |
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