CN216901639U - Digital radio frequency memory - Google Patents

Abstract

The application discloses digital radio frequency memory, includes: the device comprises an ADC (analog-to-digital converter), a DAC (digital-to-analog converter), an FPGA (field programmable gate array), a static random access memory SRAM (static random access memory), a clock and a power supply; the clock is connected with the ADC converter and the DAC converter and used for providing working clock signals. The application solves the technical problem that a DRFM equipment framework in the prior art cannot meet the requirements of miniaturization and low power consumption.

Description

Digital radio frequency memory

Technical Field

The application relates to the technical field of digital signal processing, in particular to a digital radio frequency memory.

Background

The Digital Radio Frequency Memory (DRFM) technology is characterized in that a digital form is used as a way of storing signal information, signals can be sampled at high speed, i.e. Radio frequency and microwave signals can be reproduced quickly, and interference signals are matched with radar signals because of the duplication of the radar original signals. The electronic interference to the radar is mainly to receive the space radar signal through DRFM, then to store, then to modulate and process into specific interference signal, finally to transmit the interference signal to interfere the radar.

The conventional DRFM device or module mostly adopts a standard industrial architecture, and a Compact Peripheral Component Interconnect (CPCI) architecture and a VPX architecture are mostly adopted, and although the architectures have unique advantages in terms of universality, the architectures must meet the unified applicability requirement of the standard architecture, so that the size, weight and power consumption of the DRFM device of both the CPCI architecture and the VPX architecture cannot meet the application requirements in more and more miniaturized low-power consumption fields.

Typical DRFM products adopt a standard industrial architecture, the size design is limited by standards, and cannot be well integrated into the miniaturized design field, and meanwhile, the power consumption often reaches more than 30W (the power consumption of the VPX architecture even reaches 50W), while in more and more application fields, the total power consumption is only about 30W, which also causes that the conventional DRFM module is difficult to reduce the power consumption and is applicable to the miniaturized electronic application field. Moreover, the standard industrial architecture itself will impose an additional cost burden on the product design, and generally, the additional cost generated by the compatible standard is about 30% of the total cost of the product, so the system cost can be effectively controlled by designing the miniaturized DRFM module.

Aiming at the technical problem that the DRFM equipment architecture in the prior art cannot meet the requirements of miniaturization and low power consumption, an effective solution is not provided at present.

Disclosure of Invention

The embodiment of the application provides a digital radio frequency memory, which is used for at least solving the technical problem that the DRFM equipment architecture in the prior art cannot meet the requirements of miniaturization and low power consumption.

According to an aspect of an embodiment of the present application, there is provided a digital radio frequency memory, including: the device comprises an ADC (analog-to-digital converter), a DAC (digital-to-analog converter), an FPGA (field programmable gate array), a static random access memory SRAM (static random access memory), a clock and a power supply;

the clock is connected with the ADC converter and the DAC converter and used for providing working clock signals.

Based on any of the above embodiments, the ADC converter is of the type EV10AQ 190.

On the basis of any one of the above embodiments, the analog signal input end of the ADC is connected to the subminiature version SMA interface, a pi-type attenuator is provided between the analog signal input end and the SMA interface, and a balancer Balun is provided between the pi-type attenuator and the SMA interface, for converting the input signal from the SMA interface into a differential signal to implement impedance matching.

On the basis of any embodiment, the model number adopted by the DAC converter is AD9739 BBCZ.

On the basis of any one of the above embodiments, the model number adopted by the FPGA is Kirtex 7 series XC7K325T

On the basis of any one of the above embodiments, a source synchronous receiving mode is adopted for the sampled data transmission between the FPGA and the ADC converter, and the working mode of the ADC converter is a DES mode.

On the basis of any of the above embodiments, the FPGA connects two independent SRAMs, specifically the quadruple data rate QDRII SRAM.

On the basis of any of the above embodiments, QDRII SRAM adopts model CY7C15632KV 18.

On the basis of any of the above embodiments, the interface between the FPGA and the ADC converter, the interface between the FPGA and the DAC converter, and the interface between the FPGA and the SRAM all use local clock networks.

On the basis of any one of the above embodiments, the power supply adopts an EMI filter for dividing the linear power output by the power supply and separately supplying power to each ADC converter and DAC converter.

In the embodiment of the present application, a digital radio frequency memory may be provided, which includes an ADC converter, a DAC converter, an FPGA, a static random access memory SRAM, a clock, and a power supply; the clock is connected with the ADC, the DAC, the FPGA and the SRAM and used for providing a working clock signal, and therefore the technical problem that a DRFM device framework in the prior art cannot meet requirements of miniaturization and low power consumption is solved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

FIG. 1 is a block diagram of a hardware architecture of a digital RF memory according to an embodiment of the present application;

FIG. 2 is a schematic diagram of the internal structure of an EV10AQ190 in accordance with an embodiment of the present application;

FIG. 3 is a circuit diagram of an ADTL2-18 application according to an embodiment of the present application;

FIG. 4 is a circuit diagram of a capacitive coupling according to an embodiment of the present application;

FIG. 5 is a diagram of an SMA single-ended access circuit according to an embodiment of the application;

fig. 6 is a block diagram of an internal structure of an AD9739BBCZ according to an embodiment of the present application;

FIG. 7 is a schematic diagram of SFDR versus sampling rate according to an embodiment of the present application;

fig. 8 is a front-end analog circuit diagram of an AD9739BBCZ in accordance with an embodiment of the present application;

FIG. 9 is a schematic diagram of the circuit connection of ADCLK914 according to an embodiment of the present application;

figure 10 is a resource information diagram for XC7K325T according to an embodiment of the present application;

FIG. 11 is a schematic diagram of an output timing of an ADC converter according to an embodiment of the present application;

FIG. 12 is a schematic diagram of an internal interface logic structure of an FPGA according to an embodiment of the present application;

FIG. 13 is a schematic diagram of a digital input interface for an AD9739BBCZ in accordance with an embodiment of the present application;

FIG. 14 is a schematic output timing diagram of an FPGA according to an embodiment of the present application;

FIG. 15 is a schematic interface diagram of an FPGA according to an embodiment of the present application;

FIG. 16 is a schematic diagram illustrating the pin connections between QDRI I SRAM and an FPGA according to an embodiment of the present application;

FIG. 17 is a schematic diagram of a core architecture according to an embodiment of the present application;

FIG. 18 is a block diagram of another hardware configuration of a digital RF memory according to an embodiment of the present application;

FIG. 19 is a graphical illustration of a PSRR curve according to an embodiment of the present application;

FIG. 20 is a schematic diagram of a digital RF memory panel according to an embodiment of the present application.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The embodiment of the application provides a digital radio frequency memory, and the hardware structure of the digital radio frequency memory can be as shown in fig. 1.

The digital radio frequency memory 10 may include: an ADC (analog-to-Digital Conversion) converter 11, a DAC (Digital-to-analog Conversion) converter 12, an FPGA (Field Programmable Gate Array) 13, an SRAM (Static Random-Access Memory) 14, a clock 15, and a power supply 16; the clock 15 is connected to the ADC converter 11 and the DAC converter 12 for providing an operation clock signal.

In an alternative arrangement, the ADC converter is of the type EV10AQ 190. The maximum sampling clock of the EV10AQ190 can reach 2.5GHz, the sampling bit number is 10bits, the internal four ADC cores perform interleaved sampling, and the sampling rate can reach 5.0G. The main technical indexes of the EV10AQ190 are as follows:

sampling precision is 10 Bits;

Power 5.65W(typ)；

Full Power Bandwidth3.0GHz(typ)；

ENOB 8.4Bits(typ)610MHz；

SNR 51dB(typ)；

SFDR 63dBc(typ)

the internal structure of EV10AQ190 is shown in fig. 2. Wherein, the signal definition of EV10AQ190 is shown in Table 1:

TABLE 1

In an alternative, the analog signal input terminal of the ADC converter 11 is connected to an SMA (SubMiniature version a) interface of the front panel, the analog signal input terminal of the ADC converter 11 is ac-coupled, and RF transfer mor is used to perform single-ended-differential conversion, and the common-mode voltage is generated in the chip. And a pi-type attenuator is arranged between the analog signal input end and the SMA interface, and a balancer Balun is arranged between the pi-type attenuator and the SMA interface and is used for converting an input signal from the SMA interface into a differential signal so as to realize impedance matching. The Balun can be ADTL2-18 from mini company, which can work at-55 to 100 ℃ and the application circuit is shown in figure 3. ADTL2-18 may, among other things, convert an input analog signal to a differential signal.

Alternatively, the sampling clock input may be an ac-coupled differential input, its internal self-bias generates common mode, the dc blocking capacitor is 10nF ceramic capacitor, and the connection circuit may be as shown in fig. 4.

In an optional scheme, because the ADC converter may adopt a high-speed ADC converter, a low-jitter clock source may be used to prevent reduction of the SNR of the output signal to noise ratio of the ADC converter, and because the board card needs to drive one ADC and one FPGA in synchronization with an external sampling clock, and needs to provide a VCO locally to meet the self-test requirement, the AD9516-0 may be selected as the clock BUFFER. The working characteristics of the AD9516-0 comprise: the highest working frequency reaches 2.6GHz, 6 LVPECL outputs, 4 LVDS outputs, 225fs jitter and 3.3V power supply.

Optionally, the external sampling clock is an SMA single-ended AC-coupled input, which can be self-biased by the AD9516-0, and the input clock 150mVpp 2Vpp, and the single-ended access circuit is shown in FIG. 5.

In an alternative arrangement, DAC converter 12 may be implemented using model AD9739BBCZ available from Analog corporation. The main properties of AD9739BBCZ include: 14bit quantization precision; the output current range is 8.66mA-31.66 mA; single-channel analog output; a maximum 2.5G reference clock input; double-path DDR LVDS input, wherein the highest clock rate of each path is 625 MHz; a serial SPI interface; 3.3V and 1.8V working power supplies, 1.1W power consumption; working temperature: TA is more than or equal to minus 40 ℃ and less than or equal to plus 85 ℃.

The internal structural diagram of the AD9739BBCZ is shown in FIG. 6. The AD9739BBCZ is a high-performance 14-bit dac with a maximum conversion rate of 2500MSPS, and the signal definition of the AD9739BBCZ is shown in table 2.

Name of signal	Function(s)
		DB1[13:0]+/-DB0[13:0]+/-	DAC data
DCI+/-	CLK IN
		DCO+/-	CLK OUT
CS	SPI
		SCLK	SPI
SDO	SPI
		SDI	SPI
RESET	RESET
		SYNC_OUT	Synchronous signal output
SYNC_IN	Synchronous signal input
		IOUTP/N	DAC analog output
I120	10K ohm resistance to ground, generating 120uA current
		VREF	1nf capacitance to ground
DACLK_N/P	Sampling clock input
		IRQ	Terminal output, open drain, pull-up 10K ohm resistor

TABLE 2

Optionally, the AD9739BBCZ adopts a current output mode, the full-scale output current of the AD9739BBCZ is adjustable from 8mA to 30mA, the output impedance is 70 ohms, and the relationship between the output spurious-free dynamic range SFDR and the sampling rate is shown in fig. 7. The IOUTP provides full-scale output, the IOUTN provides output direct current bias, the output can be converted into single-ended output by using a transfermor, resistance between the IOUTP and the IOUTN can be taken into consideration when output voltage and output impedance are designed, and internal resistance is 70 ohms.

A block diagram of the AD9739BBCZ front-end analog circuit design can be seen in fig. 8. According to the circuit in fig. 8, the following features can be obtained:

Rout＝(90+90)||70:1:1＝50.4；

vout is Ioutfs Rout (Ioutfs is adjustable between 8mA and 30 mA);

the type of the transformer is as follows: MABACT0039 (or ETC1-1-13) and ADTL1-12 may be selected;

frequency range: 20-1200 MHz;

insertion loss: 2dB, frequency 1.2 GHz;

primary-secondary coil ratio: 1: 1;

input power: 1W;

working temperature: -20 to +85 ℃.

In an alternative scheme, the AD9739BBCZ has a high requirement on the input clock swing, so that the clock driving BUFFER of the ADC converter 11 cannot be used, and the embodiment may select the clock BUFFER ADCLK914 recommended by the AD9739 BBCZ. The circuit connection of ADCLK914 is shown in FIG. 9, where the clock input is 0.2-2.8V, about-13.5-9 dB.

In an alternative, the FPGA13 is provided in the form of a Kirtex 7 series XC7K 325T. The resource information of XC7K325T is shown in FIG. 10.

In an alternative scheme, the sampled data transmission between the FPGA13 and the ADC converter 11 is performed in a source synchronous receiving manner, the operation mode of the ADC converter 11 is a DES mode, and the output timing is as shown in fig. 11.

In an alternative arrangement, the internal interface logic structure of the FPGA13 is shown in FIG. 12. The digital input interface of the AD9739BBCZ is shown in FIG. 13. The AD9739BBCZ is input to the high-speed DAC converter 12 in the same manner as the high-speed ADC converter 11, and may be a cross data input method. Therefore, the output interface of the FPGA13 needs to consider the source synchronous relationship of data and the clock 15, and the output timing thereof is as shown in fig. 14.

Alternatively, the interface implementation of the FPGA13 may refer to the design shown in FIG. 15.

In an alternative, the FPGA13 may be connected to two independent SRAMs 14, where SRAM14 is embodied as a quad data rate QDRII SRAM.

Standard synchronous SRAM is an ideal choice for cache storage and data computing applications. Cache chips that can be used are ZBT SRAM, DDRII SRAM, QDRII SRAM, RLDRAM, and the like. Wherein: ZBT SRAMs, i.e., "zero bus turnaround" type SRAMs, contain data registers in peripheral circuits for pipelined read and write operations, thereby eliminating latency cycles and achieving peak bus utilization. However, data reading and writing of the ZBT SRAM are all single clock edge, and the clock frequency is not high, and is usually within 200 MHz.

DDRII SRAM have high interface read/write speed but cannot perform simultaneous read/write operations on the memory chip. QDRII SRAM have certain similarities with RLDRAM, such as independent data read/write ports, double data interfaces, echo clocks, programmable impedances, etc. An RLDRAM memory array is also a dynamic memory cell, which is an improved DRAM that can use a circular addressing scheme and a specific access sequence to achieve 100% bandwidth utilization, but is less efficient when performing random data access. Furthermore, the initial delay time of the RLDRAM is long when short data access operations occur in succession.

QDRII SRAM because of the static RAM, the read operation of the data is delayed by only 1 or 1.5 clock cycles. In contrast to RLDRAM, QDRII SRAM does not require any wait between access operations and therefore is not affected by application randomness.

Therefore, in this embodiment, QDRII SRAM may be used to implement storage. Alternatively, as shown in fig. 18, two independent QDRII SRAM controllers may be connected to the FPGA in this embodiment. The data bit width of each QDRII SRAM controller is 36bits, each controller has two 18-bit controllers, and a single board has eight QDRII SRAM chips, and the capacity of each chip is 72 Mbit.

In an alternative scheme, QDRII SRAM selects CY7C15632KV18 of CYPRESS company as a model supported by the FPGA development tool ISE12.2 MIG 3.5, and of course, the model of the chip may be replaced according to the procurement condition, and then the parameters stored in the MIG tool are modified according to the replaced model.

The main characteristics of CY7C15632KV18 are as follows:

2.5 clock read delays;

a Double Data Rate (DDR) interface can achieve a 1100MHz data transmission rate at a 550MHz frequency, and currently, a single port can achieve 300MHz DDR 36 bits-2.4 GB/s;

4-word Burst (Burst), which can reduce the address bus frequency;

two input clocks (K and K #), which can realize precise DDR time sequence;

the associated clock (CQ and CQ #) can simplify the data capture in a high-speed system;

the core voltage VDD is 1.8V, the I/O interface voltage VDDQ is 1.4V at the minimum, and the maximum is the core voltage VDD;

an HSTL input buffer and an HSTL output buffer with adjustable driving capability;

when the single chip works at the frequency of 550MHz, the maximum working current is 920mA, and when the single chip works at the frequency of 400MHz, the maximum working current is 710 mA.

The main pin description of CY7C15632KV18 is shown in table 3.

TABLE 3

Alternatively, the pin connections of QDRI I SRAM and FPGA13 are as shown in FIG. 16. The core structure generated by MIG is shown in FIG. 17.

In an alternative scheme, an interface between the FPGA and the ADC converter, an interface between the FPGA and the DAC converter, and an interface between the FPGA and the SRAM all use a local clock network. As shown in fig. 18, the ADC converter and the DAC converter are respectively connected to different clock chips, wherein the clock chip connected to the ADC converter may be AD9516, and the clock chip connected to the DAC converter may be ADCLX 9514.

In an alternative scheme, the power supply adopts an EMI filter for dividing the linear power supply output by the power supply to supply power for each ADC converter and DAC converter separately. This suppresses interference between the two analog circuits (mainly from the power supply). Alternatively, in order to prevent the power supply rejection ratio PSRR of the linear power supply from being insufficient, ripple rejection may be increased using NFM18PS105R0J3, the characteristic curve of which is shown in fig. 19.

In an alternative, as shown in fig. 20, the panel size of the digital rf memory 10 may be 100mm by 20 mm.

Based on above-mentioned embodiment, the digital radio frequency memory of this application can realize miniaturized DRFM design scheme through adopting above-mentioned framework, when compatible with the performance index of traditional DRFM product, the module size that significantly reduces can adapt to more miniaturized electronic equipment fields, for example unmanned aerial vehicle mini jammer, miniaturized simulation radiation source etc.. And the power consumption of the module can be controlled within 8W, so that the possibility of adapting the DRFM to the application fields with limited power is provided, meanwhile, the cost of the original DRFM product can be reduced by nearly 50%, and the profit of the whole system is indirectly improved.

In addition, the digital radio frequency memory can adopt indexes of industrial standard devices (-40-85 ℃), and wide-temperature environment adaptability of-50-85 ℃ is achieved.

The above-mentioned serial numbers of the embodiments of the present application are merely for description, and do not represent the advantages and disadvantages of the embodiments.

In the above embodiments of the present application, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit is merely a division of a logic function, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The foregoing is only a preferred embodiment of the present application and it should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.

Claims (9)

1. A digital radio frequency memory, comprising: the device comprises an ADC (analog-to-digital converter), a DAC (digital-to-analog converter), an FPGA (field programmable gate array), a static random access memory SRAM (static random access memory), a clock and a power supply;

the clock is connected with the ADC converter and the DAC converter and used for providing a working clock signal;

the interface between the FPGA and the ADC converter, the interface between the FPGA and the DAC converter and the interface between the FPGA and the SRAM adopt local clock networks.

2. The digital radio frequency memory of claim 1,

the ADC converter is of the type EV10AQ 190.

3. The digital radio frequency memory of claim 2,

the analog signal input end of the ADC is connected with the subminiature version SMA interface, a pi-type attenuator is arranged between the analog signal input end and the SMA interface, and a balancer Balun is arranged between the pi-type attenuator and the SMA interface and used for converting input signals from the SMA interface into differential signals so as to realize impedance matching.

4. The digital radio frequency memory of claim 1,

the DAC converter is of the type AD9739 BBCZ.

5. The digital radio frequency memory of claim 1,

the FPGA adopts a model number of Kirtex 7 series XC7K 325T.

6. The digital radio frequency memory of claim 1,

the sampled data transmission between the FPGA and the ADC adopts a source synchronous receiving mode, and the working mode of the ADC is a DES mode.

7. The digital radio frequency memory of claim 1,

the FPGA is connected to two independent SRAMs, specifically quad data rate QDRII SRAM.

8. The digital radio frequency memory of claim 7,

QDRII SRAM adopts model CY7C15632KV 18.

9. The digital radio frequency memory according to any of claims 1 to 8,

the power supply adopts an EMI filter for dividing the linear power output by the power supply and respectively supplies power for each path of ADC converter and DAC converter.

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