CN216901263U - Array substrate, display panel and display device - Google Patents

Abstract

The application discloses an array substrate, a display panel and a display device, wherein the array substrate comprises a substrate base plate, a first conducting layer, a second conducting layer and an intermediate layer, the second conducting layer, the intermediate layer and the first conducting layer are sequentially arranged on the substrate base plate, the first conducting layer is arranged above the second conducting layer, the intermediate layer is arranged between the first conducting layer and the second conducting layer, the intermediate layer is provided with a through hole, and the first conducting layer is communicated with the second conducting layer through the through hole; the through holes at least comprise a first through hole and a second through hole, the first through hole is positioned above the second through hole, the first through hole and the second through hole are coaxially arranged, the side wall of the first through hole is directly connected with the side wall of the second through hole to form the through hole, and the included angle between the side wall of the first through hole and the substrate base plate is smaller than or equal to the included angle between the side wall of the second through hole and the substrate base plate. This application effectively improves the problem that bad contact appears between first conducting layer and the second conducting layer and even breaks through above mode.

Description

Array substrate, display panel and display device

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a display panel and a display device.

Background

With the continuous development of science and technology, the living standard of people is continuously improved, the demand of people on display equipment is higher and higher, and the quality of a display panel which is taken as a core component in the display equipment directly influences the quality of the display equipment. The display panel is generally composed of a color filter substrate, an array substrate and a liquid crystal layer disposed between the two substrates. Generally, the array substrate and the color filter substrate are respectively provided with a pixel electrode and a common electrode. When voltages are applied to the pixel electrodes and the common electrode, an electric field is generated in the liquid crystal layer, which determines the orientation of liquid crystal molecules, thereby adjusting the polarization of light incident to the liquid crystal layer, and displaying images on the liquid crystal panel.

The pixel electrode and the common electrode are usually connected through a via hole on the array substrate and a conductive layer to form an electric field after being electrified, but the opening angle of the via hole is small, so that the side wall of the via hole is too steep, and the pixel electrode and the common electrode are easy to be in poor contact or even broken when passing through the via hole, so that liquid crystal cannot deflect normally, and the display effect of the display panel is influenced.

SUMMERY OF THE UTILITY MODEL

The application aims to provide an array substrate, a display panel and a display device, which can effectively solve the problem that poor contact and even disconnection occur between a first conducting layer and a second conducting layer.

The application discloses an array substrate, which comprises a substrate base plate, a first conducting layer, a second conducting layer and an intermediate layer, wherein the second conducting layer, the intermediate layer and the first conducting layer are sequentially arranged on the substrate base plate; the through-hole includes first through-hole and second through-hole at least, first through-hole is located second through-hole top, first through-hole with the coaxial setting of second through-hole, just the lateral wall of first through-hole with the lateral wall lug connection of second through-hole forms the through-hole, the lateral wall of first through-hole with contained angle between the substrate base plate is less than or equal to the lateral wall of second through-hole with contained angle between the substrate base plate.

Optionally, an included angle between the sidewall of the first through hole and the substrate base plate ranges from 30 ° to 40 °; the included angle between the side wall of the second through hole and the substrate base plate ranges from 40 degrees to 50 degrees.

Optionally, a difference between the opening width of the first through hole and the opening width of the second through hole ranges from 0.4 micrometers to 0.6 micrometers.

Optionally, at least one first through groove is formed in a side wall of the first through hole, and the first through groove is formed along an extending direction of the side wall of the first through hole; at least one second through groove is formed in the side wall of the second through hole, and the second through groove is formed in the extending direction of the side wall of the second through hole; at least one first through groove is communicated with at least one second through groove, and the orthographic projection of the first through groove on the substrate base plate and the orthographic projection of the second through groove on the substrate base plate are on the same straight line.

Optionally, a stepped portion is disposed at a groove bottom of the second through groove, and the stepped portion does not protrude from a plane where openings of the first through groove and the second through groove are located.

Optionally, at least one first protruding strip is arranged on a side wall of the first through hole, and the first protruding strip is arranged along an extending direction of the side wall of the first through hole; at least one second raised line is arranged on the side wall of the second through hole and arranged along the extending direction of the side wall of the second through hole; one end of the first raised line is connected with one end of the second raised line, and the orthographic projection of the first raised line on the substrate base plate and the orthographic projection of the second raised line on the substrate base plate are on the same straight line.

Optionally, the array substrate includes a thin film transistor, the thin film transistor includes a drain, the second conductive layer is the drain, the first conductive layer includes a pixel electrode, and the pixel electrode is connected to the drain through the through hole.

Optionally, the first conductive layer further includes a common electrode, the array substrate further includes a common electrode line, the common electrode line is disposed on the substrate, the second conductive layer is the common electrode line, and the common electrode is connected to the common electrode line through the through hole.

The application also discloses a display panel, including the opposition base plate, display panel still includes foretell array substrate, the opposition base plate with array substrate sets up to the box.

The application also discloses a display device, including backlight unit, display device still includes foretell display panel, backlight unit sets up one side of display panel's income plain noodles.

The through holes of the middle layer are arranged into at least two sections, namely at least a first through hole and a second through hole are arranged, the included angle between the side wall of the first through hole and the substrate base plate is smaller than or equal to the included angle between the side wall of the second through hole and the substrate base plate, the first through hole and the second through hole with different side wall inclination angles are combined, the opening width of the through holes is increased, the inclination of the side wall of the through hole is effectively reduced, and the side wall of the through hole becomes gentler and less steep; when the first conducting layer is connected with the second conducting layer through the through hole, the first conducting layer can better cover the side wall of the through hole, and the problem that poor contact and even disconnection occur between the first conducting layer and the second conducting layer is effectively solved. And the side wall of the first through hole is directly connected with the side wall of the second through hole to form the through hole, so that the through hole can be manufactured in the middle layer only through one process, the working procedures are saved, and the cost is saved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

fig. 1 is a partial schematic view of a first embodiment of an array substrate according to the present application;

FIG. 2 is a partial schematic view of a second embodiment of an array substrate according to the present application;

FIG. 3 is a partial schematic view of a third embodiment of an array substrate according to the present application;

FIG. 4 is a partial schematic view of a fourth embodiment of an array substrate according to the present application;

FIG. 5 is a schematic diagram of an embodiment of a display panel according to the present application;

FIG. 6 is a schematic diagram of an embodiment of a display device according to the present application.

10, a display device; 100. a display panel; 200. a backlight module; 110. an opposing substrate; 111. a glass substrate; 120. an array substrate; 121. a first conductive layer; 122. a second conductive layer; 123. an intermediate layer; 124. a through hole; 125. a first through hole; 126. a first through groove; 127. a first rib; 128. a second through hole; 129. a second through groove; 130. a second convex strip; 131. a step portion; 132. a planarization layer; 133. a gate insulating layer; 134. a passivation layer; 135. a base substrate; 136. a pixel electrode; 137. a common electrode; 138. a drain electrode; 139. a common electrode line.

Detailed Description

It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.

Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.

Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

The present application is described in detail below with reference to the figures and alternative embodiments.

Fig. 1 is a partial schematic view of a first embodiment of an array substrate, as shown in fig. 1, the present application discloses an array substrate 120, which includes a substrate 135, a first conductive layer 121, a second conductive layer 122 and an intermediate layer 123, wherein the second conductive layer 122, the intermediate layer 123 and the first conductive layer 121 are sequentially disposed on the substrate 135, the first conductive layer 121 is disposed above the second conductive layer 122, the intermediate layer 123 is disposed between the first conductive layer 121 and the second conductive layer 122, the intermediate layer 123 is provided with a through hole 124, and the first conductive layer 121 is communicated with the second conductive layer 122 through the through hole 124; the through holes 124 at least include a first through hole 125 and a second through hole 128, the first through hole 125 is located above the second through hole 128, the first through hole 125 and the second through hole 128 are coaxially arranged, a side wall of the first through hole 125 is directly connected with a side wall of the second through hole 128 to form the through hole 124, and an included angle between the side wall of the first through hole 125 and the substrate base plate 135 is smaller than or equal to an included angle between the side wall of the second through hole 128 and the substrate base plate 135.

The through hole 124 of the intermediate layer 123 is arranged into at least two sections, namely at least a first through hole 125 and a second through hole 128 are provided, the included angle between the side wall of the first through hole 125 and the substrate base plate 135 is smaller than or equal to the included angle between the side wall of the second through hole 128 and the substrate base plate 135, the opening width of the through hole 124 is increased by combining the first through hole 125 and the second through hole 128, the inclination angles of the side walls of the through hole 124 are effectively reduced, and the side wall of the through hole 124 becomes gentler and less steep; when the first conductive layer 121 is connected to the second conductive layer 122 through the through hole 124, the first conductive layer 121 can better cover the sidewall of the through hole 124, thereby effectively improving the problem of poor contact or even disconnection between the first conductive layer 121 and the second conductive layer 122. And the side wall of the first through hole 125 is directly connected with the side wall of the second through hole 128 to form the through hole 124, so that the through hole 124 can be manufactured on the middle layer 123 only through one process, the process is saved, and the cost is saved.

It should be noted that the array substrate 120 of the present application may be applied to a common liquid crystal display panel, and may also be applied to a COA display panel, where the application only uses the display panel 100 as the COA display panel, and the array substrate 120 in the COA display panel is exemplified; in addition, the through hole 124 in the present application may be a through hole 124 in the array substrate 120, in which the pixel electrode 136 is connected to the drain electrode 138, or a through hole 124 in which the common electrode 137 is connected to the common electrode line 139, and the two structures are the same and are only applied to different positions of the array substrate 120, specifically as follows:

as shown in fig. 1, the array substrate 120 includes a thin film transistor including a drain electrode 138, the second conductive layer 122 is the drain electrode 138, the first conductive layer 121 includes a pixel electrode 136, and the pixel electrode 136 is connected to the drain electrode 138 through the via 124.

When the via 124 is disposed between the pixel electrode 136 and the drain electrode 138 of the thin film transistor, the first conductive layer 121 is the pixel electrode 136, the second conductive layer 122 is the drain electrode 138, the intermediate layer 123 may be the passivation layer 134, the planarization layer 132, and the like, the first via 125 of the via 124 may be disposed on the planarization layer 132, and the second via 128 may be disposed on the passivation layer 134, or the first via 125 may simultaneously pass through the planarization layer 132 and the passivation layer 134, and the positions of the passivation layer 134 and the planarization layer 132 corresponding to the first via 125 and the second via 128 are only required to be adapted to the structure of the via 124 in the present application, and are not particularly limited herein.

The pixel electrode 136 can better cover the through hole 124, thereby avoiding the problem of poor contact or disconnection between the pixel electrode 136 and the drain 138 of the thin film transistor, and further ensuring the display quality of the display panel 100.

When the through hole 124 is disposed between the common electrode 137 and the common electrode line 139, the first conductive layer 121 further includes the common electrode 137, the array substrate 120 further includes the common electrode line 139, the common electrode line 139 is disposed on the substrate 135, the second conductive layer 122 is the common electrode line 139, and the common electrode 137 is connected to the common electrode line 139 through the through hole 124. The intermediate layer 123 may be a passivation layer 134, a planarization layer 132, a gate insulating layer 133, etc., and the first via 125 of the vias 124 may be disposed on the planarization layer 132 and the second via 128 may pass through both the passivation layer 134 and the gate insulating layer 133, or the first via 125 may pass through both the planarization layer 132 and the passivation layer 134 and the second via 128 is disposed on the gate insulating layer 133.

The common electrode 137 can better cover the through hole 124, so that the problem of poor contact or disconnection between the common electrode 137 and the common electrode line 139 is avoided, and the display quality of the display panel 100 is further ensured.

Of course, the through hole 124 of the present application may be disposed only between the common electrode 137 and the common electrode line 139, or only between the pixel electrode 136 and the drain electrode 138, for improving the problem of poor contact or short line; through holes 124 can be arranged between the common electrode 137 and the common electrode line 139 and between the pixel electrode 136 and the drain electrode 138, so that the problems of poor contact or disconnection can be further prevented.

This application makes through-hole 124 become more gentle in order to further improve the slope of through-hole 124 lateral wall, improves through-hole 124, specifically as follows:

the angle α between the sidewall of the first through hole 125 and the substrate base plate 135 ranges from 30 ° to 40 °; the angle β between the sidewall of the second via 128 and the substrate base 135 is in the range of 40 ° to 50 °. Since the smaller the angle between the side walls of the first through hole 125 and the second through hole 128 and the substrate base plate 135 is, the more gradual the slope of the side walls of the first through hole 125 and the second through hole 128 is, but in actual process manufacturing, the angle α between the side wall of the first through hole 125 and the substrate base plate 135 is set to be between 30 ° and 40 °, specifically, 35 °; setting an included angle β between the sidewall of the second through hole 128 and the substrate base plate 135 to be 40 ° to 50 °, specifically 45 °; the slope formed by the side walls of the first through hole 125 and the second through hole 128 is limited by limiting the included angle between the first through hole 125 and the second through hole 128 and the substrate base plate 135, so that the first through hole 125 and the second through hole 128 can be formed more easily through process manufacturing, and meanwhile, the slope is relatively gentle, and the problem of poor contact or disconnection when the first conductive layer 121 and the second conductive layer 122 are connected through the through hole 124 is avoided.

Further, the difference between the opening width of the first via 125 and the opening width of the second via 128 ranges from 0.4 micrometers to 0.6 micrometers. On the premise that the aperture ratio of the display panel 100 is not affected, the slope of the first through hole 125 is further reduced, the problem of poor contact or disconnection when the first conductive layer 121 and the second conductive layer 122 are connected through the through hole 124 is effectively solved, and the display quality of the display panel 100 is further improved.

Fig. 2 is a partial schematic view of a second embodiment of the array substrate of the present application, as shown in fig. 2, the embodiment shown in fig. 2 is based on the improvement of fig. 1; at least one first through groove 126 is formed in the side wall of the first through hole 125, and the first through groove 126 is formed along the extending direction of the side wall of the first through hole 125; at least one second through groove 129 is formed in the side wall of the second through hole 128, and the second through groove 129 is formed along the extending direction of the side wall of the second through hole 128; the at least one first through slot 126 is communicated with the at least one second through slot 129, and an orthographic projection of the first through slot 126 on the substrate base plate 135 is on the same straight line with an orthographic projection of the second through slot 129 on the substrate base plate 135.

In this embodiment, the first through groove 126 and the second through groove 129 are formed by recessing the side wall of the first through hole 125 and the side wall of the second through hole 128, respectively, and the first through groove 126 and the second through groove 129 are communicated, when the pixel electrode 136 or the common electrode 137 is deposited on the through hole 124, the first through groove 126 and the second through groove 129 increase the contact area between the pixel electrode 136 and the common electrode 137 and the side wall of the through hole 124, and the pixel electrode 136 or the common electrode 137 may form a filling in the first through groove 126 and the second through groove 129, so that the pixel electrode 136 or the common electrode 137 deposited in the first through groove 126 and the second through groove 129 can have a better "adhesion" property in the first through groove 126 and the second through groove 129; meanwhile, after the pixel electrode 136 or the common electrode 137 completely fills the first through groove 126 and the second through groove 129, the thickness of the pixel electrode 136 or the common electrode 137 at the positions of the first through groove 126 and the second through groove 129 is increased, the problem of poor contact or disconnection caused by connection with the drain electrode 138 or the common electrode line 139 of the array substrate 120 when the pixel electrode 136 or the common electrode 137 is deposited on the through hole 124 is effectively solved, and the display quality of the display panel 100 is improved.

Fig. 3 is a partial schematic view of a third embodiment of the array substrate of the present application, as shown in fig. 3, the embodiment shown in fig. 3 is based on the improvement of fig. 2, a step 131 is provided at the bottom of the second through groove 129, and the step 131 does not protrude from the plane where the openings of the first through groove 126 and the second through groove 129 are located.

The difference between the present embodiment and the previous embodiment is that the stepped portion 131 is disposed at the bottom of the second through groove 129, the contact area between the pixel electrode 136 or the common electrode 137 and the second through hole 128 is further increased by the stepped portion 131, and meanwhile, after the first through groove 126 and the second through groove 129 are completely filled with the pixel electrode 136 or the common electrode 137, the stepped portion can further increase the thickness of the pixel electrode 136 or the common electrode 137 at the position of the second through groove 129, thereby effectively improving the problem of poor contact or disconnection caused by connection with the drain electrode 138 or the common electrode line 139 of the array substrate 120 when the pixel electrode 136 or the common electrode 137 is deposited on the through hole 124, and improving the display quality of the display panel 100.

Fig. 4 is a partial schematic view of a fourth embodiment of the array substrate of the present application, as shown in fig. 4, the embodiment shown in fig. 4 is based on the improvement of fig. 2, at least one first protruding strip 127 is disposed on a sidewall of the first through hole 125, and the first protruding strip 127 is disposed along an extending direction of the sidewall of the first through hole 125; at least one second protruding strip 130 is arranged on the side wall of the second through hole 128, and the second protruding strip 130 is arranged along the extending direction of the side wall of the second through hole 128; one end of the first protrusion 127 is connected to one end of the second protrusion 130, and an orthogonal projection of the first protrusion 127 on the substrate base 135 and an orthogonal projection of the second protrusion 130 on the substrate base 135 are on the same straight line.

In the present embodiment, the protruding strips, that is, the first protruding strip 127 and the second protruding strip 130, are disposed on the sidewalls of the first through hole 125 and the second through hole 128, and the first protruding strip 127 and the second protruding strip 130 increase the contact area of the first conductive layer 121 passing through the first through hole 125 and the second through hole 128, for example, when the first conductive layer 121 is the pixel electrode 136 and the second conductive layer 122 is the drain electrode 138 on the array substrate 120, because the first protruding strip 127 and the second protruding strip 130 increase the surface area of the sidewall of the through hole 124, when the pixel electrode 136 covers the sidewall of the through hole 124, the contact area with the sidewall of the through hole 124 is increased, so as to form a better "adhesion", and the pixel electrode 136 is not prone to have a poor contact or disconnection between the position of the through hole 124 and the drain electrode 138. The display quality of the display panel 100 is further ensured.

For the sake of space limitation, the embodiment is only illustrated by the arrangement that the two ends of the first protruding strip 127 and the second protruding strip 130 are connected and projected on the same straight line, but the arrangement of the first protruding strip 127 and the second protruding strip 130 is not limited thereto, and other arrangements are also possible; for example, both ends of the first protruding strip 127 and the second protruding strip 130 may not be connected, the first protruding strip 127 and the second protruding strip 130 may be arranged in a staggered manner, and the contact area between the first through hole 125 and the pixel electrode 136 or the common electrode 137 and the contact area between the second through hole 128 and the pixel electrode 136 may be increased; in addition, the number of the first protruding strip 127 and the second protruding strip 130 may be one each, or may be multiple each, and when the first protruding strip 127 and the second protruding strip 130 are multiple, they may be arranged along a circumference of the sidewall of the first through hole 125 and the sidewall of the second through hole 128.

Fig. 5 is a schematic diagram of an embodiment of a display panel of the present application, and as shown in fig. 5, the present application further discloses a display panel 100, which includes an opposite substrate 110, the display panel 100 further includes the array substrate 120, and the opposite substrate 110 and the array substrate 120 are disposed in a box-to-box manner.

The display panel 100 of the present application may be a liquid crystal display panel 100, a COA display panel 100, or the like, and is not particularly limited herein. In the COA display panel 100, the counter substrate 110 is a glass substrate 111, a liquid crystal layer is disposed between the array substrate 120 and the glass substrate 111, and the pixel electrode 136 and the common electrode 137 are provided on the array substrate 120. (the pixel electrode 136 and the common electrode 137 in this application may be in the same layer or different layers, and are not limited thereto.)

When voltages are applied to the pixel electrode 136 and the common electrode 137, an electric field is generated in the liquid crystal layer, which determines the orientation of liquid crystal molecules, thereby adjusting the polarization of light incident to the liquid crystal layer, and displaying images on the liquid crystal panel. The display panel 100 of the present application can enable the pixel electrode 136 or the common electrode 137 to more easily cover the through hole 124 of the middle layer 123 of the array substrate 120, effectively improve the problem that poor contact or even disconnection occurs between the pixel electrode 136 and the drain electrode 138 of the array substrate 120 or between the common electrode 137 and the common electrode line 139, and further ensure the product quality of the display panel 100. And the through hole 124 on the array substrate 120 can be manufactured on the middle layer 123 only by one process, so that the working procedure is saved, and the cost is saved.

Fig. 6 is a schematic view of an embodiment of a display device according to the present application, and as shown in fig. 6, the present application discloses a display device 10 including a backlight module 200, the display device 10 further includes the display panel 100, and the backlight module 200 is disposed on one side of the light incident surface of the display panel 100. The display panel 100 does not emit light, and the light source provided by the backlight module 200 irradiates the display panel 100 to ensure the normal display of the display panel 100. After the display device 10 of the present application uses the display panel 100, the problem that the display panel 100 is abnormal or cannot display due to poor contact or short lines between the pixel electrode 136 and the drain electrode 138 inside the display panel 100 or between the common electrode 137 and the common electrode line 139 can be effectively improved, and the product quality of the display device 10 is improved.

It should be noted that the inventive concept of the present application can form many embodiments, but the present application has a limited space and cannot be listed one by one, so that, on the premise of no conflict, any combination between the above-described embodiments or technical features can form a new embodiment, and after the embodiments or technical features are combined, the original technical effect will be enhanced.

The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be considered as belonging to the protection scope of the present application.

Claims (10)

1. An array substrate comprises a substrate base plate, a first conducting layer, a second conducting layer and an intermediate layer, wherein the second conducting layer, the intermediate layer and the first conducting layer are sequentially arranged on the substrate base plate;

the through hole is characterized by at least comprising a first through hole and a second through hole, wherein the first through hole is positioned above the second through hole, the first through hole is coaxially arranged with the second through hole, the side wall of the first through hole is directly connected with the side wall of the second through hole to form the through hole, and the angle between the side wall of the first through hole and the substrate is less than or equal to that between the side wall of the second through hole and the substrate.

2. The array substrate of claim 1, wherein an angle between the sidewall of the first via and the substrate base is in a range of 30 ° to 40 °; the included angle between the side wall of the second through hole and the substrate base plate ranges from 40 degrees to 50 degrees.

3. The array substrate of claim 2, wherein the difference between the opening width of the first via and the opening width of the second via is in a range of 0.4 microns to 0.6 microns.

4. The array substrate according to claim 2, wherein at least one first through groove is disposed on a side wall of the first through hole, and the first through groove is disposed along an extending direction of the side wall of the first through hole;

at least one second through groove is formed in the side wall of the second through hole, and the second through groove is formed in the extending direction of the side wall of the second through hole;

at least one first through groove is communicated with at least one second through groove, and the orthographic projection of the first through groove on the substrate base plate and the orthographic projection of the second through groove on the substrate base plate are on the same straight line.

5. The array substrate of claim 4, wherein the bottom of the second through groove is provided with a step portion, and the step portion does not protrude from a plane where the openings of the first through groove and the second through groove are located.

6. The array substrate of claim 2, wherein at least one first rib is disposed on a sidewall of the first through hole, and the first rib is disposed along an extending direction of the sidewall of the first through hole;

at least one second raised line is arranged on the side wall of the second through hole, and the second raised line is arranged along the extending direction of the side wall of the second through hole;

one end of the first raised line is connected with one end of the second raised line, and the orthographic projection of the first raised line on the substrate base plate is on the same straight line with the orthographic projection of the second raised line on the substrate base plate.

7. The array substrate of any one of claims 1 to 6, wherein the array substrate comprises a thin film transistor, the thin film transistor comprises a drain electrode, the second conductive layer is the drain electrode, the first conductive layer comprises a pixel electrode, and the pixel electrode is connected with the drain electrode through the through hole.

8. The array substrate of any one of claims 1 to 6, wherein the first conductive layer further comprises a common electrode, the array substrate further comprises a common electrode line, the common electrode line is disposed on the substrate, the second conductive layer is the common electrode line, and the common electrode is connected to the common electrode line through the through hole.

9. A display panel comprising a counter substrate, wherein the display panel further comprises an array substrate according to any one of claims 1 to 8, and the counter substrate is provided in a pair with the array substrate.

10. A display device comprising a backlight module, wherein the display device further comprises the display panel according to any one of claims 1 to 9, and the backlight module is disposed on one side of the light incident surface of the display panel.

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