CN216873077U - Voltage dynamic adjustment circuit for power output and intelligent power supply thereof - Google Patents
Voltage dynamic adjustment circuit for power output and intelligent power supply thereof Download PDFInfo
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- CN216873077U CN216873077U CN202123223588.1U CN202123223588U CN216873077U CN 216873077 U CN216873077 U CN 216873077U CN 202123223588 U CN202123223588 U CN 202123223588U CN 216873077 U CN216873077 U CN 216873077U
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Abstract
The utility model discloses a voltage dynamic adjusting circuit for power output and an intelligent power supply thereof, wherein the voltage dynamic adjusting circuit comprises an input power supply, a power supply chip, a first resistor and a second resistor, the power supply chip is used for adjusting the voltage output by the input power supply to a load, the power supply chip comprises a reference power supply, an error amplifier and an MOS (metal oxide semiconductor) tube, the output end of the error amplifier is connected to the grid electrode of the MOS tube, one end of the reference power supply is grounded, the other end of the reference power supply is connected to the positive input end of the error amplifier, the drain electrode of the MOS tube is connected to the input power supply, and the source electrode of the MOS tube is used for being connected to the load; the first resistor and the second resistor are connected in series to form a first branch circuit, one end of the first branch circuit is connected to the source electrode of the MOS tube, the other end of the first branch circuit is grounded, and the connection point of the first resistor and the second resistor is connected to the negative input end of the error amplifier. The voltage dynamic adjusting circuit and the intelligent power supply thereof provided by the utility model replace a chip special for a communication interface by using simple circuit elements, thereby greatly reducing the cost.
Description
Technical Field
The utility model relates to the technical field of voltage regulation output, in particular to a dynamic voltage regulation circuit for power supply output and an intelligent power supply thereof.
Background
In the existing practical application, when the output voltage needs to be adjusted in real time, a special IC with a communication interface is often used, the controller communicates with the IC to adjust the output voltage of the power supply IC, the power supply is fed back to the interior of the IC, and different output voltage gears are selected through software configuration, so that different voltages are generated, and the purpose of real-time dynamic adjustment is achieved. However, such a power IC is expensive, needs to communicate with the power IC, is easily interfered, and increases the difficulty of software design, and such a dedicated IC generally has a high cost and a complicated software design. In addition, many power supply feedback points of the conventional power supply IC can be arranged outside the IC, and the output voltage can be adjusted by adjusting an external feedback resistor, but the purpose of adjusting the output voltage in real time cannot be achieved by the scheme that the feedback resistor needs to be replaced manually. Therefore, it is necessary to provide a low-cost and low-development-difficulty dynamic output voltage adjustment scheme.
SUMMERY OF THE UTILITY MODEL
In order to solve the problems in the prior art, the utility model provides a voltage dynamic adjustment circuit for power supply output and an intelligent power supply thereof, wherein the technical scheme is as follows:
in one aspect, a dynamic voltage adjustment circuit for power output is provided, which includes an input power supply, a power supply chip, a first resistor R1 and a second resistor R2, where the power supply chip is configured to adjust a voltage output by the input power supply to a load, the power supply chip includes a reference power supply, an error amplifier U1 and a MOS transistor Q1, the error amplifier U1 is configured to adjust a linear state of operation of the MOS transistor Q1, an output end of the error amplifier U1 is connected to a gate of the MOS transistor Q1, one end of the reference power supply is grounded, the other end of the reference power supply is connected to a positive input end of the error amplifier U1, a drain of the MOS transistor Q1 is connected to the input power supply, and a source of the MOS transistor Q1 is configured to be connected to the load;
the first resistor R1 and the second resistor R2 are connected in series to form a first branch, one end of the first branch is connected to the source electrode of the MOS transistor Q1, the other end of the first branch is grounded, and the connection point of the first resistor R1 and the second resistor R2 is connected to the negative input end of the error amplifier U1.
Further, the voltage dynamic adjustment circuit further includes a third resistor R3 and a capacitor C1, the third resistor R3 and the capacitor C1 are connected in series to form a second branch, one end of the second branch is connected to the PWM interface of the load, the other end of the second branch is grounded, and a connection point of the third resistor R3 and the capacitor C1 is connected to a connection point of the first resistor R1 and the second resistor R2.
Furthermore, the voltage dynamic adjustment circuit further includes a fourth resistor R4, one end of the fourth resistor R4 is connected to a connection point of the third resistor R3 and the capacitor C1, and the other end of the fourth resistor R4 is connected to a connection point of the first resistor R1 and the second resistor R2.
Further, when the voltage of the positive input end of the error amplifier U1 is greater than that of the negative input end thereof, the power chip increases the output; when the voltage of the positive input end of the error amplifier U1 is smaller than that of the negative input end thereof, the power chip reduces the output.
Further, the resistance value of the fourth resistor R4 is greater than that of the third resistor R3.
Further, the voltage of the reference power supply is less than the voltage of the input power supply.
Further, the resistance value of the first resistor R1 is greater than that of the second resistor R2, and the second resistor R2 is grounded.
Further, the reference power supply, the error amplifier U1 and the MOS transistor Q1 are integrated, and the negative input end of the error amplifier U1 is used as a feedback access point of the power supply chip.
Further, the voltage output by the power supply chip is not greater than the voltage of the input power supply.
Further, the MOS transistor Q1 is an N-channel MOS transistor.
Further, the negative pole of the input power supply is grounded, and the positive pole of the input power supply is connected to the drain of the MOS transistor Q1.
In another aspect, an intelligent power supply is provided, which includes the voltage dynamic adjustment circuit.
The technical scheme provided by the utility model has the following beneficial effects:
a. a chip special for a communication interface is replaced by a simple circuit element, so that the cost is greatly reduced;
b. the adjusting speed is high, and the anti-interference capability is strong.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of a dynamic voltage adjustment circuit according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a dynamic voltage adjustment circuit according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the utility model described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or device that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or device.
In an embodiment of the present invention, a dynamic voltage adjustment circuit for power supply output is provided, including an input power supply, a power supply chip, a first resistor R1 and a second resistor R2, where the power supply chip is capable of adjusting a voltage output by the input power supply to a load, the power supply chip includes a reference power supply, an error amplifier U1 and a MOS transistor Q1, the voltage of the reference power supply is less than the voltage of the input power supply, the MOS transistor Q1 is an N-channel MOS transistor, the error amplifier U1 is capable of providing a linear state of operation of the adjustment MOS transistor Q1 to control an output voltage, an output end of the error amplifier U1 is connected to a gate of the MOS transistor Q1, one end of the reference power supply is grounded, the other end of the reference power supply is connected to a positive input end of the error amplifier U1, a drain of the MOS transistor Q1 is connected to the input power supply, and a source of the MOS transistor Q1 is connected to the load; the first resistor R1 and the second resistor R2 are connected in series to form a first branch, one end of the first branch is connected to the source electrode of the MOS transistor Q1, the other end of the first branch is grounded, and the connection point of the first resistor R1 and the second resistor R2 is connected to the negative input end of the error amplifier U1. Because the reference power supply, the error amplifier U1 and the MOS transistor Q1 are integrated, the negative input end of the error amplifier U1 is the feedback access point of the power supply chip, and the connection point of the first resistor R1 and the second resistor R2 is connected to the feedback access point, so that the power supply chip obtains the feedback voltage Vb。
When the voltage of the positive input end of the error amplifier U1 is greater than that of the negative input end thereof, the power chip increases the output by adjusting an MOS tube Q1; when the voltage of the positive input end of the error amplifier U1 is smaller than that of the negative input end thereof, the power chip adjusts the MOS tube Q1 to reduce the output. The voltage output by the power supply chip is not greater than the voltage of the input power supply, the resistance value of the first resistor R1 is greater than that of the second resistor R2, the second resistor R2 is grounded, so that the voltage obtained at the feedback access point is relatively less, and a reference power supply compared with the reference power supply can also be a low-voltage power supply correspondingly, so that the high voltage of the input voltage can be regulated and controlled by the low voltage of the reference power supply, and the voltage requirement of a load can be met.
In particular, the input voltage V of the input power supplyinIs regulated into an output voltage V after passing through a voltage chipoutThe output voltage VoutThe output can be regulated through the feedback of the first resistor R1 and the second resistor R2, and the output voltage V is obtained after the relevant power supply is startedoutThe calculation formula is as follows:
accordingly, the feedback voltage calculation formula of the feedback access point is as follows:
the feedback voltage V is fed back by the error amplifier inside the power chipbAnd a reference supply voltage VrMaking a comparison if VbLower than the reference supply voltage VrThe power supply chip will increase the output until the feedback voltage VbAnd a reference supply voltage VrAre equal. On the contrary, if VbHigher than the reference supply voltage VrThe power supply chip will reduce the output until the feedback voltage VbAnd a reference supply voltage VrAnd the voltage is equal to realize stable output of the single operation voltage of the load. For example, the load needs 3V voltage during operation, the input power supply is 5V, the voltage output to the load is equal to 3V through feedback regulation of the power supply chip, and if the input power supply is 5V and the loss is reduced to 4V, the MOS transistor Q1 is adjusted through feedback regulation of the power supply chip, so that the voltage output to the load is unchanged.
In an embodiment of the present invention, referring to fig. 1, the voltage dynamic adjustment circuit further includes a third resistor R3 and a capacitor C1, the third resistor R3 and the capacitor C1 are connected in series to form a second branch, one end of the second branch is connected to the PWM interface of the load, the other end of the second branch is grounded, and a connection point of the third resistor R3 and the capacitor C1 is connected to a connection point of the first resistor R1 and the second resistor R2.
If the load needs to adjust the voltage, the duty ratio of PWM is adjusted to adjust the feedback voltage VbThereby adjusting the output voltage Vout. Such as the load desired VoutWhen the PWM output duty ratio of the load is reduced, the PWM output duty ratio of the load is increased, a stable voltage is obtained through a filter circuit formed by a third resistor R3 and a capacitor C1 after the PWM output duty ratio is increased, and the voltage and the feedback voltage are superposed to ensure that V is obtainedbIncreasing, the power chip will VbAnd a reference supply voltage VrAfter comparison, V was foundbBecome large, Vb>VrThe power chip can consider VoutIncrease, at which point V is decreasedoutThereby making VbDecrease until Vb＝Vr；
Then, the load again expects VoutWhen the voltage rises, the PWM output duty ratio of the load is reduced, and after the PWM duty ratio is reduced, a stable voltage is obtained through a filter circuit formed by a third resistor R3 and a capacitor C1, wherein the voltage is V which is hoped to be higher than the voltage of the loadoutWhen the voltage is reduced, the obtained stable voltage is small, and after the stable voltage is superposed with the feedback voltage, V is enabledbRelatively reduced, the power supply chip will VbAnd a reference supply voltage VrAfter comparison, V was foundbBecome small, the power supply chip can consider VoutDecrease, at which point V is increasedoutThereby making VbIncrease until Vb＝Vr。
When the load does not need to be adjusted to the high voltage or the low voltage, the PWM stops outputting, and the scheme of the previous embodiment is adopted to carry out stable output on the constant value and the constant voltage.
In a preferred embodiment of this embodiment, referring to fig. 2, the voltage dynamic adjustment circuit further includesOne end of the fourth resistor R4 is connected to a connection point of the third resistor R3 and the capacitor C1, and the other end of the fourth resistor R4 is connected to a connection point of the first resistor R1 and the second resistor R2. The fourth resistor R4 has a larger resistance, for example, 100K Ω, which is larger than the third resistor R3, and can reduce the current influence of the output of the feedback access point corresponding to the PWM interface, so that VbGreater or less than VrOne point, the adjustment of the error amplifier to the MOS transistor Q1 is smoother, the service life of the related electronic components is protected, for example, the load needs to be reduced by 3V voltage, the voltage fed back to the feedback access point is only increased by 0.3V through the superposition of the PWM voltage, the small amplitude is greater than Vr, and the level output by the error amplifier is slowly reduced in the dynamic adjustment process, so that the output of the electronic chip is reduced.
In one embodiment of the utility model, an intelligent power supply is provided, which comprises the voltage dynamic adjusting circuit. The intelligent power supply stably outputs voltage to the load and correspondingly adjusts the voltage along with the adjustment of the voltage required by the load, for example, different voltage requirements can be met when the load is switched to different working modes, and the intelligent power supply can timely respond to the change and output corresponding voltage. The idea of the embodiment of the intelligent power supply and the working process of the voltage dynamic adjustment circuit in the embodiment belong to the same idea, and the whole content of the embodiment of the voltage dynamic adjustment circuit is incorporated into the embodiment of the intelligent power supply by full-text reference, which is not repeated.
The voltage dynamic adjusting circuit for power supply output and the intelligent power supply thereof provided by the utility model replace a chip with a communication interface by using simple circuit elements, so that the cost is greatly reduced, and the voltage feedback data is more accurate, the adjusting speed is high, the anti-interference capability is strong, and the reliability is high.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the utility model, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A voltage dynamic adjustment circuit for power supply output is characterized by comprising an input power supply, a power supply chip, a first resistor R1 and a second resistor R2, wherein the power supply chip is used for adjusting the voltage output by the input power supply to a load, the power supply chip comprises a reference power supply, an error amplifier U1 and a MOS transistor Q1, the error amplifier U1 is used for adjusting the working linear state of the MOS transistor Q1, the output end of the error amplifier U1 is connected to the grid of the MOS transistor Q1, one end of the reference power supply is grounded, the other end of the reference power supply is connected to the positive input end of the error amplifier U1, the drain of the MOS transistor Q1 is connected to the input power supply, and the source of the MOS transistor Q1 is used for being connected to the load;
the first resistor R1 and the second resistor R2 are connected in series to form a first branch, one end of the first branch is connected to the source electrode of the MOS transistor Q1, the other end of the first branch is grounded, and the connection point of the first resistor R1 and the second resistor R2 is connected to the negative input end of the error amplifier U1.
2. The voltage dynamic adjustment circuit according to claim 1, further comprising a third resistor R3 and a capacitor C1, wherein the third resistor R3 is connected in series with the capacitor C1 to form a second branch, one end of the second branch is connected to the PWM interface of the load, the other end of the second branch is connected to ground, and a connection point of the third resistor R3 and the capacitor C1 is connected to a connection point of the first resistor R1 and the second resistor R2.
3. The voltage dynamic adjustment circuit of claim 2, further comprising a fourth resistor R4, wherein one end of the fourth resistor R4 is connected to a connection point of the third resistor R3 and the capacitor C1, and the other end of the fourth resistor R4 is connected to a connection point of the first resistor R1 and the second resistor R2.
4. The dynamic voltage regulation circuit of claim 3, wherein the fourth resistor R4 has a larger resistance than the third resistor R3.
5. The circuit of claim 1, wherein when the voltage at the positive input terminal of the error amplifier U1 is greater than the voltage at the negative input terminal thereof, the power chip increases the output; when the voltage of the positive input end of the error amplifier U1 is smaller than that of the negative input end thereof, the power chip reduces the output.
6. The circuit of claim 1, wherein the voltage of the reference power supply is less than the voltage of the input power supply, and the voltage output by the power chip is not greater than the voltage of the input power supply.
7. The dynamic voltage regulation circuit of claim 6, wherein the resistance of the first resistor R1 is greater than the resistance of the second resistor R2, and the second resistor R2 is grounded.
8. The voltage dynamic adjustment circuit of claim 1, wherein the reference power supply, the error amplifier U1 and the MOS transistor Q1 are integrated, and the negative input terminal of the error amplifier U1 is used as a feedback access point of the power supply chip.
9. The voltage dynamic adjustment circuit of claim 1, wherein the MOS transistor Q1 is an N-channel MOS transistor.
10. An intelligent power supply, characterized by comprising the voltage dynamic adjustment circuit of any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123223588.1U CN216873077U (en) | 2021-12-21 | 2021-12-21 | Voltage dynamic adjustment circuit for power output and intelligent power supply thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202123223588.1U CN216873077U (en) | 2021-12-21 | 2021-12-21 | Voltage dynamic adjustment circuit for power output and intelligent power supply thereof |
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| CN216873077U true CN216873077U (en) | 2022-07-01 |
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| CN202123223588.1U Active CN216873077U (en) | 2021-12-21 | 2021-12-21 | Voltage dynamic adjustment circuit for power output and intelligent power supply thereof |
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