CN216872087U

CN216872087U - Low-power consumption wake-up circuit

Info

Publication number: CN216872087U
Application number: CN202220095462.6U
Authority: CN
Inventors: 曹宇宁; 缪爱军; 王明仁
Original assignee: Weizman Power Suzhou Co ltd
Current assignee: Weizman Power Suzhou Co ltd
Priority date: 2022-01-14
Filing date: 2022-01-14
Publication date: 2022-07-01
Anticipated expiration: 2032-01-14

Abstract

The utility model discloses a low-power consumption wake-up circuit, which comprises a first MOS (metal oxide semiconductor) tube, a second MOS tube, a key, an MCU (micro control unit) and a power management chip, wherein the first MOS tube is connected with the second MOS tube; the first MOS tube is a PMOS tube, a first resistor is connected between a grid electrode and a source electrode of the first MOS tube, the grid electrode of the first MOS tube is connected with the key through a second resistor, the source electrode of the first MOS tube is connected with the anode of the battery, and a drain electrode of the first MOS tube is connected with the power management chip and the charging interface; the second MOS transistor is an NMOS transistor, a third resistor is connected between a grid electrode and a source electrode of the second MOS transistor, the grid electrode of the second MOS transistor is connected with the MCU through a fourth resistor, a drain electrode of the second MOS transistor is connected with the grid electrode of the first MOS transistor through a fifth resistor, and the source electrode of the second MOS transistor is grounded; the circuit connected with the key is grounded after the key is pressed. In the utility model, when the system is idle, the first MOS tube cuts off the output circuit of the battery, the first MOS tube is conducted after a user presses a key, and the MCU acts on the second MOS tube through the fourth resistor to enable the system to be self-locked, so that the system is awakened.

Description

Low-power consumption wake-up circuit

Technical Field

The utility model relates to the technical field of charging management circuits, in particular to a low-power-consumption wake-up circuit.

Background

The BMS battery system is commonly called a battery caregiver or a battery manager, and is mainly used for intelligently managing and maintaining each battery unit, preventing overcharge and overdischarge of the battery, prolonging the service life of the battery, and monitoring the state of the battery. When the existing BMS battery system is in an idle state, the power consumption is high, so that the electric quantity stored in the battery is consumed, and a user often finds that the residual electric quantity of the battery is less when the user wants to use the battery after idling tools for a long time, so that the user experience is reduced.

Disclosure of Invention

The purpose of the utility model is as follows: in order to overcome the defects in the prior art, the utility model provides a low-power consumption wake-up circuit for solving the problem of overhigh self-power consumption of a BMS battery system in an idle state.

The technical scheme is as follows: in order to achieve the purpose, the low-power consumption wake-up circuit comprises a first MOS tube, a second MOS tube, a key, an MCU and a power management chip;

the first MOS tube is a PMOS tube, a first resistor is connected between a grid electrode and a source electrode of the first MOS tube, the grid electrode of the first MOS tube is connected with the key through a second resistor, the source electrode of the first MOS tube is connected with the anode of the battery, and a drain electrode of the first MOS tube is connected with the power management chip and the charging interface;

the second MOS tube is an NMOS tube, a third resistor is connected between a grid electrode and a source electrode of the second MOS tube, the grid electrode of the second MOS tube is connected with the MCU through a fourth resistor, a drain electrode of the second MOS tube is connected with the grid electrode of the first MOS tube through a fifth resistor, and the source electrode of the second MOS tube is grounded;

and the circuit connected with the key is grounded after the key is pressed.

Further, the device also comprises a third MOS tube;

the third MOS tube is an NMOS tube, a sixth resistor is connected between the grid electrode and the source electrode of the third MOS tube, the grid electrode of the third MOS tube is connected with the key, the source electrode of the third MOS tube is grounded, the drain electrode of the third MOS tube is connected with the output end of the power management chip through a seventh resistor, and the drain electrode of the third MOS tube is connected with the MCU.

Furthermore, the grid electrode of the second MOS tube is connected with an input pin through an eighth resistor, and when the charging interface is connected with a charger, the input pin generates voltage.

Further, the drain electrode of the first MOS tube is connected with the power management chip through a step-down switching regulator.

Further, the MCU is also connected with a detection element for detecting the output current of the battery.

Furthermore, a voltage stabilizing diode is connected in series on a line where the fourth resistor is located.

Furthermore, a voltage stabilizing diode is connected in series on a line where the eighth resistor is located.

Further, a voltage stabilizing diode and a capacitor are connected in parallel between two ends of the first resistor.

Further, a voltage stabilizing diode and a capacitor are connected in parallel between two ends of the sixth resistor.

Has the advantages that: in the low-power-consumption wake-up circuit, when a system is idle, an output circuit of a battery is cut off through the first MOS tube, the first MOS tube is conducted after a user presses a key, and the MCU acts on the second MOS tube through the fourth resistor to enable the system to be self-locked, so that the wake-up of the system is realized.

Drawings

FIG. 1 is a circuit diagram of a low power wake-up circuit;

FIG. 2 is a detailed circuit diagram of a buck switching regulator circuit;

fig. 3 is a specific circuit diagram of the power management chip circuit.

Detailed Description

The present invention will be further described with reference to the accompanying drawings.

As shown in fig. 1, the low power consumption wake-up circuit can be used in a battery management system of an electric power assisted vehicle (e.g., an electric vehicle, an electric scooter, an electric power assisted vehicle, etc.), and includes a first MOS transistor Q1, a second MOS transistor Q2, a key SW, an MCU, and a power management chip U1;

the first MOS transistor Q1 is a PMOS transistor, a first resistor R1 is connected between the gate and the source of the first MOS transistor Q1, and a zener diode and a capacitor are connected in parallel with the first resistor R1 to ensure the safety of the first MOS transistor Q1; the grid electrode of the first MOS tube Q1 is connected with the key SW through a second resistor R2, the source electrode of the first MOS tube Q1 is connected with the battery anode BATT +, and the drain electrode of the first MOS tube Q1 is connected with the power management chip U1 and the charging interface VT; the battery anode BATT + is connected with the battery.

The second MOS transistor Q2 is an NMOS transistor, a third resistor R3 is connected between the gate and the source, the gate is connected to the MCU through a fourth resistor R4 and a zener diode, and in fig. 1, the MCU is connected to a line where the fourth resistor R4 is located through an MPOWER; the drain electrode of the second MOS transistor Q2 is connected with the grid electrode of the first MOS transistor Q1 through a fifth resistor R5, and the source electrode of the second MOS transistor Q2 is grounded;

the circuit connected with the key SW is grounded after the key SW is pressed, the key SW is a self-resetting key, the key SW in the figure 1 comprises four

pins

1, 2, 3 and 4, the

pins

3 and 4 are grounded, and the

pins

1 and 2 can be grounded after the key SW is pressed.

In addition, the low-power wake-up circuit further comprises a third MOS tube Q3;

the third MOS transistor Q3 is an NMOS transistor, a sixth resistor R6 is connected between the gate and the source of the third MOS transistor Q3, and a zener diode and a capacitor are connected in parallel with the sixth resistor R6 to ensure the safety of the third MOS transistor Q3; the gate of the switch is connected with the key SW, the source of the switch is grounded, the drain of the switch is connected with the output end VDD of the power management chip U1 through a seventh resistor R7, and the drain of the switch is connected with the MCU, wherein in the figure 1, the MCU is connected with the drain of a third MOS tube Q3 through KYEIN.

Preferably, the gate of the second MOS transistor Q2 is connected to the input pin VCC through the eighth resistor R8 and the zener diode, and when the charging interface VT is connected to the charger, the input pin VCC generates a voltage.

In addition, preferably, the drain of the first MOS transistor Q1 is connected to the power management chip U1 through a buck switching regulator U2. Specific circuit diagrams of the buck switching regulator circuit and the power management chip circuit are respectively shown in fig. 2 and fig. 3, and since the buck switching regulator circuit and the power management chip circuit belong to conventional designs, detailed descriptions thereof are omitted in the present application. 5VDD in fig. 2 corresponds to 5VDD in fig. 3.

Preferably, the MCU is further connected to a detection element for detecting an output current of the battery.

Preferably, the model of the power management chip U1 is CX1117C33, and the model of the step-down switching regulator U2 is LM 5008A.

The operation principle of the low power consumption is as follows:

in the idle state, the first MOS transistor Q1, the second MOS transistor Q2, and the third MOS transistor Q3 are all in the off state.

When a user presses the key SW, the first MOS tube Q1 is conducted, and the battery anode BATT + can supply power to the power management chip U1; after the key SW is pressed down, the third MOS transistor Q3 is also turned on, KEYIN in fig. 1 detects a low level, the MCU knows that the key SW is pressed down, and outputs a high level through MPOWER to turn on the second MOS transistor Q2, so that the first MOS transistor Q1 is always in a conducting state to realize system self-locking, the battery anode BATT + continuously supplies power to the power management chip U1, and the system is completely awakened.

In the first case, when the user presses the key SW again, the third MOS transistor Q3 is turned on again, and the KEYIN detects a low level, the MCU knows that the key SW is pressed and knows that the user is about to end the power supply, and thus outputs the low level through the MPOWER, so that the second MOS transistor Q2 is turned off, the first MOS transistor Q1 is also turned off, and the system returns to the idle state.

In the second case, when the MCU knows that the current is smaller than the set value (e.g., 10mA) through the detection element and the time reaches the set value (e.g., 12 hours), the MCU outputs a low level through the MPOWER to turn off the second MOS transistor Q2, the first MOS transistor Q1 is also turned off, and the system returns to the idle state.

In addition, when the system is in an idle state, if the charging interface VT is connected to the charger, the input pin VCC generates a voltage, and the input pin VCC acts on the second MOS transistor Q2 through the eighth resistor R8 and the zener diode, so that the second MOS transistor Q2 is turned on, and thus, the first MOS transistor Q1 is turned on, and then the MCU is interlocked through the MPOWER.

The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the utility model and these are intended to be within the scope of the utility model.

Claims

1. A low-power consumption wake-up circuit is characterized by comprising a first MOS tube, a second MOS tube, a key, an MCU and a power management chip;

the first MOS transistor is a PMOS transistor, a first resistor is connected between a grid electrode and a source electrode of the first MOS transistor, the grid electrode of the first MOS transistor is connected with the key through a second resistor, the source electrode of the first MOS transistor is connected with a battery anode, and a drain electrode of the first MOS transistor is connected with the power management chip and the charging interface;

and the circuit connected with the key is grounded after the key is pressed.

2. The low-power wake-up circuit according to claim 1, further comprising a third MOS transistor;

3. The wake-up circuit with low power consumption of claim 1, wherein the gate of the second MOS transistor is simultaneously connected to an input pin through an eighth resistor, and when the charging interface is connected to a charger, the input pin generates a voltage.

4. The wake-up circuit with low power consumption of claim 1, wherein the drain of the first MOS transistor is connected to the power management chip through a buck switching regulator.

5. The wake-up circuit with low power consumption of claim 1, wherein the MCU is further connected to a detection element for detecting the output current of the battery.

6. The wake-up circuit with low power consumption of claim 1, wherein a zener diode is connected in series to a line on which the fourth resistor is located.

7. The wake-up circuit with low power consumption of claim 3, wherein a zener diode is connected in series to a line on which the eighth resistor is located.

8. The wake-up circuit with low power consumption of claim 1, wherein a voltage regulator diode and a capacitor are connected in parallel between two ends of the first resistor.

9. The wake-up circuit with low power consumption of claim 2, wherein a zener diode and a capacitor are connected in parallel between two ends of the sixth resistor.