CN216848122U

CN216848122U - Active beam control unit

Info

Publication number: CN216848122U
Application number: CN202123227427.XU
Authority: CN
Inventors: 胡徐松; 徐克兴
Original assignee: Dfine Technology Co Ltd
Current assignee: Dfine Technology Co Ltd
Priority date: 2021-12-21
Filing date: 2021-12-21
Publication date: 2022-06-28
Anticipated expiration: 2031-12-21

Abstract

The utility model discloses an active wave beam control unit, which comprises a TR channel unit, a calibration source, a digital processing board, a power division network, a sum and difference device, a switch module and a power supply module; the digital processing board is respectively connected with the power supply module, the calibration source, the switch module and the TR channel unit; the power supply module is respectively connected with the digital processing board, the calibration source, the switch module and the TR channel unit; the power division network is respectively connected with the sum and difference device and the TR channel unit; the switch module is respectively connected with the calibration source module and the sum and difference device; the TR channel unit is provided with an input and output common end I and an input and output common end II, the input and output common end I is connected with an external antenna, and the input and output common end 2 is connected with a power distribution network. The utility model relates to a phased array radar's front end can be applied to the machine and carries the system, realizes system communication, and it is high to have the circuit integration degree, and is small, compact structure, advantages such as reliability height.

Description

Active beam control unit

Technical Field

The utility model relates to a phased array radar technical field especially relates to an active beam control unit.

Background

A wave beam (wave beam) refers to a shape formed on the earth surface by electromagnetic waves emitted from a satellite antenna (for example, a light beam emitted to a dark place like a flashlight). Mainly comprises a global beam, a point-shaped beam and a shaped beam. They are shaped by the transmitting antenna.

A phased array antenna (phased array antenna) is an antenna that changes the shape of a pattern by controlling the feeding phase of a radiating element in the array antenna. The control phase can change the direction of the maximum value of the antenna pattern so as to achieve the purpose of beam scanning.

In a reconnaissance mode of the radar countermeasure system, an antenna array surface is combined with a multi-beam network unit to realize the formation of receiving multiple beams, and the system reconnaissance of signals of different wave positions only needs to schedule the multiple beams, so that quick and quick beam scanning can be realized. The beam is swept rapidly from one direction to another, creating multiple independent beams, or rapidly switching a single beam to view multiple targets. These require rapid scheduling of the listening beams to point the beams to the area to be scanned or to the target to be tracked.

The beam control scheme used by the existing countermeasure system is mainly a PC-104 computer module + FPGA chip architecture in the field of industrial control, the PC-104 module is in butt joint with the module through a bottom plate for electrical connection, and under the high-vibration-level environment of an onboard environment, the architecture has the hidden danger of poor contact and cannot meet the requirement of high reliability of the system. Meanwhile, in order to intercept target radar signals as much as possible, the detection device usually needs 360-degree omni-directional beam control, in order to simplify the control, a large array surface is usually divided into a plurality of sub-arrays for processing, a central beam control unit distributes instructions to each sub-array beam control unit, and meanwhile, the design of the central beam control unit can be unified and modularized with that of the sub-array beam control units, so that the system design is simplified, and the system expansion is facilitated. Traditional wave control instruction and data are transmitted to each subarray through electric signals, the electric signals are easily interfered by airborne high electromagnetic environment under the airborne severe electromagnetic environment, and the longer the communication link is, the heavier the cable is. In order to shorten the phase time for the sub-array antenna and to reduce the weight of the transmission cable, optical fibers are used for controlling the transmission of the data stream. The PowerPC processor has the advantage of high reliability of a general embedded system, the FPGA is used as a special integrated circuit, the defect of a customized circuit is overcome, the defect that the gate circuit quantity of the original programmable device is limited is overcome, and the PowerPC processor has the characteristics of flexible architecture and logic units, high integration level, wide application range and the like. The radar countermeasure system interception beam control system combining the PowerPC and the FPGA can fully utilize the high-performance processing capability of the PowerPC and the customized circuit design capability of the FPGA, and simultaneously considers the factors such as power consumption, cost, design period and the like, and is an effective solution for the radar countermeasure system interception beam control system with small volume requirement, light load requirement and high calculation capability requirement. In circuit design, QorQP 2020 of Freescale company is selected as a main control chip, each parameter of the system is configured, and as the system needs to perform data interaction with a plurality of working units of the countermeasure system, in order to reduce the types of interface chips, the connection of interfaces is performed by adopting FPGA.

In patent CN201611165128.9, a detective beam control system and method applied to an airborne radar countermeasure system is disclosed, which includes a central beam control unit, a plurality of front plane beam control units, and a plurality of sets of unit components corresponding to the plurality of front plane beam control units. Each group of unit components comprises a weighting amplification unit, a beam selection switch unit and a compensation amplification unit. The central beam control unit acquires a control instruction from a master control center of the airborne radar countermeasure system, packages the control instruction and data according to a specified protocol, and distributes the packaged control instruction and data to corresponding array plane beam control units; the wave array beam control unit which receives the distribution command sends a wave beam selection switch command to the corresponding wave beam selection switch unit, and simultaneously, the amplitude weighted code and the phase compensation code are respectively sent to the corresponding weighting amplification unit and the corresponding compensation amplification unit for carrying out compensation amplification on the received wave beam. The active beam control of the scheme is applied to the front end of the phased array radar to realize the receiving and the transmitting of radio frequency signals; however, for the front end of the phased array radar, how to transmit and receive radio frequency signals, and how to amplify, phase shift, and convert signals cannot be solved.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome prior art's is not enough, provide an active beam control unit.

The purpose of the utility model is realized through the following technical scheme:

an active beam control unit comprises a TR channel unit, a calibration source, a digital processing board, a power division network, a sum-difference device, a switch module and a power supply module; the digital processing board is respectively connected with the power supply module, the calibration source, the switch module and the TR channel unit; the power supply module is respectively connected with the digital processing board, the calibration source, the switch module and the TR channel unit; the power division network is respectively connected with the sum and difference device and the TR channel unit; the switch module is respectively connected with the correction source module and the sum and difference device; the TR channel unit is provided with an input and output common end I and an input and output common end II, the input and output common end I is connected with an external antenna, and the input and output common end 2 is connected with a power distribution network.

Further, the TR channel unit includes 10 TR channel subunits.

Furthermore, the TR channel subunit comprises a programmable attenuator, a phase shifter, a transceiving switch, an amplifier I, an amplifier II, an amplitude limiter, a circulator and a filter, wherein the programmable attenuator, the phase shifter, the transceiving switch, the amplifier I, the circulator and the filter are sequentially connected from the common end I to the common end II; an amplifier II and an amplitude limiter are also connected between the transceiving switch and the circulator.

Further, the calibration source comprises a frequency source and a one-to-two power divider, wherein the frequency source comprises a crystal oscillator, an attenuator I, an amplifier, a filter, an attenuator II and a VCO; the output end of the crystal oscillator is connected with the input end of the attenuator I; the output end of the attenuator I is connected with the input end of the amplifier; the output end of the amplifier is connected with the input end of the filter; the output end of the filter is connected with the input end of the attenuator II; the output end of the attenuator II is connected with the input end of the VCO; the output end of the VCO is connected with the input end of the one-to-two power divider; the output end of the one-to-two power divider is respectively connected with the receiving calibration end and the transmitting calibration end.

Further, the digital processing board comprises a crystal oscillator, a communication interface, a control processor FPGA, an external memory FLASH, a temperature sensor, a reset chip and a receiving and transmitting switch drive and control interface; the output end of the crystal oscillator is connected with the input end of a clock pin of the FPGA of the control processor; the communication interface is connected with a pin of the control processor FPGA; the external memory FLASH is connected with a special configuration pin of the control processor FPGA; the output end of the temperature sensor is connected with an IO pin of the FPGA; the output end of the reset chip is connected with a special reset pin of the control processor FPGA; the receiving and transmitting switch driving input end is connected with an IO pin of the control processor FPGA; the control interface is connected with an IO pin of the control processor FPGA.

Further, the switch module includes a switch SW1, a switch SW2, a switch SW3, a switch SW4, a switch SW5, an attenuator 1, an attenuator 2, a one-to-two power divider 1, and a one-to-two power divider 2; a port 1 of the switch SW1 is connected with a port 2 of the switch SW5, a port 2 is connected with an output end of the one-to-two power divider 1, and a port 3 is connected with a common port of the power dividing network; the other output end of the one-to-two power divider 1 is connected with a port 1 of a switch SW5, and the input end of the one-to-two power divider is connected with a calibration source emission calibration end; the 3 port of the switch SW5 is connected with an external port sigma; a port 1 of the switch SW2 is connected to an attenuator 1, a port 2 is connected to a common port of the power distribution network, and a port 3 is connected to an external port Δ; a port 1 of the switch SW3 is connected to an output end of the one-to-two power divider 2, a port 2 is connected to a port 1 of the switch SW4, and a port 3 is connected to the attenuator 1; the input end of the one-to-two power divider 2 is connected with a calibration source receiving calibration end, the other output end of the one-to-two power divider is connected with the port 2 of the switch SW4, the port 1 of the switch SW4 is connected with the port 2 of the switch SW3, the port 2 is connected with the other output end of the one-to-two power divider 2, and the port 3 is connected with the attenuator 2; the other end of the attenuator 2 is connected with an antenna coupling port.

Furthermore, the power supply module comprises a power supply submodule I and a power supply submodule II, the input ends of the power supply submodule I and the power supply submodule II are both connected with an external input power supply, the output end of the power supply submodule I is connected with the TR channel unit, and the output end of the power supply module 2 is connected with the DCDC 1; the output end of the DCDC1 is respectively connected with an FPGA power supply pin, an LDO1, an LDO2, an LDO3, an LDO4, an LDO5, an LDO6, an LDO7, an LDO8, an LDO9, an LDO10 and an LDO 11; the LDO1, the LDO2, the LDO3, the LDO4, the LDO5, the LDO6, the LDO7, the LDO8, the LDO9 and the LDO10 are respectively connected with the TR channel sub-unit; the output end of the LDO11 is connected with a calibration source and a switch module.

The utility model has the advantages that: the utility model relates to a phased array radar's front end can be applied to the machine and carries the system in, realizes system communication, and the main function is for receiving and transmitting radio frequency signal, and it is high to have the circuit integration degree, and is small, compact structure, advantages such as reliability height.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

Fig. 1 is a schematic block diagram of a system configuration.

FIG. 2 is a schematic block diagram of a TR channel unit.

FIG. 3 is a functional block diagram of a calibration source.

FIG. 4 is a schematic block diagram of a digital processing board.

Fig. 5 is a functional block diagram of a switch module.

FIG. 6 is a schematic block diagram of a power module.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

In this embodiment, as shown in fig. 1, an active beam control unit includes a TR channel, a calibration source, a digital processing board, a power division network, a sum and difference device, a switch module, and a power supply module.

The input and output common end I of the TR channel unit is connected with an external antenna, and the input and output common end II is connected with the power distribution network unit; the public end of the power division network unit is connected with the sum and difference unit; the sum and difference unit is connected with the switch module unit; the switch module unit is respectively connected with the frequency source unit and the external interface; the frequency source unit is connected with the digital processing board unit; and the power supply module unit is respectively connected with the digital processing board unit, the frequency source unit, the switch module unit and the TR channel unit.

In the embodiment of the present application, as shown in fig. 2, the TR channel unit includes a programmable attenuator, a phase shifter, a transceiver switch, an amplifier 1, an amplifier 2, a limiter, a circulator, and a filter.

When the TR channel is in a transmitting state, the input end of the program-controlled attenuator is connected with the input and output common end 1, and the output end of the program-controlled attenuator is connected with the input end of the phase shifter; the input end of the phase shifter is connected with the output end of the program-controlled attenuator, and the output end of the phase shifter is connected with the input end of the receiving and transmitting switch; the input end of the receiving and transmitting switch is connected with the output end of the phase shifter, and the output end of the receiving and transmitting switch is connected with the input end of the amplifier 1; the output end of the amplifier 1 is connected with the input end of the circulator; the output end of the circulator is connected with the input end of the filter; the output end of the filter is connected with the input and output common end 2.

When the TR channel is in a receiving state, the input end of the filter is connected with the input and output public end 2, and the output end of the filter is connected with the circulator; the output end of the circulator is connected with the input end of the amplitude limiter; the output end of the amplitude limiter is connected with the amplifier 2; the output end of the amplifier 2 is connected with a receiving and transmitting switch; the output end of the receiving and transmitting switch is connected with the phase shifter; the output end of the phase shifter is connected with the programmable attenuator; the output end of the programmable attenuator is connected with an input public end 1 and an output public end 1.

In the embodiment of the present application, as shown in fig. 3, the calibration source includes a power divider with two divisions and a frequency source, where the frequency source includes a crystal oscillator, an attenuator I, an amplifier, a filter, an attenuator II, and a VCO (i.e., a frequency synthesizer with a built-in VCO).

The output end of the crystal oscillator is connected with the input end of the attenuator I; the output end of the attenuator I is connected with the input end of the amplifier; the output end of the amplifier is connected with the input end of the filter; the output end of the filter is connected with the input end of the attenuator II; the output end of the attenuator II is connected with the input end of the VCO; the output end of the VCO is connected with the input end of the one-to-two power divider; the output end of the one-to-two power divider is respectively connected with the receiving calibration end and the transmitting calibration end.

As shown in fig. 4, in the embodiment of the present application, the digital processing board unit includes a crystal oscillator, a communication interface, a control processor FPGA, an external memory FLASH, a temperature sensor, a reset chip, and a transceiver switch driving and control interface.

The output end of the crystal oscillator is connected with the input end of a clock pin of the FPGA of the control processor; the communication interface is connected with a pin of the FPGA of the control processor; the external memory FLASH is connected with a special configuration pin of the control processor FPGA; the output end of the temperature sensor is connected with an IO pin of the FPGA; the output end of the reset chip is connected with a special reset pin of the control processor FPGA; the receiving and transmitting switch driving input end is connected with an IO pin of the control processor FPGA; the control interface is connected with an IO pin of the control processor FPGA.

As shown in fig. 5, in the embodiment of the present application, the switch module unit includes a switch SW1, a switch SW2, a switch SW3, a switch SW4, a switch SW5, an attenuator 1, an attenuator 2, a one-to-two power divider 1, and a one-to-two power divider 2.

A port 1 of the switch SW1 is connected with a port 2 of the switch SW5, a port 2 is connected with an output end of the one-to-two power divider 1, and a port 3 is connected with a common port of the power dividing network; the other output end of the one-to-two power divider 1 is connected with a port 1 of a switch SW5, and the input end of the one-to-two power divider is connected with a calibration source emission calibration end; the 3 port of the switch SW5 is connected with an external port sigma; a port 1 of the switch SW2 is connected to an attenuator 1, a port 2 is connected to a common port of the power distribution network, and a port 3 is connected to an external port Δ; a port 1 of the switch SW3 is connected with the output end of the one-to-two power divider 2, a port 2 is connected with a port 1 of the switch SW4, and a port 3 is connected with the attenuator 1; the input end of the one-to-two power divider 2 is connected with a calibration source receiving calibration end, the other output end of the one-to-two power divider is connected with the port 2 of the switch SW4, the port 1 of the switch SW4 is connected with the port 2 of the switch SW3, the port 2 is connected with the other output end of the one-to-two power divider 2, and the port 3 is connected with the attenuator 2; the other end of the attenuator 2 is connected with an antenna coupling port.

As shown in fig. 6, in the embodiment of the present application, the power module unit includes power module 1, power module 2, DCDC1, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, LDO9, LDO10, LDO 11.

The input end of the power module 1 is connected with an external input 28V power supply, and the output end of the power module is connected with a TR channel; the input end of the power module 2 is connected with an external input 28V power supply, and the output end of the power module is connected with DCDC 1; the output end of the DCDC1 is respectively connected with an FPGA power supply pin, an LDO1, an LDO2, an LDO3, an LDO4, an LDO5, an LDO6, an LDO7, an LDO8, an LDO9, an LDO10 and an LDO 11; the output end of the LDO1 is connected with a TR channel 1; the output end of the LDO2 is connected with a TR channel 2; the output end of the LDO3 is connected with a TR channel 3; the output end of the LDO4 is connected with a TR channel 4; the output end of the LDO5 is connected with a TR channel 5; the output end of the LDO6 is connected with a TR channel 6; the output end of the LDO7 is connected with a TR channel 7; the output end of the LDO8 is connected with a TR channel 8; the output end of the LDO9 is connected with a TR channel 9; the output end of the LDO10 is connected with a TR channel 10; the output end of the LDO11 is connected with a calibration source and a switch module.

The working principle of the product is as follows:

the TR channel has the functions of transmitting and receiving, phase shifting, attenuating, amplifying, amplitude limiting and wave detecting, and the circuit adopts a chip design and works in a transmitting and receiving time-sharing mode. In the transmitting mode, a transmitting radio frequency signal enters an amplifier for amplification after passing through the program-controlled attenuation, the phase shifter and the receiving and transmitting switch, and finally is sent to an antenna after passing through the circulator and the filter. In a receiving mode, a received radio frequency signal enters the amplifier after passing through the filter, the circulator and the amplitude limiter, and then is output from the public port after passing through the transceiving switch, the phase shifter and the programmable attenuator.

The calibration source has the functions of attenuation, amplification, filtering and power division and provides a calibration signal for the TR channel. The crystal oscillator outputs a clock reference signal, the clock reference signal enters a frequency synthesizer after being attenuated, amplified and filtered, and the clock reference signal outputs a required calibration signal and then passes through a one-to-two power divider to be respectively used for receiving calibration and transmitting calibration.

The digital processing board completes control, communication and signal processing of each module and consists of a crystal oscillator, a communication interface, a control processor FPGA, an external memory FLASH, a temperature sensor, a reset chip, a receiving and transmitting switch drive and control interface. The crystal oscillator provides a working clock for the FPGA, the communication interface is used for communicating with an external interface, the FLASH is used for storing an FPGA program, the temperature sensor is used for monitoring the temperature of the module, the reset chip is used for power-on reset of the FPGA, the receiving and transmitting switch drive is used for controlling the receiving and transmitting switch in the TR channel, and the control interface is used for controlling the calibration source and the switch module and communicating with the outside through the RS 422.

The power division network mainly completes power division and synthesis of the radio frequency transceiving signals.

The sum-difference device mainly completes the conversion process of the transmitting-receiving signal phase.

The switch module mainly completes channel selection switching in a calibration mode and is used for channel calibration and selection of a radio frequency signal path in a normal transceiving mode.

The power module converts external power supply voltage into voltage required by each chip and supplies power to each module, + 28V voltage provided by the outside is converted by the power module 1 and then +36V is output to be directly used by a power amplifier of a TR channel, +12V voltage is output after being converted by the power module 2, +12V voltage is converted by the DC/DC1 and then + 3.3V, + 1.8V, + 1.0V is output to supply power to a digital board and an FPGA, +5.5V is output and then +5V is output through the LDO1 … … LDO10 respectively to supply power to the TR channel, and simultaneously +5V is output through the LDO11 to supply power to a calibration source and a switch module.

The structures, functions, and connections disclosed herein may be implemented in other ways. For example, the embodiments described above are merely illustrative, e.g., multiple components may be combined or integrated with another component; in addition, functional components in the embodiments herein may be integrated into one functional component, or each functional component may exist alone physically, or two or more functional components may be integrated into one functional component.

The foregoing is illustrative of the preferred embodiments of the present invention, and it is to be understood that the invention is not limited to the precise forms disclosed herein, and that various other combinations, modifications, and environments may be resorted to, falling within the scope of the invention as defined by the appended claims. But that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention, which is to be limited only by the claims appended hereto.

Claims

1. An active beam control unit is characterized by comprising a TR channel unit, a calibration source, a digital processing board, a power division network, a sum and difference device, a switch module and a power supply module; the digital processing board is respectively connected with the power supply module, the calibration source, the switch module and the TR channel unit; the power supply module is respectively connected with the digital processing board, the calibration source, the switch module and the TR channel unit; the power division network is respectively connected with the sum and difference device and the TR channel unit; the switch module is respectively connected with the calibration source module and the sum and difference device; the TR channel unit is provided with an input and output common terminal I and an input and output common terminal II, the input and output common terminal I is connected with an external antenna, and the input and output common terminal II is connected with a power distribution network.

2. The active beam steering element of claim 1 wherein the TR channel element includes 10 TR channel sub-elements.

3. The active beam control unit of claim 1, wherein the TR channel sub-unit comprises a programmable attenuator, a phase shifter, a transceiver switch, an amplifier I, an amplifier II, a limiter, a circulator and a filter, and the programmable attenuator, the phase shifter, the transceiver switch, the amplifier I, the circulator and the filter are connected in sequence from a common terminal I to the common terminal II; an amplifier II and an amplitude limiter are also connected between the transceiving switch and the circulator.

4. The active beam steering unit of claim 1, wherein the calibration source comprises a frequency source and a one-to-two power divider, the frequency source comprises a crystal oscillator, an attenuator I, an amplifier, a filter, an attenuator II, and a VCO; the output end of the crystal oscillator is connected with the input end of the attenuator I; the output end of the attenuator I is connected with the input end of the amplifier; the output end of the amplifier is connected with the input end of the filter; the output end of the filter is connected with the input end of the attenuator II; the output end of the attenuator II is connected with the input end of the VCO; the output end of the VCO is connected with the input end of the one-to-two power divider; the output end of the one-to-two power divider is respectively connected with the receiving calibration end and the transmitting calibration end.

5. The active beam control unit of claim 1, wherein the digital processing board comprises a crystal oscillator, a communication interface, a control processor FPGA, an external memory FLASH, a temperature sensor, a reset chip, a transceiver switch driver and a control interface; the output end of the crystal oscillator is connected with the input end of a clock pin of the FPGA of the control processor; the communication interface is connected with a pin of the control processor FPGA; the external memory FLASH is connected with a special configuration pin of the control processor FPGA; the output end of the temperature sensor is connected with an IO pin of the FPGA; the output end of the reset chip is connected with a special reset pin of the FPGA of the control processor; the receiving and transmitting switch driving input end is connected with an IO pin of the control processor FPGA; the control interface is connected with an IO pin of the control processor FPGA.

6. The active beam control unit of claim 1 wherein the switch module comprises a switch SW1, a switch SW2, a switch SW3, a switch SW4, a switch SW5, an attenuator 1, an attenuator 2, a one-to-two power divider 1, a one-to-two power divider 2; a port 1 of the switch SW1 is connected with a port 2 of the switch SW5, a port 2 is connected with an output end of the one-to-two power divider 1, and a port 3 is connected with a common port of the power dividing network; the other output end of the one-to-two power divider 1 is connected with a port 1 of a switch SW5, and the input end of the one-to-two power divider is connected with a calibration source emission calibration end; the 3 port of the switch SW5 is connected with an external port sigma; a port 1 of the switch SW2 is connected with an attenuator 1, a port 2 is connected with a common port of the power distribution network, and a port 3 is connected with an external port delta; a port 1 of the switch SW3 is connected to an output end of the one-to-two power divider 2, a port 2 is connected to a port 1 of the switch SW4, and a port 3 is connected to the attenuator 1; the input end of the one-to-two power divider 2 is connected with a calibration source receiving calibration end, and the other output end of the one-to-two power divider is connected with the 2 port of the switch SW 4; the switch SW4 has a port 1 connected to the port 2 of the switch SW3, a port 2 connected to the other output terminal of the one-to-two power divider 2, and a port 3 connected to the attenuator 2 and the antenna coupling port.

7. The active beam control unit of claim 2, wherein the power module comprises a power sub-module I, a power sub-module II, DCDC1, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, LDO9, LDO10, and LDO11, wherein the input terminals of the power sub-module I and the power sub-module II are connected to an external input power source, the output terminal of the power sub-module I is connected to the TR channel unit, and the output terminal of the power module 2 is connected to DCDC 1; the output end of the DCDC1 is respectively connected with an FPGA power supply pin, an LDO1, an LDO2, an LDO3, an LDO4, an LDO5, an LDO6, an LDO7, an LDO8, an LDO9, an LDO10 and an LDO 11; the LDO1, the LDO2, the LDO3, the LDO4, the LDO5, the LDO6, the LDO7, the LDO8, the LDO9 and the LDO10 are respectively connected with the TR channel sub-unit; the output end of the LDO11 is connected with a calibration source and a switch module.