CN216751693U

CN216751693U - Adjustable equalizer and multi-order adjustable equalizer

Info

Publication number: CN216751693U
Application number: CN202220232729.1U
Authority: CN
Inventors: 不公告发明人
Original assignee: Shijiazhuang Chuangtian Electronic Technology Co ltd
Current assignee: Shijiazhuang Chuangtian Electronic Technology Co ltd
Priority date: 2022-01-27
Filing date: 2022-01-27
Publication date: 2022-06-14
Anticipated expiration: 2032-01-27

Abstract

The embodiment of the application relates to a debuggable equalizer and a multi-stage debuggable equalizer, wherein the debuggable equalizer comprises a first resistor R1, a second resistor R2 with a first end connected with a first end of a first resistor R1, a second end connected with a second end of a second resistor R2, a third resistor R3 with a second end connected with a second end of a first resistor R1, a first end connected with a first end of a second resistor R2, a first capacitor C1 with a second end connected with a first end of a first inductor L1, a fourth resistor R4 with a first end connected with a second end of a second resistor R2, a second capacitor C2 and a second inductor L2, a second end of the first inductor L1 is connected with a second end of a third resistor R3, the first inductor L1 and the second inductor L2 are both located inside a substrate, and the multi-stage debuggable equalizer comprises the above debuggable equalizer. The debuggable equalizer and the multi-order debuggable equalizer disclosed by the embodiment of the application realize the miniaturization and integration of the equalizer by using a mode of integrating the inductor into the substrate.

Description

Adjustable equalizer and multi-order adjustable equalizer

Technical Field

The present application relates to the field of communications technologies, and in particular, to a debuggable equalizer and a multi-stage debuggable equalizer.

Background

When designing an ultra-wideband T/R component, the problem of amplitude flatness in a wide frequency band is solved. Due to uneven amplifier gain of the ultra-wideband T/R component and loss difference in the signal transmission process, certain fluctuation exists in the in-band gain in the working frequency band.

In radio frequency and microwave circuits, an air core inductor and a magnetic ring inductor are mainly used as resonance or matching elements, and at a lower frequency (generally below 150 MHz), a magnetic ring inductor is generally used because the required inductance value is larger. At higher frequencies (above 150 MHz), the required inductance is small and air core inductors are usually used.

After the process assembly of the hollow inductor and the magnetic ring inductor is completed, the inductance value is adjusted by adjusting the turn-to-turn distance of the coil, and finally the required product performance is obtained. And then the glue is dispensed and cured. The inductance values of the hollow inductor and the magnetic ring inductor are inaccurate, the discreteness is large, the repeated debugging is needed, and the technical processes of assembling, curing and the like are also complex.

Disclosure of Invention

The embodiment of the application provides a debuggable equalizer and a multi-order debuggable equalizer, and the miniaturization and integration of the equalizer are realized by using a mode of integrating an inductor into a substrate.

The above object of the embodiments of the present application is achieved by the following technical solutions:

in a first aspect, an embodiment of the present application provides a debuggable equalizer, including:

the circuit includes:

a first resistor R1;

a second resistor R2, a first end of which is connected with a second end of the first resistor R1;

a first end of the third resistor R3 is connected with the second end of the second resistor R2, and a second end of the third resistor R3 is connected with the second end of the first resistor R1;

a first end of the first capacitor C1 is connected to the first end of the second resistor R2, a second end of the first capacitor C1 is connected to the first end of the first inductor L1, and a second end of the first inductor L1 is connected to the second end of the third resistor R3;

a fourth resistor R4, a first end of which is connected with the second end of the second resistor R2; and

a first end of a second capacitor C2 and a second end of a second inductor L2 are both connected with a second end of a fourth resistor R4, and the second ends are both grounded;

the first inductor L1 and the second inductor L2 are both located inside the substrate.

In one possible implementation of the first aspect, the first inductor L1 and the second inductor L2 are made of a copper material.

In one possible implementation manner of the first aspect, the first capacitor C1 and the second capacitor C2 both use patch capacitors.

In one possible implementation form of the first aspect, the patch capacitor uses a high-Q patch capacitor.

In one possible implementation manner of the first aspect, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 all use patch resistors.

In a second aspect, an embodiment of the present application provides a multi-stage debuggable equalizer, including the debuggable equalizer described in the first aspect and any possible implementation manner of the first aspect, a second end of the third resistor R3 in the first debuggable equalizer is connected to a first end of the first resistor R1 in the second debuggable equalizer, a second end of the third resistor R3 in the second debuggable equalizer is connected to a first end of the first resistor R1 in the third debuggable equalizer, and so on.

Drawings

Fig. 1 is a schematic perspective view of a substrate according to an embodiment of the present disclosure.

Fig. 2 is a schematic plan view of a substrate according to an embodiment of the present disclosure.

Fig. 3 is an equivalent schematic diagram of a circuit on a substrate according to an embodiment of the present disclosure.

Fig. 4 is a circuit diagram of a multi-stage tunable equalizer according to an embodiment of the present application.

In the figure, 1, a substrate.

Detailed Description

The technical solution of the present application is further described in detail below with reference to the accompanying drawings.

Referring to fig. 1 to fig. 3, a tunable equalizer disclosed in an embodiment of the present application includes a substrate 1 and a circuit disposed on the substrate 1, in which an electrical component of the circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a first inductor L1, and a second inductor L2, specifically, the circuit includes four parts, that is, three parallel sub-circuits and a grounded sub-circuit, the first sub-circuit includes the second resistor R2 and the third resistor R3, a first end of the second resistor R2 serves as an input end, a second end of the second resistor R2 is connected to a first end of the third resistor R3, and a second end of the third resistor R3 serves as an output end.

The second sub-circuit comprises a first resistor R1, a first terminal of the first resistor R1 is connected to a first terminal of a second resistor R2, and a second terminal is connected to a second terminal of a third resistor R3.

The third sub-circuit comprises a first capacitor C1 and a first inductor L1, wherein a first end of the first capacitor C1 is connected with a first end of a second resistor R2, a second end of the first capacitor C1 is connected with a first end of a first inductor L1, and a second end of the first inductor L1 is connected with a second end of a third resistor R3.

The third branch circuit is composed of a fourth resistor R4, a second capacitor C2 and a second inductor L2, the first end of the fourth resistor R4 is connected with the second end of the second resistor R2, the first ends of the second capacitor C2 and the second inductor L2 are both connected with the second end of the fourth resistor R4, and the second ends of the second capacitor C2 and the second inductor L2 are both grounded.

The first inductor L1 and the second inductor L2 in the above description are both inductors integrated in the substrate 1, or are strip line patterns arranged at a predetermined interval inside the substrate 1.

The first inductor L1 and the second inductor L2 are made of copper, for example, by etching or by directly patterning a circuit on the substrate 1.

C1 and L1 form series resonance, C2 and L2 form parallel resonance, the resonance frequency of the resonator is adjusted, and R1, R2, R3 and R4 adjust the size of the balance weight of the equalizer.

In summary, the debuggable equalizer provided in the embodiment of the present application realizes miniaturization and integration of the equalizer by integrating the inductors (the first inductor L1 and the second inductor L2) into the substrate 1, and integrates all the electrical components on the substrate 1, so that the volume of the equalizer can be rapidly reduced, and the degree of integration can be rapidly improved, for example, in various use environments, the circuit on the substrate 1 can participate in the processing process only by connecting the substrate 1 into the circuit, which is obvious, and the debuggable equalizer provided in the embodiment of the present application is more convenient to use.

As a specific embodiment of the debuggable equalizer provided by the application, the first capacitor C1 and the second capacitor C2 both use patch capacitors, and the use of patch capacitors means that the capacitance holding capacity of the first capacitor C1 and the second capacitor C2 is adjustable, that is, the standing wave and frequency of the equalizer can be adjusted by external capacitors.

Further, the patch capacitor uses a high-Q patch capacitor.

As a specific embodiment of the debuggable equalizer provided by the application, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 all use chip resistors, and using the chip resistors means that the resistance values of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are adjustable, that is, the amount of equalization of the equalizer can be adjusted by an external resistor.

When the patch capacitor and the patch resistor are used, each processing parameter of the circuit can be adjusted according to actual situations, for example, if the capacitor (the first capacitor C1 and the second capacitor C2) and the resistor (the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4) are all fixed on the substrate 1, that is, each processing parameter of the circuit on the substrate 1 is fixed, and needs to be redesigned for different use scenarios.

After having used paster electric capacity and chip resistor, to the use scene of difference, only need to change the paster electric capacity that suitably holds the electric field ability and the chip resistor of different resistances, just can satisfy the user demand.

Referring to fig. 4, an embodiment of the present application further discloses a multi-stage debuggable equalizer, where the multi-stage debuggable equalizer is formed by serially connecting a plurality of the debuggable equalizers described in the above, specifically, a second end of the second resistor R2 in the first debuggable equalizer is connected to a first end of the first resistor R1 in the second debuggable equalizer, a second end of the second resistor R2 in the second debuggable equalizer is connected to a first end of the first resistor R1 in the third debuggable equalizer, and so on.

The embodiments of the present invention are preferred embodiments of the present application, and the scope of protection of the present application is not limited by the embodiments, so: all equivalent changes made according to the structure, shape and principle of the present application shall be covered by the protection scope of the present application.

Claims

1. A debuggable equalizer, comprising:

a substrate (1) and a circuit provided on the substrate (1), the circuit comprising:

a first resistor R1;

a second resistor R2, a first end of which is connected with a first end of the first resistor R1;

a third resistor R3, the first end of which is connected with the second end of the second resistor R2, and the second end of which is connected with the second end of the first resistor R1;

the first inductor L1 and the second inductor L2 are both located inside the substrate (1).

2. The debuggable equalizer of claim 1, wherein the first inductor L1 and the second inductor L2 are fabricated using a copper material.

3. The debuggable equalizer of claim 1, wherein the first capacitor C1 and the second capacitor C2 both use patch capacitors.

4. The debuggable equalizer of claim 3, wherein the patch capacitors use high Q patch capacitors.

5. The debuggable equalizer of claim 1, 3 or 4, wherein the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 all use patch resistors.

6. A multi-stage tuneable equalizer comprising a plurality of tuneable equalizers according to any of claims 1 to 5, wherein the second terminal of the third resistor R3 in the first tuneable equalizer is connected to the first terminal of the first resistor R1 in the second tuneable equalizer, the second terminal of the third resistor R3 in the second tuneable equalizer is connected to the first terminal of the first resistor R1 in the third tuneable equalizer, and so on.