CN216749877U

CN216749877U - Semiconductor device with a plurality of transistors

Info

Publication number: CN216749877U
Application number: CN202220428065.6U
Authority: CN
Inventors: 贾钊; 窦志珍; 兰晓雯; 杨琦; 胡加辉; 金从龙; 顾伟
Original assignee: Jiangxi Zhao Chi Semiconductor Co Ltd
Current assignee: Jiangxi Zhao Chi Semiconductor Co Ltd
Priority date: 2022-02-24
Filing date: 2022-02-24
Publication date: 2022-06-14
Anticipated expiration: 2032-02-24

Abstract

The utility model provides a semiconductor device which comprises a first wafer, a second wafer and a bonding layer for bonding the first wafer and the second wafer, wherein the bonding layer comprises a first Si thin layer arranged on the first wafer and a second Si thin layer arranged on the second wafer, and the first Si thin layer and the second Si thin layer are bonded with each other through Si atomic bonds. According to the utility model, the Si thin layer is used as the bonding layer, and the Si thin layer is extremely thin, so that the light can be transmitted without influence on the light; and the Si thin layers can be bonded through the bond energy, so that the effective bonding success rate is higher than that of the traditional bonding process by 20% or more, and the double requirements of high light transmission and high bonding success rate can be met simultaneously.

Description

Semiconductor device with a plurality of transistors

Technical Field

The utility model relates to the technical field of semiconductors, in particular to a semiconductor device.

Background

In LED manufacturing, wafer bonding technology is a very critical process in current wafer manufacturing, and provides possibility for replacing substrates, and the wafer bonding technologies mainly adopted at present are metal bonding and surface activation bonding respectively.

The success rate of effective bonding of metal bonding is as high as 95% or more, but the metal bonding mostly adopts Au as a plating layer, so that the cost is higher and light cannot be transmitted; the surface activation bonding is light permeable, but the effective bonding success rate is 60-70% on average, and the bonding success rate is low. Therefore, the wafer bonding technology used at present is difficult to satisfy the dual requirements of high light transmittance and high bonding success rate.

SUMMERY OF THE UTILITY MODEL

Based on this, the present invention aims to provide a semiconductor device, which aims to solve the technical problem that the existing wafer bonding technology is difficult to simultaneously satisfy the dual requirements of high light transmission and high bonding success rate.

According to the embodiment of the utility model, the semiconductor device comprises a first wafer, a second wafer and a bonding layer for bonding the first wafer and the second wafer, wherein the bonding layer comprises a first Si thin layer arranged on the first wafer and a second Si thin layer arranged on the second wafer, and the first Si thin layer and the second Si thin layer are bonded with each other through Si atomic bonds.

Preferably, the first and second thin Si layers have a thickness of 5A to 10A.

Preferably, SiO is arranged between the first Si thin layer and the first wafer₂Layer of said SiO₂A first Si thin layer formed on the first wafer and the SiO thin layer₂On the layer.

Preferably, the outermost layer of the first wafer is a GaP layer, and the SiO layer₂The layer is formed on the GaP layer.

Preferably, the GaP layer is a roughened GaP layer.

Preferably, the first wafer is an epitaxial wafer or a chip, and the first wafer is a substrate.

According to a bonding process of a semiconductor device among embodiments of the present invention, a first wafer and a second wafer for bonding are provided;

sputtering a first thin layer of Si on the first wafer and a second thin layer of Si on the second wafer;

performing ion bombardment on the first wafer and the second wafer to form Si atomic bonds on bonding surfaces of the first Si thin layer and the second Si thin layer;

and bonding the first wafer and the second wafer in a bonding machine to bond Si atomic bonds between the first Si thin layer and the second Si thin layer.

Preferably, the step of sputtering a first thin Si layer on the first wafer comprises:

coarsening the GaP layer on the outermost layer of the first wafer;

growing SiO on the surface of the coarsened GaP layer₂Layer of and on said SiO₂Polishing and organic cleaning the layer;

SiO after polishing and organic cleaning₂A first thin Si layer is sputtered on the surface of the layer using a sputtering station.

Preferably, the step of sputtering a second thin layer of Si on the second wafer comprises:

and sputtering a second Si thin layer on the surface of the second wafer by using a sputtering machine.

Preferably, the bonding of the first wafer and the second wafer is low-temperature high-pressure bonding, the bonding temperature is 300-.

Compared with the prior art: by using the Si thin layer as the bonding layer, the Si thin layer can transmit light due to the extremely thin thickness and has no influence on the light transmission; and the Si thin layers can be bonded through the bond energy, so that the effective bonding success rate is higher than that of the traditional bonding process by 20% or more, and the double requirements of high light transmission and high bonding success rate can be met simultaneously.

Drawings

Fig. 1 is a schematic structural diagram of a semiconductor device according to a first embodiment of the present invention;

fig. 2 is a flowchart of a bonding process of a semiconductor device according to a second embodiment of the present invention;

fig. 3 is a schematic structural diagram of steps of a bonding process of a semiconductor device according to a second embodiment of the present invention.

The following detailed description will further illustrate the utility model in conjunction with the above-described figures.

Detailed Description

To facilitate an understanding of the utility model, the utility model will now be described more fully hereinafter with reference to the accompanying drawings. Several embodiments of the utility model are presented in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the utility model herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Example one

Referring to fig. 1, a semiconductor device according to a first embodiment of the present invention is shown, which includes a first wafer 1, a second wafer 2, and a bonding layer 3 for bonding the first wafer 1 and the second wafer 2, where the bonding layer 3 includes a first Si thin layer 31 disposed on the first wafer 1 and a second Si thin layer 32 disposed on the second wafer 2, and the first Si thin layer 31 and the second Si thin layer 32 are bonded to each other through Si atomic bonds, that is, in this embodiment, the Si thin layer is used as the bonding layer 3, since the Si thin layer is very thin, light can be transmitted through the Si thin layer, no influence is caused on light transmission, and the Si thin layers can be bonded through bonds, so that an effective bonding success rate is 20% or more higher than that of a conventional bonding process. In addition, the first wafer 1 may be an epitaxial wafer or a chip, the second wafer 2 may be a substrate, and the substrate may specifically be a sapphire substrate, that is, the method of bonding a Si thin layer proposed in this embodiment may be suitable for bonding between various epitaxial wafers, various chips, and various substrates, and has good compatibility.

Preferably, the thicknesses of the first Si thin layer 31 and the second Si thin layer 32 are 5A to 10A, and the thicknesses of the first Si thin layer 31 and the second Si thin layer 32 may be the same, for example, both are 8A, or the thicknesses of the first Si thin layer 31 and the second Si thin layer 32 may be different, for example, the thickness of the first Si thin layer 31 is 6A, and the thickness of the first Si thin layer 31 is 9A.

In other alternative embodiments, SiO may also be provided between the first Si thin layer 31 and the first wafer 1₂ Layer 4, wherein the outermost layer of the first wafer 1 is GaP layer 5, SiO₂The layer 4 is formed on the GaP layer 5, and the first Si thin layer 31 is formed on the SiO thin layer₂On the layer 4. Wherein, SiO₂ Layer 4 is a bonding layer, plays a bonding role, can grow by evaporation, and has a growth temperature of 200 ℃360 ℃; in addition, for better subsequent epitaxial growth, the GaP layer 5 is embodied as a roughened GaP layer, i.e. SiO is epitaxially grown on the roughened GaP layer 5₂And (4) a layer.

Example two

Referring to fig. 2-3, a bonding process of a semiconductor device according to a second embodiment of the present invention is shown, which can be used for bonding the semiconductor device according to the above embodiment, and by way of example and not limitation, the present embodiment will be described by taking a first wafer as an epitaxial wafer and a second wafer as a sapphire substrate, where the bonding process specifically includes:

step S01, providing an epitaxial wafer and a sapphire substrate for bonding;

step S02, coarsening the GaP layer on the outermost layer of the first wafer;

and the GaP layer can effectively improve the brightness of the chip after being coarsened. However, it should be noted that in some alternative embodiments, the GaP layer may not be roughened.

Step S03, growing SiO on the surface of the coarsened GaP layer₂Layer of and on said SiO₂Polishing and organic cleaning the layer;

step S04 SiO after polishing and organic cleaning₂Sputtering a first Si thin layer on the surface of the layer by using a sputtering machine, and sputtering a second Si thin layer on the surface of the sapphire substrate by using the sputtering machine;

in specific implementation, a sputtering machine station may be used to perform sputtering growth of the Si thin layer, and the sputtering parameter may be, for example, a vacuum degree of 2 × 10^-4Pa～4*10^-4Pa, temperature of 200-460 deg.C, sputtering rate of 0.01-0.03 nm/s.

Step S05, carrying out ion bombardment on the epitaxial wafer and the sapphire substrate to form Si atomic bonds on the bonding surfaces of the first Si thin layer and the second Si thin layer;

and step S06, bonding the epitaxial wafer and the sapphire substrate into a bonding machine for low-temperature high-pressure bonding, so that Si atomic bonds between the first Si thin layer and the second Si thin layer are bonded with each other.

Specifically, the bonding temperature of the epitaxial wafer and the sapphire substrate is 300-400 ℃, preferably 360 ℃, the bonding pressure is more than 15000kg, and the bonding time is 80-100min, preferably 90 min.

In summary, in the semiconductor device and the bonding process thereof in the present embodiment, by using the Si thin layer as the bonding layer 3, the Si thin layer is very thin and therefore light can be transmitted, and has no influence on light transmission; the Si thin layers can be bonded through the bond energy, the effective bonding area can reach more than 90%, the effective bonding success rate is higher than that of the traditional bonding process by 20% or more, the double requirements of high light transmission and high bonding success rate can be met, and more possibilities are provided for the subsequent chip process which can be performed only through bonding. In addition, this method is not limited to the bonding of a general epitaxial wafer and sapphire, and various substrates of various chips can be bonded to each other by this method as long as sputtering of a thin layer Si is possible.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A semiconductor device is characterized by comprising a first wafer, a second wafer and a bonding layer for bonding the first wafer and the second wafer, wherein the bonding layer comprises a first Si thin layer arranged on the first wafer and a second Si thin layer arranged on the second wafer, and the first Si thin layer and the second Si thin layer are bonded with each other through Si atomic bonds.

2. The semiconductor device according to claim 1, wherein the first thin Si layer and the second thin Si layer have a thickness of 5A to 10A.

3. The semiconductor device of claim 1, wherein SiO is disposed between the first Si thin layer and the first wafer₂Layer of said SiO₂A first Si thin layer formed on the first wafer and the SiO thin layer₂On the layer.

4. The semiconductor device of claim 3, wherein the outermost layer of the first wafer is a GaP layer, and the SiO is₂The layer is formed on the GaP layer.

5. The semiconductor device of claim 4, wherein the GaP layer is a roughened GaP layer.

6. The semiconductor device according to any one of claims 1 to 5, wherein the first wafer is an epitaxial wafer or a chip.

7. The semiconductor device according to any one of claims 1 to 5, wherein the first wafer is a substrate.