CN216749321U - Dead pixel self-detection device and chip - Google Patents

Abstract

The utility model provides a dead pixel self-detection device and a chip of a static random access memory. The dead pixel self-detection device includes: the controller is used for realizing read-write control on the static random access memory; a self-detector, comprising: the monitoring unit is used for monitoring the working state of the static random access memory; the notification unit is connected with the monitoring unit and used for sending the storage address to be detected and the standard data to the controller under the condition that the static random access memory is in an idle state, and the controller reads and writes data in the storage unit corresponding to the storage address to be detected according to the storage address to be detected; and the detection unit is used for judging whether the read data read from the storage address to be detected is consistent with the standard data or not so as to judge whether the storage unit corresponding to the storage address to be detected has a dead pixel or not. The technical scheme can realize the self-detection of the dead pixel of each storage unit in the static random access memory in the chip, and improve the working reliability of the chip carrying the static random access memory.

Description

Dead pixel self-detection device and chip

Technical Field

The utility model relates to the technical field of chips, and particularly discloses a dead pixel self-detection device of a static random access memory and a chip.

Background

Static Random Access Memory (SRAM) is often required for chip design. An sram is a type of random access memory in which stored data can be constantly maintained as long as power is maintained. Because the static random access memory can not carry out DFT (design For test) test, the DFT test means that various hardware logics For improving the testability (including controllability and observability) of the chip are inserted in the stage of the original design of the chip, and test vectors are generated through the logics so as to achieve the purpose of testing large-scale chips. In the prior art, joint detection and correction are often performed in a manner of combining manual work and software for error detection of the sram, and the degree of automation of dead pixel detection and correction of the sram needs to be improved.

Meanwhile, in the prior art, error detection is usually performed only once on the sram when the chip leaves the factory, which results in failure to perform real-time error detection on the sram during the use of the chip, and thus causes a problem in the operational reliability of the chip loaded with the sram.

Disclosure of Invention

According to the problems that the detection and correction efficiency of the static random access memory is low and the real-time detection of the whole life process cannot be realized in the prior art, the utility model provides a dead pixel self-detection device and a chip of the static random access memory.

In a first aspect of the present application, there is provided a self-test device for a dead pixel of an sram, including:

the controller is connected with the static random access memory through a bus and is used for realizing the read-write control of the static random access memory;

self-test ware, self-test ware is connected with controller and SRAM respectively, and self-test ware includes:

the monitoring unit is used for continuously monitoring the working state of the static random access memory, and the working state comprises an idle state and a non-idle state;

the notification unit is connected with the monitoring unit and used for sending the storage address to be detected and the standard data to the controller under the condition that the static random access memory is in an idle state;

the controller writes the standard data into the storage address to be detected according to the received storage address to be detected and the standard data, and reads the data from the storage address to be detected;

the detection unit is used for judging whether the read data read from the memory address to be detected is consistent with the standard data: under the condition that the read data is consistent with the standard data, judging that no dead pixel exists in the storage unit corresponding to the storage address to be detected; and under the condition that the read data is inconsistent with the standard data, judging that a storage unit corresponding to the storage address to be detected has a dead pixel.

In one possible implementation of the first aspect described above, the bus comprises a control bus and a data bus;

the self-detector is connected with the static random access memory in a mode of respectively accessing the control bus and the data bus.

In one possible implementation of the first aspect, the self-detector further includes:

and the counter is connected with the self-detector and used for taking the memory address to be detected as a dead pixel address and recording the number of the dead pixel addresses under the condition that the memory unit corresponding to the memory address to be detected has dead pixels according to the judgment result.

In one possible implementation of the first aspect, the self-detector further comprises:

and the alarm is connected with the counter and used for outputting corresponding alarm information under the condition that the number of the dead pixel addresses is greater than a preset threshold value.

In one possible implementation of the first aspect, the alarm includes a first sub-memory and a first comparator;

the first comparator is used for comparing the number of the current dead pixel addresses with a preset threshold value;

the first sub-memory is used for storing alarm information.

In one possible implementation of the first aspect, the monitoring unit includes a multiplexer;

the access end of the multiplexer is connected with the bus and is used for continuously monitoring the generation condition of the enabling signal of the controller so as to continuously monitor the real-time working state of the static random access memory.

In a possible implementation of the first aspect described above, the notification unit comprises a second sub-memory and an address accumulator;

the second sub-memory is used for storing standard data;

the address accumulator is used for determining the storage address to be detected corresponding to the current detection, and executing the address accumulation operation under the condition that the current detection is completed so as to determine the storage address to be detected corresponding to the next detection.

In one possible implementation of the first aspect, the detection unit includes a second comparator;

the second comparator is connected with the bus and used for comparing the read data with the standard data.

In a possible implementation of the first aspect, the notification unit is further connected to the second comparator; and the notification unit takes the memory address to be detected as a dead pixel address and sends the dead pixel address to the controller under the condition that the memory unit corresponding to the memory address to be detected has a dead pixel according to the result of the second comparator.

In one possible implementation of the first aspect described above, the controller includes a third sub-memory for storing the dead pixel address.

A second aspect of the present application provides a chip, which is loaded with at least one static random access memory through the dead pixel self-detection apparatus provided in the first aspect of the present application.

Compared with the prior art, the utility model has the following beneficial effects:

through the technical scheme provided by the application, the self-detection of the dead pixel of each storage unit in the static random access memory in the chip can be realized: under the condition that the static random access memory is in an idle state, the controller controls the storage unit in the static random access memory to perform normal data reading and writing to detect the dead pixel, so that the dead pixel can be recorded in time when the dead pixel appears in the static random access memory, and alarm information can be generated under the condition that the number of the dead pixels is excessive, thereby realizing the working reliability of a chip carrying the static random access memory and having popularization value.

Drawings

Other features, objects and advantages of the utility model will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

fig. 1 is a schematic structural diagram illustrating a self-bad-point detection apparatus of an sram according to an embodiment of the present application;

FIG. 2 is a flow chart illustrating how the self-detection apparatus for dead pixel can detect dead pixel in SRAM according to an embodiment of the present application;

FIG. 3 is a schematic diagram illustrating another flow chart of how to implement a dead-cell detection for an SRAM according to an embodiment of the present application;

FIG. 4 is a diagram illustrating a state change of an SRAM performing self-detection according to an embodiment of the present application.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the utility model, but are not intended to limit the utility model in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the utility model. All falling within the scope of the present invention.

The term "include" and variations thereof as used herein is meant to be inclusive in an open-ended manner, i.e., "including but not limited to". Unless specifically stated otherwise, the term "or" means "and/or". The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below.

In order to solve the problems that a static random access memory lacks an efficient dead pixel detection method and cannot realize real-time detection of a full life process in the prior art, the application provides a dead pixel self-detection device and a chip of the static random access memory. The dead pixel self-detection device can realize the dead pixel self-detection of each storage unit in the static random access memory in the chip, and further improve the working reliability of the chip with the static random access memory.

Specifically, fig. 1 shows a schematic structural diagram of a self-bad-point detection apparatus of an sram according to some embodiments of the present application, which specifically includes:

an sram 300, a controller 310, and a self-detector 320. The controller 310 is connected to the sram 300 through a bus 330, and is configured to implement read/write control on the sram 300; the self-detector 320 is connected to the controller 310 and the sram 300, respectively.

As shown in FIG. 1, the bus 330 includes a data bus 330a and a control bus 330b, wherein the control bus 330b is transmitted from the controller 310 to the SRAM 300 in a single direction, and the data bus 330a is transmitted between the controller 310 and the SRAM 300 in a double direction to achieve the interaction of read and write data.

Specifically, as shown in fig. 1, the self-detector 320 may include:

the monitoring unit 321 is configured to continuously monitor an operating state of the sram. The working state of the static random access memory can comprise an idle state and a non-idle state, and the non-idle state can further comprise a reading state and a writing state.

Specifically, the monitoring unit 321 may be implemented by a multiplexer, an enable end of the multiplexer accesses the bus, detects an enable signal generated by the controller, and if the controller enable signal is not detected, the sram is currently in an idle state, and may perform a relevant procedure of dead pixel self-detection. Of course, this can be achieved in other ways that are common in the art. When the sram 100 is in a normal operating state, the controller 110 needs to perform continuous read/write control on the sram 100, and generates a corresponding enable signal. Therefore, in the case where the controller 110 enable signal is not detected, which indicates that the sram 100 is currently in an idle state, the self-bad-cell detector may start to operate. Of course, the monitoring and acquisition of the idle state of the sram may be implemented by other means commonly used in the art by those skilled in the art.

The notification unit 322 is connected to the monitoring unit 321, and is configured to communicate with the controller 310 at least when the sram is in an idle state, and send the memory address to be tested and the standard data to the controller. And the controller writes the standard data into the memory address to be tested according to the received memory address to be tested and the standard data, and reads the data from the memory address to be tested.

Specifically, the notification unit 322 may include an address accumulator and a memory, wherein the address accumulator is used to determine the currently detected memory address to be detected, and perform address accumulation to determine the next memory address to be detected to be provided to the controller 310 when the current detection is completed; the memory is used for storing standard data for detection. In an example, the notification unit includes a second sub-memory and an address accumulator. The second sub-memory is used for storing standard data for self-detection of the dead pixel; the address accumulator may be coupled to the multiplexer, and configured to determine a memory address to be tested corresponding to a current test, and perform an address accumulation operation when the current test is completed, so as to determine a memory address to be tested corresponding to a next test.

The controller 310 writes the standard data into the memory address to be tested according to the received memory address to be tested and the standard data, and reads data from the memory address to be tested. Both standard data writes and data reads are performed via bus 330 to interact with the sram.

A detection unit 323 for acquiring read data via the bus 330 and comparing with written standard data: under the condition that the read data is consistent with the standard data, judging that no dead pixel exists in the storage unit corresponding to the storage address to be detected; and under the condition that the read data is inconsistent with the standard data, judging that a storage unit corresponding to the storage address to be detected has a dead pixel.

Specifically, the detection unit 323 may be implemented by a comparator, and the corresponding determination result is obtained by comparing the read data acquired from the bus 330 with the standard data. In a specific example, the detection unit comprises a second comparator, wherein the second comparator is connected with the bus for comparing the read data with the standard data. Specifically, one input of the second comparator can access the bus 130 to obtain the read data and compare it with the preset standard data for consistency.

Further, in the above embodiment, the self-detector 320 may also feed back the information related to the dead pixel address to the controller 310 when the memory cell corresponding to the memory address to be detected has a dead pixel. Specifically, in some embodiments of the present application, the detection unit 323 may be connected to the notification unit 322, and send the information of the address of the dead pixel to the controller 310 through the notification unit 322. If the comparator of the detection unit is further coupled to the notification unit, the notification unit may take the memory address to be detected as a dead pixel address and send the dead pixel address to the controller, in case that the memory unit corresponding to the memory address to be detected has a dead pixel according to the determination result generated by the determination comparator. The sending of the address of the dead pixel may be implemented by the comparator and the address accumulator, or of course, the notification of the address of the dead pixel judged by the detecting unit to the controller may also be implemented by other common means in the art.

As shown in fig. 3, the controller 310 may further include a recording unit 311 for recording the defective pixel address. Specifically, the recording unit 311 may be implemented by a memory. In a specific example, the recording unit 311 includes a third sub-memory for storing a dead pixel address.

It is understood that in some implementations of the above embodiments, the self-detector 320 can be implemented in the form of a detection circuit: the detection circuit is disposed between the SRAM 300 and the bus 330 of the controller 310, and can continuously detect the enable signal through the selector element; when the static random access memory is detected to be in an idle state currently, the to-be-detected storage address and the standard data are selected to be sent to the controller 310 for read-write operation through the address accumulator element and the memory element; and then, by means of the comparator element, consistency comparison is performed according to the read data and the write data intercepted from the data bus 330b, so as to realize self-detection of a bad point of a memory cell corresponding to a certain memory address to be detected.

Further, in the above embodiments, the self-detector may further include at least one of the following devices:

the counter is used for taking the memory address to be detected as a dead pixel address and recording the number of the dead pixel addresses under the condition that the memory unit corresponding to the memory address to be detected has dead pixels; and the alarm is used for generating corresponding alarm information under the condition that the number of the dead pixel addresses is greater than a preset threshold value.

Specifically, the counting unit may be connected to the detecting unit, and may be implemented by a counter, for example, the counter is connected to a comparator of the detecting unit, and when a situation that a storage unit corresponding to a new to-be-detected storage address has a dead pixel occurs, the counter adds one to accumulate on the basis of original data, so as to update the number of the dead pixel addresses in real time.

In addition, the alarm unit can be connected with the counting unit and can be realized through the comparator and the memory, and through the comparison between the current number of the dead pixel addresses and the preset threshold value, under the condition that the current number of the dead pixel addresses exceeds the preset threshold value, the preset alarm information is extracted from the memory and informed to the current development integration environment, so that the fault information of the static random access memory can be fed back in time. In a specific example, the alarm unit includes a first sub-memory and a first comparator, where the first comparator may be connected to the counter, the first comparator is configured to implement comparison between the number of current dead pixel addresses and a preset threshold, and the first sub-memory is configured to store the alarm information. The first comparator can compare the current real-time number of the dead pixel addresses of the counter with a preset threshold value, and under the condition that the current number of the dead pixel addresses exceeds the preset threshold value, pre-stored warning information is extracted from the first sub-memory and informed to the current development integration environment, so that the fault information of the static random access memory can be fed back in time.

Through the detection circuit externally connected with the controller 310 and the static random access memory 300, on one hand, the dead pixel automatic detection in the whole life cycle can be effectively realized, on the other hand, the control logic of the controller 310 does not need to be adjusted or the comparison and judgment logic is additionally added in the controller 310, and the detection circuit is easy to realize landing and is widely popularized.

Now, a schematic flow chart of how the self-detection device for dead pixel detects a dead pixel of a static random access memory is provided to further describe the functional implementation of the self-detection device for dead pixel according to the present application, as shown in fig. 2, the method specifically includes:

step 100: whether the static random access memory is in an idle state is judged. If yes, go to step 101; if not, the current static random access memory is in a working state, the working requirement of the static random access memory needs to be met preferentially, the static random access memory in the current state is not suitable for performing dead pixel detection, and in this case, the step 100 can be returned to continue to execute the next idle state judgment.

It is understood that, in some embodiments of the present application, the self-defect-detecting apparatus may be continuously executed for the above step 100, or may be adjusted according to the actual working condition of the chip on which the sram is mounted, for example, by periodically executing the step 100 by setting the interval time for initiating the judgment.

For example, if the single operation execution time of the chip with the sram is 2 seconds on average, the self-defect detection apparatus may be configured to perform the determination as in step 100 once for the operating state of the sram every 2 seconds, so as to perform the self-detection on the possible memory address defect as soon as possible without affecting the normal operation of the sram.

Step 101: and writing the standard data into a memory address to be tested of the static random access memory. It can be understood that, in the case that the sram is in an idle state, the sram may be subjected to a dead-point test by a read-write test. The static random access memory comprises a memory cell array composed of a plurality of memory cells, each memory cell in the memory array shares electrical connection with other memory cells on rows and columns, wherein a connection line representing data flowing into and out of the memory cell in a horizontal direction is called a "word line", a connection line representing data flowing into and out of the memory cell in a vertical direction is called a "bit line", a user can select a specific word line and bit line by inputting an address, a selected memory cell is at an intersection of the word line and the bit line, and each memory cell is uniquely selected according to the method. That is, each memory address to be tested corresponds to a specific memory cell in the sram, and effective testing of the read-write capability of the memory cell can be achieved through data read-write testing using the memory address to be tested.

Step 102: and reading data from the memory address to be tested, and judging whether the read data is consistent with the standard data. If the read data is consistent with the standard data, it indicates that the memory address to be tested can perform normal read-write operation, and there is no bad point problem, and then go to step 104; if the read data is not consistent with the standard data, it indicates that the write data and the read data for the memory address to be tested cannot be consistent due to various failure reasons, and normal read-write operation cannot be performed, which results in a defect, and then the process goes to step 103.

Step 103: and judging that the storage unit corresponding to the storage address to be detected has a dead pixel.

Step 104: and judging that no dead pixel exists in the storage unit corresponding to the storage address to be detected.

In the above embodiments, steps 100 to 104 implement a real-time self-test process for a single memory address to be tested and a corresponding memory cell thereof, but considering that there is more than one memory address and memory cell in the sram, it is necessary to implement a comprehensive self-test for the sram by performing a traversal self-test for each memory address and each memory cell, so in some embodiments of the present application, after the above steps 100 to 104 are completed, a new memory address to be tested may be reselected to repeatedly perform steps 100 to 104, so as to implement a comprehensive self-test for the sram. The specific process steps related to the selection of the memory address to be tested will be described later.

It can be seen that, in the above steps 100 to 104, the single memory address to be tested is subjected to the bad point detection through the read/write test. In order to improve the detection accuracy as much as possible while ensuring the dead pixel detection efficiency, fig. 3 shows a schematic flow chart of another dead pixel self-detection apparatus for performing dead pixel detection on the sram according to some embodiments of the present application.

Step 200: and writing the write-once data into the memory address to be tested of the static random access memory under the condition that the static random access memory is in an idle state.

Step 201: and reading data once from the storage address to be tested, and judging whether the read data once is consistent with the write data once. If the once read data is inconsistent with the once written data, it is also indicated that the memory cell corresponding to the memory address to be tested cannot perform normal read-write operation, and there is a bad point problem, and then the process goes to step 204; if the once read data is consistent with the once written data, it indicates that the memory cell corresponding to the memory address to be tested remains normal in the current data reading and writing process, and then the process goes to step 202.

Step 202: and writing the secondary write data into the memory address to be tested of the static random access memory. It can be understood that, in order to ensure the test diversity of the memory cells corresponding to the memory address to be tested, the requirement for writing data twice is different from that for writing data once.

Step 203: and reading the secondary data from the storage address to be detected, and judging whether the secondary read data is consistent with the secondary write data. If the secondary read data is inconsistent with the secondary write data, it is also indicated that the memory cell corresponding to the memory address to be tested cannot perform normal read-write operation, and there is a bad point problem, and then the process goes to step 204: if the secondary read data is consistent with the secondary write data, it indicates that the memory cell corresponding to the memory address to be tested performs normal read/write operations twice, and then the process goes to step 205.

Step 204: and judging that the storage unit corresponding to the storage address to be detected has a dead pixel.

Step 205: and judging that no dead pixel exists in the storage unit corresponding to the storage address to be detected.

It can be understood that there is a certain test contingency in performing one independent read-write test on the memory address to be tested by using the standard data, and the passing of the single read-write test cannot completely ensure that the memory unit corresponding to the memory address to be tested does not have a dead pixel. In order to prevent missing of dead pixels in the static random access memory and improve accuracy of dead pixel self-detection, in the above embodiment, a dead pixel self-detection mode for the storage unit can be optimized by continuously reading and writing different data twice, when read and write data are inconsistent in any one read and write process, it can be judged that a dead pixel exists in the storage unit corresponding to the current storage address to be detected, and normal read and write operation of the storage unit can be ensured only by continuously passing through two read and write verifications of different data. That is, the memory included in the notification unit 322 may store two different types of standard data corresponding to the write-once data and the write-twice data, respectively, as described in the above embodiments.

For example, in some embodiments of the present application, when a memory cell corresponding to a memory address to be tested in an sram is in an abnormal state where the memory cell is always at a high level, the write standard data is "1", at this time, data reading is performed on the memory cell, and "1" representing the high level can be read, so that it is displayed that there is no bad point in the memory cell corresponding to the memory address to be tested; only when the standard data is written again to be '0', the data reading is carried out on the storage unit again at this time, and the read data is still '1' representing high level and is not consistent with the standard data written in twice, so that the storage unit corresponding to the storage address to be tested is proved to have bad spots, and the bad spots are easy to be missed due to the success of one-time read-write test.

Further, in other embodiments of the present application, the write-once data and the write-twice data may also be dynamically generated or dynamically changed, so as to ensure randomness in the bad point test process of the memory cell.

In some embodiments of the present application, a plurality of spare memory addresses are provided in the sram. It can be understood that, for example, a static random access memory includes 100 physical memory units for data storage, and when the static random access memory is packaged in a functional chip, 90 of the physical memory units are used as daily-work memory units and are assigned with one-to-one corresponding memory addresses, and the remaining 10 physical memory units are used as spare memory units and are also assigned with one-to-one corresponding spare memory addresses. When the storage unit for daily work fails in reading and writing and cannot be used, the static random access memory or the whole chip does not need to be replaced, and the standby storage unit can be directly called for replacement. The specific implementation of replacing the spare storage unit may be to map the storage address corresponding to the failed storage unit to the replaced spare storage address, and then to store the read-write data in the corresponding spare storage unit. The skilled person can select the desired implementation according to the actual needs, and the implementation is not limited herein.

In the foregoing embodiment, in the process of performing real-time self-detection by using the method provided in the foregoing embodiment, if a defect exists in the memory cell corresponding to the current memory address to be detected in step 103 or step 204, the current memory address may be replaced by a spare memory address, so as to ensure that the normal operation of the sram is not affected. For example, in the specific embodiment of the present application, the detection of the defect at step 200 to step 205 may be performed on the storage address "00101101" in the sram, and when the storage unit corresponding to the storage address "00101101" is detected to have a defect, the storage address "00101101" may be recorded by the controller of the sram. In the subsequent normal use process, when the sram receives a command requiring a read/write operation using the memory address "00101101" again, the read/write controller modifies the memory address "00101101" into a spare memory address "00101100" through internal mapping and executes a corresponding read/write operation. By the technical scheme, the static random access memory can be subjected to real-time self-detection, and meanwhile, the storage addresses with dead pixel conditions and possibly caused read-write errors can be replaced and corrected in time, so that the safety of the subsequent normal data read-write process is ensured.

It can be understood that, under the normal use condition, due to the existence of the spare memory unit and the spare memory address, when a small number of dead pixels exist in the sram, the spare memory address can be called to perform the correction and repair in a replacement manner, and the subsequent normal use of the sram is not affected. However, when the number of bad bits existing in the sram is too large, especially the number of bad bits is larger than the number of spare memory addresses, it indicates that the sram cannot achieve normal data read/write capability, and the data written in the sram cannot be effectively stored and read, and a necessary scrap program needs to be executed. Therefore, in the above embodiment, by updating the number of the dead pixel addresses in real time, the real-time operation condition of the sram can be accurately known, and when the number of the dead pixel addresses is greater than the preset threshold, the sram can not meet the normal read/write requirement and needs to be discarded or replaced in time by generating corresponding warning information.

In the above embodiments, the predetermined threshold may be equal to the number of the spare memory addresses or less than the number of the spare memory addresses. In an ideal state, the memory address corresponding to the dead pixel can be replaced by the spare memory address, and then each dead pixel can be replaced by the spare memory address under the condition that the preset threshold value is equal to the number of the spare memory addresses, so that the cache performance of the static random access memory is not influenced. However, in consideration of the problem that the mutual interference may occur between an excessive number of dead pixels and then cause abnormal read/write operations to occur in other originally normal memory cells in the subsequent normal operation, in order to further improve the reliability of the sram, the preset threshold may need to be set to be smaller than the number of spare memory addresses. Regarding the setting mode and the setting value of the preset threshold, those skilled in the art can perform autonomous setting according to actual needs, and are not limited herein.

It is understood that, in order to implement the traversal self-detection for all the memory cells in the sram, the operations of steps 100 to 104 or steps 200 to 205 described above need to be performed for the memory address corresponding to each memory cell. Therefore, in the above embodiment, with the aid of the storage address list in the sram, under the condition that the sram is in the idle state according to the list order in the storage address list, one storage address can be sequentially extracted from the storage address list as the storage address to be tested, and the operations in steps 100 to 104 or steps 200 to 205 are described above. After the step of detecting all bad points of the current storage address to be detected is completed, the current working state of the static random access memory needs to be judged once again, if the static random access memory is still in an idle state, the next storage address is continuously extracted according to the sequence in the storage address list to be used as the storage address to be detected, and the operation of the steps 100 to 104 or the steps 200 to 205 is repeated until all the storage addresses in the storage address list are traversed once.

Further, in the above embodiment, if the static random access memory obtains that the external work instruction needs to be converted into the read state or the write state after completing all the dead pixel detection steps of the current memory address to be detected, the position information of the completed memory address to be detected in the memory address list may be recorded, and when the static random access memory is in the idle state again, the next memory address is extracted as the new memory address to be detected according to the recorded position information, thereby implementing one-time traversal of all the memory addresses in the memory address list. In particular, since the step of self-detecting the bad pixel of the memory address to be detected includes at least one data write operation and at least one data read operation, in some embodiments, the static random access memory receives an external work instruction during the data write operation and the data read operation, and the data write operation or the data read operation required by the work is required to be executed. In this case, in order to ensure that the normal use of the sram is not disturbed or affected, the execution of all the dead pixel self-detection operations on the current to-be-detected address may be stopped, the work instruction is preferentially executed, and the position information of the current to-be-detected memory address in the memory address list is synchronously recorded. Because the memory address to be detected does not complete all the dead pixel self-detection operations, when the static random access memory is in an idle state again, the memory address can be extracted according to the recorded position information to carry out dead pixel self-detection operations again.

Further, in the above embodiment, considering that the sram needs to continuously operate according to actual requirements, the dead point self-detection traversal of all the memory addresses completed at a certain specific time point cannot completely reflect the real-time operating condition state of the full life cycle of the sram. In the above embodiment, the self-detection traversal of the dead pixel for all the memory addresses in the sram may be performed at a predetermined interval, for example, 1 hour or 1 day; or starting a new round of self-detection traversal of the dead pixel by circularly and repeatedly reading the storage address list after the execution of a round of complete self-detection traversal of the dead pixel is finished. Particularly, if the sram is in an idle state during a round of complete self-inspection and traversal execution of the bad point, it indicates that the sram does not execute a working instruction, and the probability of occurrence of a new bad point is low, and the cycle bad point self-inspection traversal for the memory cell may be suspended until the sram completes at least one working instruction and is in an idle state again, and at this time, the sram may have a new bad point due to a load caused by the working instruction, and may start the cycle bad point self-inspection for the memory cell again.

In some embodiments of the present application, FIG. 4 illustrates a state change diagram of an SRAM performing self-detection. Specifically, as shown in fig. 4, when the integrated development environment provided with the sram detects that the sram is in an Idle state (Idle), a self-detection process is performed starting with a preset address to be detected as a current address: firstly, writing data0 into the current address and reading the data00 of the current address, performing primary detection judgment on the current address by comparing whether the data0 and the data00 are consistent, if so, writing data1 again and reading data10, and performing secondary detection judgment on the current address by comparing whether the data1 and the data10 are consistent. If any write-in data is inconsistent with the read data, recording the current address as an error address, and updating the number of the error addresses in real time. If the number of the error addresses is larger than the preset threshold value, the current integrated development environment is directly informed that the static random access memory has errors and needs to be warned, if the number of the error addresses does not reach the preset threshold value or the two detection judgments pass, 1 is added on the basis of the current address, and the next address in the address list is detected for a new round. If the address detection for one round of completion in the SRAM is completed, the next round of address detection is turned on by the current integrated development environment.

In some embodiments of the present application, a chip is also provided. According to the chip, at least one static random access memory is built through the real-time self-detection system provided by the embodiment, the real-time dead pixel self-detection of the static random access memory can be realized, and timely correction or timely replacement warning is given out when dead pixels appear, so that the reliability of chip application is effectively improved.

In some embodiments of the present application, an electronic device is also provided. The electronic device comprises a memory and a processor, wherein the memory is used for storing a processing program, and the processor executes the processing program according to instructions. When the processor executes the processing program, the method for real-time self-detection of the sram chip in the foregoing embodiment is implemented.

Technical solutions presented herein relate to methods, apparatuses, systems, chips, electronic devices, computer-readable storage media, and/or computer program products. The computer program product may include computer-readable program instructions for performing various aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a Digital Versatile Disk (DVD), a memory stick, a floppy disk, a mechanical coding device, a raised structure in a punch card or recess, for example, having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.

The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.

Computer program instructions for carrying out operations of the present disclosure may be assembler instructions, Instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry that can execute the computer-readable program instructions implements aspects of the present disclosure by utilizing the state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (11)

1. A self-test device for bad point is applied to static random access memory, which is characterized in that it includes:

the controller is connected with the static random access memory through a bus and is used for realizing the read-write control of the static random access memory;

a self-detector connected to the controller and the SRAM, respectively, the self-detector comprising:

the monitoring unit is used for continuously monitoring the working state of the static random access memory, and the working state comprises an idle state and a non-idle state;

the notification unit is connected with the monitoring unit and used for sending the storage address to be detected and the standard data to the controller under the condition that the static random access memory is in an idle state;

the controller writes the standard data into the memory address to be tested according to the received memory address to be tested and the standard data, and reads data from the memory address to be tested;

the detection unit is used for judging whether the read data read from the storage address to be detected is consistent with the standard data or not and generating a corresponding judgment result;

and under the condition that the read data read from the memory address to be detected is inconsistent with the standard data, judging that the memory unit corresponding to the memory address to be detected has a dead pixel.

2. The self-bad-point detection apparatus of claim 1, wherein the bus comprises a control bus and a data bus;

the self-detector is connected with the static random access memory in a mode of respectively accessing the control bus and the data bus.

3. The dead-spot self-detection apparatus of claim 1, wherein the self-detector further comprises:

and the counter is connected with the self-detector and used for taking the storage address to be detected as a dead pixel address and recording the number of the dead pixel addresses under the condition that the storage unit corresponding to the storage address to be detected has dead pixels according to the judgment result.

4. A self-bad-point detecting apparatus according to claim 3, wherein said self-detector further comprises:

and the alarm is connected with the counter and used for outputting corresponding alarm information under the condition that the number of the dead pixel addresses is greater than a preset threshold value.

5. The self-detection device of a dead pixel as claimed in claim 4, wherein the alarm includes a first sub-memory and a first comparator;

the first comparator is used for comparing the current number of the dead pixel addresses with the preset threshold value;

the first sub-memory is used for storing the alarm information.

6. The dead point self-detection device of claim 1, wherein the monitoring unit includes a multiplexer;

and the access end of the multiplexer is connected with the bus and is used for continuously monitoring the generation condition of the enabling signal of the controller so as to continuously monitor the real-time working state of the static random access memory.

7. The self-detection apparatus of claim 1, wherein the notification unit includes a second sub-memory and an address accumulator;

the second sub-memory is used for storing the standard data;

the address accumulator is used for determining the storage address to be detected corresponding to the current detection, and executing address accumulation operation on the storage address to be detected corresponding to the current detection under the condition that the current detection is completed so as to determine the storage address to be detected corresponding to the next detection.

8. The dead-spot self-detection device of claim 1, wherein the detection unit includes a second comparator;

the second comparator is connected with the bus and used for comparing the read data with the standard data.

9. The dead point self-detection device according to claim 8, wherein the notification unit is further connected to the second comparator; and the notification unit takes the memory address to be detected as a dead pixel address and sends the dead pixel address to the controller under the condition that the memory unit corresponding to the memory address to be detected has a dead pixel according to the result of the second comparator.

10. The dead point self-detection apparatus of claim 9, wherein the controller comprises:

and the third sub-memory is used for storing the dead pixel address.

11. A chip, characterized in that the chip is equipped with at least one static random access memory by the self-detection device of bad pixels according to any one of claims 1 to 10.

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