CN216721592U - 4G USB (universal serial bus) internet surfing rod driven to be installed automatically - Google Patents
4G USB (universal serial bus) internet surfing rod driven to be installed automatically Download PDFInfo
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- CN216721592U CN216721592U CN202123365326.9U CN202123365326U CN216721592U CN 216721592 U CN216721592 U CN 216721592U CN 202123365326 U CN202123365326 U CN 202123365326U CN 216721592 U CN216721592 U CN 216721592U
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Abstract
The application provides a drive self-installation 4G USB (universal serial bus) internet stick, which comprises a first wireless block, a second wireless block, a register and a wireless networking unit, wherein the first wireless block is used for operating in a drive-free mode, the second wireless block is used for operating in a standard mode, the register is connected with the first wireless block and the second wireless block, the register is used for processing a resource request and controlling the operation of the first wireless block or the second wireless block, the output ends of the first wireless block and the second wireless block are connected with the wireless networking unit, and the wireless networking unit is used for networking through 4G dialing; the coexisting device comprises a synchronous counter, the state calculator of the synchronous counter is a serial carry adder, the even number of the synchronous counter is composed of a phase inverter and a NOR gate, the odd number of the synchronous counter is a NAND gate, the phase inverter is connected with one input end of the NOR gate, the output end of the NOR gate is connected with one input end of the NAND gate, and the output end of the NAND gate is connected with one input end of the next NOR gate with the even number.
Description
Technical Field
The utility model relates to the field of wireless communication equipment, in particular to a drive self-installation 4G USB network rod.
Background
The device such as notebook computer, desktop computer, tablet personal computer (personal computer), medical equipment, Mobile Internet Device (MID) and handheld device is connected with peripheral equipment or wireless local area network through configuring network card, wherein, the 4G USB network stick supports various communication modes according to different communication protocols, and has the advantages of mobility, portability and wide application. The current 4G USB internet surfing rod is divided into a drive-free mode and a manual installation driving mode, if the two driving modes are combined into a whole, a standby function of manual installation driving is reserved under a special condition, the 4G USB internet surfing rod needs to be provided with a register, the register enables the internet surfing rod to run a second wireless block to use shared resources without waking up the first wireless block, and the allocation of blocks for processing resource requests is achieved. The coexistence means includes a synchronization counter that tracks the tracking duration, and control logic coupled to the counter that determines the duration. However, the synchronous counter requires an additional state calculator to calculate the count value, so the area of the synchronous counter is large, the delay generated when calculating the carry value is large, the operating frequency of the synchronous counter is low, the error generated by the register is large, and the operation of the 4G USB network rod is prone to failure.
Therefore, the application provides a drive self-mounting 4G USB network rod, which has a standard mode of mounting a drive and a drive-free mode of self-mounting the drive, has high working frequency of a synchronous counter of a memorizer, does not increase the circuit scale, and has stable operation.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a drive self-mounting 4G USB network rod, which has a standard mode for mounting a drive and a drive-free mode for driving the self-mounting, has high working frequency of a synchronous counter of a register, does not increase the circuit scale, and operates stably.
A drive self-mounted 4G USB internet stick comprises a first wireless block, a second wireless block, a register and a wireless networking unit, wherein the first wireless block is used for operating in a drive-free mode, the second wireless block is used for operating in a standard mode, the register is connected with the first wireless block and the second wireless block, the register is used for processing resource requests and controlling the operation of the first wireless block or the second wireless block, the output ends of the first wireless block and the second wireless block are connected with the wireless networking unit, and the wireless networking unit is connected with a 4G dial-up network; the register is characterized by comprising a synchronous counter, wherein a state calculator of the synchronous counter is a serial carry adder, the even number of the serial carry adder consists of a phase inverter and a NOR gate, the odd number of the phase inverter is a NAND gate, the phase inverter is connected with one input end of the NOR gate, the output end of the NOR gate is connected with one input end of the NAND gate, and the output end of the NAND gate is connected with one input end of the NOR gate at the next even number.
In some embodiments, the inverter of the 0 th bit of the serial carry adder is connected to the input a of the nor gate, the output of the 0 th bit of the nor gate is connected to the input B of the 1 st bit of the nand gate, the output of the 1 st bit of the nand gate is connected to the input B of the 2 nd bit of the nor gate, and the input a of the 2 nd bit of the nor gate is connected to the inverter; the output Y of the NAND gate of the 2n-1 th bit is connected with the input B of the NOR gate of the 2n th bit, and the input A of the NOR gate of the 2n th bit is connected with the inverter.
Further, the output end of the 0 th bit NOR gate of the serial carry adder is C0The input end B of the 0 th NAND gate is low level, the input end A is connected with the inverter, and the input of the input end of the 0 th inverter is A0The output of the 1 st bit NAND gate is C1The input of the input end B is C0Input terminal AIs shown as A1(ii) a The output of the output end of the NAND gate of the 2n-1 th bit is C2n-1The input of the input end A is A2n-1The output of the output terminal of the 2 n-th bit NOR gate is C2nThe input of the input end B is C2n-1The input end A is connected with a phase inverter, and the input end of the phase inverter is An。
Furthermore, the serial carry adder uses logic '1' (high level) as the carry flag, and the carry output value C of the 0 th bit0The preceding stage carry value used is fixed to "1".
Further, when all the inputs of the nor gate are low level (0), the output is high level (1), when one of the inputs of the nor gate is high level, the output is low level, when all the inputs of the nand gate are high level, the output is high level, when one of the inputs of the nand gate is low level, the output is high level, therefore, when the even bit carry flag is "0" (low level), the serial carry adder indicates that carry is needed, and when the odd bit carry flag is "1", the serial carry adder indicates that carry is needed.
Furthermore, the serial carry adder can obtain a carry output value through a NAND gate and a NOR gate by switching the carry flag. In the conventional serial carry synchronous counter, the carry flag is fixed, so that the carry output value can be obtained only through an AND gate or a NOT gate.
Furthermore, the serial carry adder adopts the NAND gate and the NOR gate to replace the AND gate and the OR gate used in the traditional structure, thereby saving the device delay caused by the inverter in the actual circuit structure. Thereby increasing the operating frequency of the synchronous counter without increasing the circuit scale of the synchronous counter.
Further, the serial carry adder uses logic "1" as a carry flag, and the logic expression Q1 at the ith bit is:
wherein Q isiRepresenting the output value of the ith bit of the adder, AiValue of the i-th bit of the addend, Ci-1Representing the carry out value of the i-1 th bit.
In some embodiments, the synchronization counter is one of 4 bits, 8 bits, 11 bits, and 16 bits.
In some embodiments, the synchronous counter further comprises a state latch (flip-flop), the state latch is connected to the state calculator, a clock signal of the state latch is provided by a clock pulse, an output (Q) of the state latch is connected to the state calculator, the state latch is used for inputting the current state to the state calculator, an output of the state calculator is connected to an input (D) of the state latch, and the state calculator is used for performing state calculation and inputting the obtained state of the next clock cycle to the input of the state latch to wait for latching.
In some embodiments, the self-mounted 4G USB net-up stick is driven up to 150Mbps in the downlink and up to 50Mbps in the uplink.
Drawings
Fig. 1 is a basic frame structure diagram of a synchronous counter according to embodiment 1 of the present application.
Fig. 2 is a schematic structural diagram of a serial carry adder of a synchronous counter according to embodiment 1 of the present application.
Detailed Description
The following examples are described to aid in the understanding of the present application and are not, and should not be construed to, limit the scope of the present application in any way.
In the following description, those skilled in the art will recognize that components may be described throughout this discussion as separate functional units (which may include sub-units), but those skilled in the art will recognize that various components or portions thereof may be divided into separate components or may be integrated together (including being integrated within a single system or component).
Further, connections between components or systems are not intended to be limited to direct connections. Rather, data between these components may be modified, reformatted, or otherwise changed by the intermediate components. Additionally, additional or fewer connections may be used. It should also be noted that the terms "coupled," "connected," or "input" should be understood to include direct connections, indirect connections through one or more intermediate devices, and wireless connections.
Example 1:
a drive self-mounted 4G USB internet stick comprises a first wireless block, a second wireless block, a register and a wireless networking unit, wherein the first wireless block is used for operating in a drive-free mode, the second wireless block is used for operating in a standard mode, the register is connected with the first wireless block and the second wireless block, the register is used for processing resource requests and controlling the operation of the first wireless block or the second wireless block, the output ends of the first wireless block and the second wireless block are connected with the wireless networking unit, and the wireless networking unit is connected with a 4G dial-up network; the register is characterized by comprising a synchronous counter, wherein a state calculator of the synchronous counter is a serial carry adder, the even number of the serial carry adder consists of a phase inverter and a NOR gate, the odd number of the phase inverter is a NAND gate, the phase inverter is connected with one input end of the NOR gate, the output end of the NOR gate is connected with one input end of the NAND gate, and the output end of the NAND gate is connected with one input end of the NOR gate at the next even number.
The synchronous counter is 11 bits, the structure of the serial carry adder is shown in fig. 2, the inverter of the 0 th bit of the serial carry adder is connected with the input end A of the NOR gate, the output end of the NOR gate of the 0 th bit is connected with the input end B of the NAND gate of the 1 st bit, the output end of the NAND gate of the 1 st bit is connected with the input end B of the NOR gate of the 2 nd bit, and the input end A of the NOR gate of the 2 nd bit is connected with the inverter; the output Y of the 9 th NAND gate is connected with the input B of the 10 th NOR gate, and the input A of the 10 th NOR gate is connected with the inverter. The output end of the 0 th bit NOR gate of the serial carry adder is C0The input end B of the 0 th NAND gate is low level, the input end A is connected with an inverter,the input of the input end of the 0 th bit inverter is A0The output of the 1 st bit NAND gate is C1The input of the input end B is C0The input of the input end A is A1(ii) a The output of the 9 th NAND gate is C9The input of the input end A is A9The output of the 10 th-bit NOR gate is C10The input of the input end B is C9The input end A is connected with a phase inverter, and the input of the input end of the phase inverter is A10. The serial carry adder adopts logic '1' (high level) as a carry mark, and the carry output value C of the 0 th bit0The preceding stage carry value used is fixed to "1". When all the inputs of the NOR gate are low level (0), the output is high level (1), when one of the inputs of the NOR gate is high level, the output is low level, when all the inputs of the NAND gate are high level, the output is low level, and when one of the inputs of the NAND gate is low level, the output is high level, therefore, when the even bit carry flag is 0 (low level), the serial carry adder indicates that carry is needed, and when the odd bit carry flag is 1, the serial carry adder indicates that carry is needed. The serial carry adder can obtain a carry output value through a NAND gate and a NOR gate by switching the carry flags. In the conventional serial carry synchronous counter, the carry flag is fixed, so that the carry output value can be obtained only through an AND gate or a NOT gate. The serial carry adder adopts the NAND gate and the NOR gate to replace the AND gate and the OR gate used in the traditional structure, thereby saving the device delay caused by the phase inverter in the actual circuit structure. Thereby increasing the operating frequency of the synchronous counter without increasing the circuit scale of the synchronous counter. The serial carry adder adopts logic '1' as a carry flag, and the logic expression Q1 of the ith bit is as follows:
wherein Q isiRepresenting the output value of the ith bit of the adder, AiValue of the i-th bit of the addend, Ci-1Representing the carry out value of the i-1 th bit.
The synchronous counter further comprises a state latch (flip-flop), the state latch is connected with the state calculator, a clock end signal of the state latch is provided by a clock pulse, an output end (Q) of the state latch is connected with the state calculator, the state latch is used for inputting the current state to the state calculator, an output end of the state calculator is connected with an input end (D) of the state latch, and the state calculator is used for performing state calculation and inputting the obtained state of the next clock cycle to the input end of the state latch to wait for latching, as shown in FIG. 1. The drive is from the descending of 4G USB net stick of installation up to 150Mbps, and the ascending is up to 50 Mbps.
While various aspects and embodiments have been disclosed herein, it will be apparent to those skilled in the art that other aspects and embodiments can be made without departing from the spirit of the disclosure, and that several modifications and improvements can be made without departing from the spirit of the disclosure. The various aspects and embodiments disclosed herein are presented by way of example only and are not intended to limit the present disclosure, which is to be controlled in the spirit and scope of the appended claims.
Claims (9)
1. A drive self-mounted 4G USB internet stick comprises a first wireless block, a second wireless block, a register and a wireless networking unit, wherein the first wireless block is used for operating in a drive-free mode, the second wireless block is used for operating in a standard mode, the register is connected with the first wireless block and the second wireless block, the register is used for processing resource requests and controlling the operation of the first wireless block or the second wireless block, the output ends of the first wireless block and the second wireless block are connected with the wireless networking unit, and the wireless networking unit is connected with a 4G dial-up network; the register is characterized by comprising a synchronous counter, wherein a state calculator of the synchronous counter is a serial carry adder, the even number of the serial carry adder consists of a phase inverter and a NOR gate, the odd number of the phase inverter is a NAND gate, the phase inverter is connected with one input end of the NOR gate, the output end of the NOR gate is connected with one input end of the NAND gate, and the output end of the NAND gate is connected with one input end of the NOR gate at the next even number.
2. The driven self-mounted 4G USB network stick of claim 1, wherein the inverter of the 0 th bit of the serial carry adder is connected with the input A of the NOR gate, the output of the NOR gate of the 0 th bit is connected with the input B of the NAND gate of the 1 st bit, the output of the NAND gate of the 1 st bit is connected with the input B of the NOR gate of the 2 nd bit, and the input A of the NOR gate of the 2 nd bit is connected with the inverter; the output Y of the NAND gate of the 2n-1 th bit is connected with the input B of the NOR gate of the 2n th bit, and the input A of the NOR gate of the 2n th bit is connected with the inverter.
3. The self-powered 4G USB network stick of claim 2 wherein the output of the 0 th bit NOR gate of the serial carry adder is C0The input end B of the 0 th NAND gate is low level, the input end A is connected with the inverter, and the input of the input end of the 0 th inverter is A0The output of the 1 st bit NAND gate is C1The input of the input end B is C0The input of the input end A is A1(ii) a The output of the output end of the NAND gate of the 2n-1 th bit is C2n-1The input of the input end A is A2n-1The output of the 2 n-th NOR gate is C2nThe input of the input end B is C2n-1The input end A is connected with a phase inverter, and the input end of the phase inverter is An。
4. The USB stick of claim 1, wherein the serial carry adder uses a logic "1" as a carry flag, and the carry output value C of the 0 th bit is the carry flag0The preceding stage carry value used is fixed to "1".
5. The USB stick of claim 4, wherein the output of the NOR gate is high when all inputs of the NOR gate are low, the output of the NOR gate is low when one of the inputs of the NOR gate is high, the output of the NAND gate is low when all inputs of the NAND gate are high, and the output of the NAND gate is high when one of the inputs of the NAND gate is low, so that the serial carry adder indicates that carry is required when the carry flag for the even bits is "0" and indicates that carry is required when the carry flag for the odd bits is "1".
6. The driven self-mounted 4G USB network stick of claim 5, wherein the serial carry adder switches carry flags to enable a carry output value to be derived through a NAND gate and a NOR gate.
7. The driven self-mounted 4G USB network stick of claim 1, wherein the synchronous counter is one of 4 bits, 8 bits, 11 bits, 16 bits.
8. The self-powered 4G USB gatekeeper of claim 1, wherein the synchronous counter further comprises a state latch, the state latch being connected to the state calculator, a clock signal of the state latch being provided by a clock pulse, an output of the state latch being connected to the state calculator, the state latch being adapted to input a current state to the state calculator, an output of the state calculator being connected to an input of the state latch, the state calculator being adapted to perform the state calculation and to input a resulting state for a next clock cycle to an input of the state latch to await latching.
9. The self-mounting enabled 4G USB netstick of claim 1, wherein the self-mounting enabled 4G USB netstick is enabled to drive up to 150Mbps in down and up to 50Mbps in up.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202123365326.9U CN216721592U (en) | 2021-12-29 | 2021-12-29 | 4G USB (universal serial bus) internet surfing rod driven to be installed automatically |
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| CN202123365326.9U CN216721592U (en) | 2021-12-29 | 2021-12-29 | 4G USB (universal serial bus) internet surfing rod driven to be installed automatically |
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| CN216721592U true CN216721592U (en) | 2022-06-10 |
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