CN216721179U

CN216721179U - Loop circuit compensation circuit

Info

Publication number: CN216721179U
Application number: CN202022830676.7U
Authority: CN
Inventors: 肖华; 赵志伟; 周阿铖
Original assignee: Shenzhen Nanyun Microelectronics Co ltd
Current assignee: Shenzhen Nanyun Microelectronics Co ltd
Priority date: 2020-11-30
Filing date: 2020-11-30
Publication date: 2022-06-10
Anticipated expiration: 2030-11-30

Abstract

The utility model provides a loop compensation circuit, which comprises a switch circuit, a hysteresis compensation circuit and a sampling circuit, wherein the switch circuit is used for being controlled by a control signal with fixed pulse width and proportional frequency to the switching frequency of a main power switching tube of a switching power supply and transmitting an error amplification signal output by a feedback network of the switching power supply to the hysteresis compensation circuit; the hysteresis compensation circuit is used for compensating an error amplification signal output by the switching power supply feedback network and transmitting the error amplification signal to the sampling circuit; the sampling circuit is used for sampling an error amplification signal output by the switching power supply feedback network and transmitting the error amplification signal and the compensated error amplification signal to the duty ratio control circuit of the main power switching tube of the switching power supply. The utility model enables the zero point to be directly added into the open-loop transmission function of the loop compensation circuit, does not need to wait for the conduction of other circuits, does not need to consider the response time of a buffer and the like, and accelerates the response of a power supply system.

Description

Loop circuit compensation circuit

Technical Field

The utility model relates to the field of switching converters, in particular to a loop compensation circuit.

Background

Switching converters (also known as switching power supplies) generally maintain the output voltage of the converter stable through a negative feedback control loop. However, for any negative feedback system, there is a problem of loop stability. The stability of the control system is determined by the system architecture, since the control system typically contains energy storage elements and inertial components, such as capacitors and inductors. Because the energy of such elements cannot change suddenly, when the system is disturbed or has input quantity, the control process is not completed immediately, but has a certain delay, and if the delay causes the fed back signal to be added to the original disturbed or input signal exactly in phase, the system will generate oscillation phenomenon. If this oscillation process is gradual, the system will eventually stabilize; if the oscillation process is maintained constant or gradually increased, the system will be out of control, i.e., an unstable system. According to the requirements of the Barkhausen criterion, the control system stability criterion is as follows: at frequencies where the open loop gain is 1 (i.e., crossover frequencies), the total open loop phase delay for all elements of the system must be less than 360 °. In addition, the phase margin is defined as the difference between the phase angle corresponding to the system at the crossover frequency and-180 °. The phase margin is too small, and the system can generate amplitude reduction oscillation; if the phase margin is too large, the response speed of the system becomes slow. In order to reduce the amplitude of the oscillations caused by the step response of the feedback system and to provide a fast adjustment speed, the phase margin is typically designed to be between 45 ° and 70 °.

In order to meet the phase margin requirement, a hysteresis compensation circuit is often used in the switching converter. As shown in fig. 3, the passive hysteresis compensation circuit is generally composed of two resistors R1, R2 and a capacitor C1 connected in series, whose transfer function gc(s) is given by equation (1),

in formula (1), s is an independent variable of the s domain, and is also called complex frequency.

Is provided with

Then equation (1) transforms to:

according to the common knowledge, the zero frequency fz and the pole frequency fp of the compensation are respectively:

the derivation of the above-mentioned formula related to the transfer function of the hysteresis compensation circuit and the frequency characteristics thereof are analyzed in detail in version 1 of "automatic control principle" compiled by Sunyuxian and Queen, published by the chemical industry Press, the ISBN number of the book is 978-7-122-11607-9, and in particular, the author describes the step of designing the hysteresis compensation circuit by applying the frequency domain method in pages 253 to 256 in "automatic control principle". To ensure that the lag angle of the lag compensation circuit at the system cutoff frequency fc (also referred to as the crossover frequency in switching converters) is no greater than-6 °, the zero frequency of the compensation is typically taken to be one tenth of the crossover frequency, and in switching converter systems, the crossover frequency is typically designed to be 1/6-1/10 of the switching frequency to meet stability requirements. The loop stability is analyzed in detail in the first edition of ' smart switching power supply design ' which is published by people's post and telecommunications press, written by Sanjaya Maniktala, translated by Wangzhiqiang et al, the ISBN number of the book is 978-7-115-18500-6, and the chapter 7 of the 1 st edition of the ' smart switching power supply design ', particularly the section 7.24 of page 201, provides a most popular and simplest method for judging the loop stability at present.

If the switching frequency of a power supply system is 100kHz, the maximum crossover frequency is 16.7kHz, and the zero frequency of the design using hysteresis compensation can be 1.67kHz, and as can be calculated from equations (3) and (4), when R2 is 68k Ω, C1 is 1.4nF, and when α is 6, R1 is 340k Ω.

If the power supply system adopts PFM control, the switching frequency will be reduced during light load, especially the no-load switching frequency will be reduced to the minimum, and the specifications of the compensation elements R1, R2, and C1 under full load and light load are calculated according to the above hysteresis compensation circuit design method, as shown in table one below, taking the no-load switching frequency as 1kHz as an example:

watch 1

Generally, for considering the no-load loop stability, the compensation capacitor C1 should be 140nF, but the capacitors of both 1.4nF and 140nF are not easy to integrate in the controller, and because the compensation capacitor is large, the slew rate of the output signal of the compensation circuit is also seriously affected, which results in poor and hard-to-correct dynamic characteristics of the system.

Although the resistor can be reduced in area by using a folding drawing method in the integrated circuit, and therefore, in the integrated circuit, the capacitor can be reduced by using a larger resistor to obtain a smaller area under the premise that the RC constant is not changed, even if this is done, it is still difficult to extend the prior art directly to the integrated circuit, as shown in the following table two:

watch two

As can be seen from table two, even if the resistance is enlarged by approximately 44 times, the capacitance C1 can only be reduced to 3.17nF, and still is not easy to be integrated, which is not favorable for improving the dynamic characteristics of the system.

Chinese patent No. CN201510574605.6 discloses a loop compensation circuit, which includes a switch circuit, a hysteresis compensation circuit, and a sampling circuit, wherein the switch circuit receives an error amplification signal output by a feedback network of a switching power supply under the control of a control signal with a preset duty ratio and transmits the error amplification signal to the hysteresis compensation circuit, and the preset duty ratio can amplify an RC constant of the hysteresis compensation circuit; the lag compensation circuit generates a compensated signal and transmits the compensated signal to the sampling circuit; the sampling circuit is controlled by another control signal with a preset duty ratio to transmit the received compensated signal to a duty ratio control circuit of a main power switching tube of the switching power supply. The sampling circuit completely stores the compensated signal and completely transmits the compensated signal to the duty ratio control circuit of the main power switching tube of the switching power supply. The preset duty ratio of the switching circuit is generated based on a driving signal of a main power switching tube of the switching power supply. The frequency of the control signal is in direct proportion to the switching frequency of the main power switch tube of the switching power supply. The preset duty cycle of the sampling circuit is the same as the preset duty cycle of the switching circuit. The control signal of the sampling circuit and the control signal of the switching circuit are a pair of synchronization signals.

The patent also discloses a specific circuit structure of the above circuit, and as shown in fig. 1, the loop compensation circuit (within a dashed line frame in fig. 1) includes a switch circuit 103, resistors R101 and R102, capacitors C101 and C102, a differential amplifier 104 and a sampling switch 105. The resistors R101 and R102 and the capacitor C101 constitute a hysteresis compensation circuit, and the differential amplifier 104, the sampling switch 105 and the capacitor C102 constitute a sampling circuit. The feedback pin FB is connected to the inverting input terminal of the transconductance amplifier 102 through a knee sampling module 101, the non-inverting input terminal of the transconductance amplifier 102 is connected to the reference voltage VFBR, the output terminal of the transconductance amplifier 102 is connected to the first terminal of the switching circuit 103 to form a node (i), the second terminal of the switching circuit 103 is connected to the first terminal of the first resistor R101 to form a node (ii), the third terminal of the switching circuit 103 is connected to the pulse generator 107 to form a node (iii), the second terminal of the first resistor R101 is connected to the first terminal of the resistor R102 to form a node (iv), the node (iv) is further connected to the non-inverting input terminal of the differential amplifier 104, the inverting input terminal of the differential amplifier 104 is connected to the output terminal of the differential amplifier 104 and the first terminal of the sampling switch 105, the second terminal of the sampling switch 105 is connected to the first terminal of the duty cycle control circuit 106, the second end of the sampling switch 105 is grounded through a second capacitor C102, the third end of the sampling switch 105 is connected with a node C, and the second end of the duty ratio control circuit 106 outputs a driving signal to control the main power switch tube SW. The switch circuit 103, as shown in fig. 2, includes a transmission gate circuit composed of a PMOS transistor PM1 and an NMOS transistor NM1, a not gate 111, where the drain of the PMOS transistor PM1 and the source of the NMOS transistor NM1 are connected to form a first end of the switch circuit, and are used to connect the output end of a transconductance amplifier of the flyback converter, the source of the PMOS transistor PM1 and the drain of the NMOS transistor NM1 are connected to form a second end of the switch circuit, and are connected to a compensation circuit, the input end of the not gate 111 and the gate of the NMOS transistor NM1 are connected to form a third end of the switch circuit, and are used to connect a pulse generator of the flyback converter, and the output end of the not gate 111 is connected to the gate of the PMOS transistor PM 1.

The patent can adopt passive devices such as smaller capacitors, resistors and the like to realize hysteresis compensation, and can integrate all control circuits into a controller, thereby reducing the number of peripheral elements and reducing the power cost. In the application occasion of a Pulse Frequency Modulation (PFM) control mode, dynamic zero and pole compensation can be realized, and the stability requirement of a switching power supply loop under the conditions of full load (higher switching frequency) and no load (lower switching frequency) can be met only by a relatively small capacitor.

However, the circuit disclosed above has the following problems:

only when the switch circuit 103 is turned on, the signal can be normally transmitted, that is, the zero and the pole compensated by the loop compensation circuit can be completely added to the open-loop transfer function only when the switch circuit 103 is turned on, so that the signal at the node (r) needs to be stored during the on-time of the switch circuit 103. When the switch circuit 103 is turned on and needs to pass through the differential amplifier 104, the differential amplifier 104 also needs a certain response time, and the effect of the zero point for accelerating the response speed of the power supply system is delayed. In the process of load jump of the power supply system, such as jump of a light load and full load, the working frequency of the power supply system is low during the light load, and when the system load changes, at least one switching cycle needs to be waited, and the response time of the differential amplifier 104 is added, so that the change of the load can be responded. The power system response time is delayed due to the effect of the zero point being delayed.

In addition, in practical use, in order to reliably transfer the zero point to the open-loop transfer function, the pulse width of the control signal of the switching circuit is limited by the response time of the differential amplifier 104. If the pulse width of the control signal is less than the response time of the differential amplifier 104, the differential amplifier 104 cannot fully add the zero to the open loop transfer function during the on period of the switching circuit 103, and the response of the power supply system lags the load change even more. The pole is to slow down the response of the power system, and if the fixed value is smaller than the response time of the differential amplifier 104, the pole cannot be completely added to the open loop transfer function through the differential amplifier 104 during the on period of the switch circuit 103, and the "slowing down the response of the power system" will slow down, but will promote the response of the power system.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned drawbacks and limitations of the prior art, the present invention provides a loop compensation circuit and a compensation method thereof, which can reduce the influence of the response time of a differential amplifier on the zero point and increase the response speed of a power system.

A loop compensation circuit is used for a switching power supply and comprises a switching circuit, a hysteresis compensation circuit and a sampling circuit, wherein the switching circuit, the hysteresis compensation circuit and the sampling circuit are sequentially connected in series, and the switching circuit is used for being controlled by a control signal and transmitting an error amplification signal output by a switching power supply feedback network to the hysteresis compensation circuit; the pulse width of the control signal is an adjustable fixed value, and the frequency of the control signal is in direct proportion to the switching frequency of a main power switching tube of the switching power supply; the delay compensation circuit is used for compensating an error amplification signal output by the switching power supply feedback network to obtain a compensation error amplification signal, and then transmitting the compensation error amplification signal to the sampling circuit, wherein the RC constant of the delay compensation circuit is amplified by the preset duty ratio of the control signal; the sampling circuit is used for sampling the error amplification signal output by the switching power supply feedback network to obtain a sampling error amplification signal, and transmitting the sampling error amplification signal and the compensation error amplification signal to the duty ratio control circuit of the switching power supply main power switching tube.

Preferably, the RC constant of the lag compensation circuit produces a pole in circuit operation and the sampled error amplified signal of the sampling circuit produces a zero in circuit operation.

The sampling circuit comprises a buffer, a resistor R103, a resistor R104 and a capacitor C102, wherein the input end of the buffer 104 is connected with a hysteresis compensation circuit, the output end of the buffer 104 is connected with one end of the resistor R104, one end of the resistor R103 is connected with the output end of a feedback network of the switching power supply, the other end of the resistor R103 is connected with the other end of the resistor R104, the input end of a duty ratio control circuit of the switching power supply and one end of the capacitor C102, and the other end of the capacitor C102 is connected with a reference potential.

Preferably, the buffer is a differential amplifier, the non-inverting input terminal of the differential amplifier is the input terminal of the buffer, and the inverting input terminal of the differential amplifier is connected to the output terminal of the differential amplifier to be the output terminal of the buffer.

One specific embodiment of the hysteresis compensation circuit includes a resistor device and a capacitor C101, one end of the resistor device is connected to the switch circuit, the other end of the resistor device is connected to a first end of the capacitor C101 and the sampling circuit, and a second end of the capacitor C101 is connected to a reference potential.

Preferably, the resistance device is composed of multiple resistances in series.

Preferably, the loop compensation circuit further comprises a fast response circuit connected in parallel with a part of the resistors of the multiple resistors.

Preferably, the fast response circuit comprises at least two bipolar transistors of the same or different types, or two MOS transistors of the same or different types, or two diodes.

The specific implementation mode of the fast response circuit comprises an NMOS tube NM2 and an NMOS tube NM3, wherein the grid and the drain of the NMOS tube NM2 are connected with the drain of the NMOS tube NM3 to form a first end of the fast response circuit, the first end of a resistor R101 is connected, the source of the NMOS tube NM2 is connected with the grid and the source of the NMOS tube NM3 to form a second end of the fast response circuit, and the second end of the resistor R101 is connected.

The switch circuit comprises a transmission gate circuit consisting of a PMOS pipe PM1 and an NMOS pipe NM1, a NOT gate 111, wherein the drain electrode of the PMOS pipe PM1 and the source electrode of the NMOS pipe NM1 are connected to form a first end of the switch circuit and are used for connecting the output end of a feedback network of a switching power supply, the source electrode of the PMOS pipe PM1 and the drain electrode of the NMOS pipe NM1 are connected to form a second end of the switch circuit and are connected with a hysteresis compensation circuit, the input end of the NOT gate 111 and the gate electrode of the NMOS pipe NM1 are connected to form a third end of the switch circuit and are used for connecting a pulse generator of the switching power supply, and the output end of the NOT gate 111 is connected with the gate electrode of the PMOS pipe PM 1.

The specific embodiment section analyzes the principles, functions and the like of each technical scheme and technical characteristics of the circuit, and the beneficial effects of the utility model are summarized as follows:

1. the zero point is directly added into an open-loop transmission function of the loop compensation circuit, the conduction of other circuits is not required to be waited, and meanwhile, the response time of a buffer and the like are not required to be considered, so that the response of a power supply system is accelerated;

2. the zero point is directly added into an open-loop transmission function of the loop compensation circuit, the size of a preset duty ratio of a switching circuit is not required to be considered, and the requirement on the response time of the buffer is reduced;

3. the requirement of quick dynamic response of a power supply system is met, a resistor device in the hysteresis compensation circuit is flexibly arranged, resistors R103 and R104 in the sampling circuit are arranged to meet the loading capacity of the buffer, and the circuit is simple to debug and easy to operate.

Drawings

FIG. 1 is a circuit schematic of a prior art loop compensation circuit;

FIG. 2 is a circuit schematic of a switching circuit in a prior art loop compensation circuit;

FIG. 3 is a schematic diagram of a conventional passive hysteresis compensation circuit;

FIG. 4 is a schematic circuit diagram of a first embodiment of the present invention;

FIG. 5 is a schematic circuit diagram of a second embodiment of the present invention;

FIG. 6 is a schematic circuit diagram of a fast response circuit in the loop compensation circuit of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not intended to limit the utility model.

First embodiment

As shown in fig. 4, which is a schematic circuit diagram of a first embodiment of the present invention, in a controller, a feedback pin FB is connected to an inverting input terminal of a transconductance amplifier 102 through a knee sampling module 101, a non-inverting input terminal of the transconductance amplifier 102 is connected to a reference voltage VFBR, an output terminal of the transconductance amplifier 102, a first terminal of a resistor R103, and a first terminal of a switch circuit 103 are connected to form a node (R), a second terminal of the switch circuit 103 is connected to a first terminal of the resistor R101 to form a node (R), a third terminal of the switch circuit 103 is connected to a pulse generator 106 to form a node (C), a second terminal of the resistor R101 is connected to a first terminal of the resistor R102, a second terminal of the resistor R102 is connected to a first terminal of the capacitor C101 to form a node (R), the node (R) is further connected to a non-inverting input terminal of a differential amplifier 104, a second terminal of the capacitor C101 is connected to a reference potential, and an inverting input terminal of the differential amplifier 104 is connected to an output terminal of the differential amplifier 104, The second end of the resistor R104 is connected, the first end of the resistor R104 and the second end of the resistor R103 are connected, the connection point of the resistor R104 and the resistor R103 is connected with the first end of the duty ratio control circuit 105 and the first end of the capacitor C102, the second end of the capacitor C102 is connected with a reference potential, and the second end of the duty ratio control circuit 106 outputs a driving signal to control the main power switch tube SW.

The loop compensation circuit (shown in a dashed line in fig. 4) of the present invention includes a switch circuit 103, resistors R101, R102, R103, and R104, capacitors C101 and C102, and a differential amplifier 104. The resistors R101 and R102 and the capacitor C101 constitute a hysteresis compensation circuit, and the differential amplifier 104, the resistor R103, the resistor R104 and the capacitor C102 constitute a sampling circuit. The switching circuit 103 takes a configuration as shown in fig. 2.

The switching circuit 103 is controlled by a control signal having a pulse width Tp and a period Tsw, the pulse width Tp being a fixed value, i.e. the duty cycle of the switching circuit 103 is Tp/Tsw < 1. When the error amplification signal at the node (I) changes, because the voltage at two ends of the capacitor (C101) cannot suddenly change at the node (II), the differential amplifier (104) transmits the voltage of the compensation error amplification signal at the node (II) to the output end of the differential amplifier (104) and the second end of the resistor (R104), and the change of the error amplification signal at the node (I) is sampled by the resistors (R103 and R104) and stored in the capacitor (C102) to form a zero point effect. The pole signal at the node R is stored in the capacitor C102 through the differential amplifier 104 and the resistors R103 and R104, so that the transfer function of the loop compensation circuit of the present invention is:

wherein

Therefore, the zero frequency fz and the pole frequency fp are compensated as follows:

through the selection of the resistors R103 and R104, a ratio alpha is formed, and the size ratio of the pole signal to the zero signal is also alpha.

First, in order to improve the attenuation effect on the high-frequency noise signal, the scaling factor α is set to 1/6, and then according to the general design experience of the switching power supply loop compensation and the hysteresis compensation, the zero frequency of the loop compensation circuit is set to 1/60 of the switching frequency. Now, if the period Tsw of the control signal of the switching circuit is consistent with the switching period, and the pulse width Tp of the control signal is 200ns, the full-load switching frequency is 100kHz (that is, the period Tsw is also 100kHz), the zero frequency fz of the compensation is 1.67kHz, according to the formula (6), (R101+ R102): C101 is 0.318 × 10-6, and if the capacitor C101 is 6.4pF, the resistor (R101+ R102) is 49.7k Ω, where R101 and R102 can be flexibly set according to the fast dynamic response requirement of the power system. Further, R103 and R104 are set to satisfy the ratio α and the load capacity of the buffer 104. The pole frequency fP is 0.278kHz, and under the parameter, the zero point frequency of compensation is 0.0167kHz and is 1/60 of 1kHz when the no-load switching frequency is calculated as 1kHz, and the stability requirement of no-load is also met.

The parameters obtained in this example were analyzed in conjunction with table two, as shown in table three below:

watch III

As can be seen from the above table, compared with the prior passive hysteresis compensation circuit technology, the utility model only needs to make the compensation resistor R₁₀₁、R₁₀₂By reducing the capacitance by 0.73 times, the compensation capacitor C can be reduced₁₀₁4 orders of magnitude are reduced, and the integration difficulty is greatly reduced.

Second embodiment

Fig. 5 is a schematic circuit diagram of a second embodiment of the present invention, which is different from the first embodiment in that a fast response circuit 205 is further included and connected in parallel to the resistor R₂₀₁(R₁₀₁) Two ends.

The fast response circuit 205 is composed of two NMOS transistors, a node of connecting the gate and the drain of the NMOS transistor NM2, and the drain of the NMOS transistor NM3, and a node of connecting the source of the NMOS transistor NM2, and the gate and the source of the NMOS transistor NM3, as shown in fig. 6.

The fast response circuit 205 will only operate when the converter load changes suddenly. When the load of the converter changes suddenly, the error amplifier outside the controller responds instantaneously to change the error amplification signal V_EA. For example, the converter load suddenly increases, the output voltage decreases, and the error amplification signal V_EAWhen the switch circuit 203 is turned on, the voltage at node II is much higher than node V, and the NMOS transistor NM2 is turned on to turn on the resistor R₂₀₁Short circuit, the response speed of the lag compensation circuit is improved, the problems of poor dynamic performance and the like caused by low pole frequency are effectively avoided, and the dynamic response characteristic of a loop is improved; similarly, if the load suddenly becomes smaller, the error amplification signal V_EAAnd the smaller the NMOS transistor NM3 is, the higher the response speed of the loop compensation circuit.

The dynamic response circuit in the second embodiment is combined with the utility model to accelerate the response speed of the loop compensation circuit together, thereby accelerating the response speed of the system.

The foregoing is merely a preferred embodiment of this invention, it being noted that the above-mentioned preferred embodiment should not be considered as limiting of this invention, and it being recognized that this invention is applicable in other broader contexts. According to the present invention, it is possible to make various modifications, substitutions and alterations without departing from the basic technical idea of the utility model, and it is within the scope of the appended claims.

Claims

1. The utility model provides a loop compensation circuit for switching power supply, includes switch circuit, hysteresis compensation circuit and sampling circuit, and switch circuit, hysteresis compensation circuit and sampling circuit establish ties in proper order, its characterized in that:

the switching circuit is used for being controlled by the control signal and transmitting an error amplification signal output by the switching power supply feedback network to the hysteresis compensation circuit;

the pulse width of the control signal is an adjustable fixed value, and the frequency of the control signal is in direct proportion to the switching frequency of a main power switching tube of the switching power supply;

the delay compensation circuit is used for compensating an error amplification signal output by the switching power supply feedback network to obtain a compensation error amplification signal, and then transmitting the compensation error amplification signal to the sampling circuit, wherein the RC constant of the delay compensation circuit is amplified by the preset duty ratio of the control signal;

the sampling circuit is used for sampling the error amplification signal output by the switching power supply feedback network to obtain a sampling error amplification signal, and transmitting the sampling error amplification signal and the compensation error amplification signal to the duty ratio control circuit of the switching power supply main power switching tube.

2. The loop compensation circuit of claim 1, wherein: the RC constant of the lag compensation circuit generates a pole in the circuit work, and the sampling error amplification signal of the sampling circuit generates a zero in the circuit work.

3. The loop compensation circuit of claim 1, wherein: the sampling circuit comprises a buffer and a resistor R₁₀₃Resistance R₁₀₄And a capacitor C₁₀₂The input terminal of the buffer 104 is connected to the hysteresis compensation circuit, and the output terminal of the buffer 104 is connected to the resistor R₁₀₄Is connected to a resistor R₁₀₃One end of the resistor R is used for being connected with the output end of the feedback network of the switching power supply₁₀₃Another terminal of (1) and a resistor R₁₀₄The other end of the capacitor (C), the input end of the duty ratio control circuit of the switching power supply and the capacitor (C)₁₀₂One end connected to a capacitor C₁₀₂To the reference potential.

4. The loop compensation circuit of claim 3, wherein: the buffer is a differential amplifier, the positive phase input end of the differential amplifier is the input end of the buffer, and the negative phase input end of the differential amplifier is connected with the output end of the differential amplifier to form the output end of the buffer.

5. The loop compensation circuit of claim 1, wherein: the hysteresis compensation circuit comprises a resistance device and a capacitor C₁₀₁One end of the resistance device is connected with the switch circuit, and the other end of the resistance device is connected with the capacitor C₁₀₁Is connected with a sampling circuit and a capacitor C₁₀₁The second terminal of (a) is connected to a reference potential.

6. The loop compensation circuit of claim 5, wherein: the resistor device is formed by connecting multiple resistors in series.

7. The loop compensation circuit of claim 6, wherein: the circuit also comprises a quick response circuit which is connected with part of the resistors in the multiple resistors in parallel.

8. The loop compensation circuit of claim 7, wherein: the quick response circuit at least comprises two bipolar transistors of the same or different types, or two MOS transistors of the same or different types, or two diodes.

9. The loop compensation circuit of claim 7, wherein: the quick response circuit comprises an NMOS (N-channel metal oxide semiconductor) tube NM2 and an NMOS tube NM3, wherein the grid and the drain of the NMOS tube NM2 are connected with the drain of the NMOS tube NM3 to form a first end of the quick response circuit, and a connecting resistor R₁₀₁The source of the NMOS transistor NM2, the grid and the source of the NMOS transistor NM3 are connected to form the second end of the quick response circuit, and a resistor R is connected₁₀₁The second end of (a).

10. The loop compensation circuit of claim 1, wherein: the switch circuit comprises a transmission gate circuit consisting of a PMOS pipe PM1 and an NMOS pipe NM1, a NOT gate 111, wherein the drain electrode of the PMOS pipe PM1 is connected with the source electrode of the NMOS pipe NM1 to form a first end of the switch circuit and is used for connecting the output end of a feedback network of a switch power supply, the source electrode of the PMOS pipe PM1 is connected with the drain electrode of the NMOS pipe NM1 to form a second end of the switch circuit and is connected with a hysteresis compensation circuit, the input end of the NOT gate 111 is connected with the gate electrode of the NMOS pipe NM1 to form a third end of the switch circuit and is used for connecting a pulse generator of the switch power supply, and the output end of the NOT gate 111 is connected with the gate electrode of the PMOS pipe PM 1.