CN216698369U - Display substrate and display device - Google Patents

Abstract

A display substrate and a display device are provided. The display substrate is provided with a display area, a barrier area and an open area and comprises a substrate, wherein the barrier area comprises at least one barrier wall at least partially surrounding the open area, each barrier wall comprises a first metal layer structure and a first laminated structure, and at least one side surface of the first metal layer structure surrounding the open area is provided with a first notch; the display area comprises a plurality of sub-pixels, each of the plurality of sub-pixels comprises a pixel driving circuit and a light-emitting device, the pixel driving circuit comprises a thin film transistor and a connecting electrode, the thin film transistor comprises a first source drain electrode and a second source drain electrode, the light-emitting device comprises a first electrode, a second electrode and a light-emitting material layer between the first electrode and the second electrode, and the connecting electrode is configured to be electrically connected with the first electrode and the first source drain electrode; the first metal layer structure and the connecting electrode are arranged on the same layer. The display substrate has higher reliability and simpler preparation process.

Description

Display substrate and display device

Technical Field

The embodiment of the disclosure relates to a display substrate and a display device.

Background

At present, the display screen of the display device is developing towards large screen and full screen. In general, a display device (e.g., a mobile phone, a tablet computer, etc.) has an image pickup device (or an imaging device) which is generally disposed on a side outside a display area of a display screen. However, since the image pickup apparatus needs a certain position for mounting, it is disadvantageous for the full-screen and narrow-bezel design of the display screen. For example, the camera device may be combined with the display area of the display screen, in which a position is reserved for the camera device to obtain a maximization of the display area of the display screen.

SUMMERY OF THE UTILITY MODEL

At least one embodiment of the present disclosure provides a display substrate having a display region, a barrier region and an open region, and including a substrate, wherein the display region and the barrier region surround the open region, the barrier region is located between the display region and the open region, the barrier region includes at least one barrier wall at least partially surrounding the open region, each of the at least one barrier wall includes a first metal layer structure and a first stacked structure, the first metal layer structure is located on a side of the first stacked structure away from the substrate, and at least one side of the first metal layer structure surrounding the open region has a first notch; the display area comprises a plurality of sub-pixels, each of the plurality of sub-pixels comprises a pixel driving circuit and a light-emitting device, the pixel driving circuit comprises a thin film transistor and a connecting electrode, the thin film transistor comprises a first source drain electrode and a second source drain electrode, the light-emitting device comprises a first electrode, a second electrode and a light-emitting material layer between the first electrode and the second electrode, and the connecting electrode is configured to be electrically connected with the first electrode and the first source drain electrode; the first metal layer structure and the connecting electrode are arranged on the same layer.

For example, in a display substrate provided by at least one embodiment of the present disclosure, the first metal layer structure includes a first metal sub-layer and a second metal sub-layer disposed on a side of the first metal sub-layer away from the substrate, and in a direction parallel to a plane of the substrate, the first metal sub-layer is retracted relative to the second metal sub-layer to form the first notch; or the first metal layer structure comprises a first metal sublayer, a second metal sublayer arranged on one side, far away from the substrate base plate, of the first metal sublayer and a third metal sublayer arranged on one side, close to the substrate base plate, of the first metal sublayer, and the first metal sublayer is retracted relative to the second metal sublayer and the third metal sublayer in a direction parallel to the plate surface of the substrate base plate so as to form the first notch.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the display region further includes a first planarization layer disposed on a side of the first source/drain electrode and the second source/drain electrode, the side being away from the substrate, the first planarization layer has a first via hole, the connection electrode is disposed on a side of the first planarization layer, the side being away from the substrate, and is electrically connected to the first source/drain electrode through the first via hole, the first stacked structure includes a first insulating sub-layer disposed on the substrate, and the first insulating sub-layer and the first planarization layer are disposed on the same layer.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the at least one barrier wall includes a plurality of barrier walls; the first metal layer structures of the multiple barrier walls are arranged at intervals on the same layer, and the first laminated structures of the multiple barrier walls are arranged at intervals on the same layer; or the first metal layer structures of the plurality of barrier walls are arranged on the same layer at intervals, and the first laminated structures of the plurality of barrier walls are arranged on the same layer and are of an integral structure.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the integrated structure has a barrier groove between the first metal layer structures of the adjacent barrier walls.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the display region further includes a first passivation layer disposed on a side of the first planarization layer away from the substrate, the first passivation layer has a second via hole penetrating through the first via hole, the connection electrode is disposed on a side of the first passivation layer away from the substrate and is electrically connected to the first source/drain electrode through the first via hole and the second via hole, the first stacked structure further includes a second insulating sub-layer disposed on a side of the first insulating sub-layer away from the substrate, and the second insulating sub-layer and the first passivation layer are disposed on the same layer.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the first insulating sub-layer has a groove between the first metal layer structures of the adjacent barrier walls, and the second insulating sub-layer is formed with equal thickness on a side of the first insulating sub-layer away from the substrate, so as to form a barrier groove at the groove.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the display region further includes a second passivation layer disposed on a side of the first source/drain electrode and the second source/drain electrode away from the substrate, the second passivation layer has a third via hole, the connection electrode is disposed on a side of the second passivation layer away from the substrate and is electrically connected to the first source/drain electrode through the third via hole, the first stacked structure includes a third insulating sub-layer disposed on the substrate, and the third insulating sub-layer and the second passivation layer are disposed on the same layer.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the at least one barrier wall includes a plurality of barrier walls; the first metal layer structures of the multiple barrier walls are arranged at the same layer and at intervals, and the first laminated structures of the multiple barrier walls are arranged at the same layer and at intervals; or the first metal layer structures of the plurality of barrier walls are arranged on the same layer at intervals, and the first laminated structures of the plurality of barrier walls are arranged on the same layer and are of an integral structure.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the third insulating sublayer in the integrated structure has a barrier groove between the first metal layer structures of the adjacent barrier walls.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the first stacked structure further includes a first metal layer, the first metal layer is disposed on a side of the first insulating sublayer close to the substrate, and the first metal layer, the first source/drain electrode, and the second source/drain electrode are disposed in the same layer.

For example, at least one embodiment of the present disclosure provides a display substrate, wherein the pixel driving circuit further includes a storage capacitor, the thin film transistor also comprises a first grid electrode which is arranged on one side of the first source-drain electrode and the second source-drain electrode close to the substrate base plate, the storage capacitor comprises a first capacitor plate and a second capacitor plate, the first capacitor plate and the first grid electrode are arranged on the same layer, the second capacitor plate is arranged on one side of the first capacitor plate far away from the substrate base plate, the first laminated structure further comprises a second metal layer and a third metal layer, the second metal layer is arranged on one side of the third metal layer far away from the substrate base plate, the second metal layer and the second capacitor plate are arranged on the same layer, and the third metal layer and the first capacitor plate are arranged on the same layer.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the display region further includes a gate insulating layer disposed between the first gate electrode and the second capacitor plate, and the gate insulating layer further extends into the barrier region and is disposed between the second metal layer and the third metal layer.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the display region further includes an interlayer insulating layer disposed on a side of the second capacitor plate away from the substrate, and the interlayer insulating layer further extends into the blocking region and is disposed on a side of the second metal layer away from the substrate.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the thin film transistor further includes a second gate electrode, the second gate electrode is disposed on a side of the interlayer insulating layer away from the substrate, the first stacked structure further includes a fourth metal layer, and the fourth metal layer and the second gate electrode are disposed on the same layer.

For example, a display substrate provided by at least one embodiment of the present disclosure further includes a circuit region disposed between the display region and the barrier region and at least partially surrounding the display region, where the circuit region includes a plurality of conductive layers and a plurality of insulating layers located between adjacent conductive layers.

At least one embodiment of the present disclosure further provides a display device, which includes the display substrate provided in the embodiment of the present disclosure.

At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate, including: forming a display region, a barrier region and an open region, wherein the display region and the barrier region surround the open region, and the barrier region is located between the display region and the open region; wherein forming the barrier region comprises: forming at least one barrier wall at least partially surrounding the open area, each of the at least one barrier wall comprising a first metal layer structure and a first laminated structure, the first metal layer structure being formed on a side of the first laminated structure remote from the substrate base plate, at least one side of the first metal layer structure surrounding the open area having a first recess; forming the display area includes: forming a plurality of sub-pixels, each of the plurality of sub-pixels including a pixel driving circuit and a light emitting device, the pixel driving circuit including a thin film transistor and a connection electrode, the thin film transistor including a first source drain electrode and a second source drain electrode, the light emitting device including a first electrode, a second electrode and a light emitting material layer between the first electrode and the second electrode, the connection electrode being formed to electrically connect the first electrode and the first source drain electrode; and the first metal layer structure and the connecting electrode are formed in the same layer.

For example, in a manufacturing method provided by at least one embodiment of the present disclosure, the first metal layer structure includes a first metal sub-layer and a second metal sub-layer formed on a side of the first metal sub-layer away from the substrate base plate, and in a direction parallel to a plate surface of the substrate base plate, the first metal sub-layer is formed to be retracted relative to the second metal sub-layer to form the first notch; or the first metal layer structure comprises a first metal sublayer, a second metal sublayer formed on one side, far away from the substrate base plate, of the first metal sublayer and a third metal sublayer formed on one side, close to the substrate base plate, of the first metal sublayer, and in the direction parallel to the plate surface of the substrate base plate, the first metal sublayer is formed to be retracted relative to the second metal sublayer and the third metal sublayer so as to form the first notch; forming the display area further comprises: the first planarization layer is formed on one side, far away from the substrate base plate, of the first source drain electrode and the second source drain electrode, the first planarization layer is provided with a first through hole, the connecting electrode is formed on one side, far away from the substrate base plate, of the first planarization layer and is electrically connected with the first source drain electrode through the first through hole, the first laminated structure comprises a first insulating sub-layer formed on the substrate base plate, and the first insulating sub-layer and the first planarization layer are formed on the same layer.

For example, in a manufacturing method provided by at least one embodiment of the present disclosure, the first metal layer structure includes a first metal sub-layer and a second metal sub-layer formed on a side of the first metal sub-layer away from the substrate base plate, and in a direction parallel to a plate surface of the substrate base plate, the first metal sub-layer is formed to be retracted relative to the second metal sub-layer to form the first notch; or the first metal layer structure comprises a first metal sublayer, a second metal sublayer formed on one side, far away from the substrate base plate, of the first metal sublayer and a third metal sublayer formed on one side, close to the substrate base plate, of the first metal sublayer, and in the direction parallel to the plate surface of the substrate base plate, the first metal sublayer is formed to be retracted relative to the second metal sublayer and the third metal sublayer so as to form the first notch; forming the display area further comprises: and forming a second passivation layer on one side of the first source drain electrode and the second source drain electrode, which is far away from the substrate base plate, wherein the second passivation layer is provided with a third through hole, the connecting electrode is formed on one side of the second passivation layer, which is far away from the substrate base plate, and is electrically connected with the first source drain electrode through the third through hole, the first laminated structure comprises a third insulating sublayer formed on the substrate base plate, and the third insulating sublayer and the second passivation layer are formed on the same layer.

For example, in a manufacturing method provided in at least one embodiment of the present disclosure, forming the first metal layer structure and the connection electrode includes: forming a connecting electrode material layer, and patterning the connecting electrode material layer to form the connecting electrode and a first metal layer initial structure; forming a second planarization layer on the connection electrode and one side of the first metal layer initial structure far away from the substrate, wherein the second planarization layer comprises a third through hole exposing the connection electrode and an opening exposing the first metal layer initial structure; and forming a first electrode material layer on one side of the second planarization layer, which is far away from the substrate base plate, and etching the first electrode material layer and the first metal layer initial structure by using the same etching liquid to form the first electrode and the first notch, wherein the first electrode is electrically connected with the connecting electrode through the third via hole.

For example, the preparation method provided by at least one embodiment of the present disclosure further includes: forming a circuit region between the display region and the barrier region and at least partially surrounding the display region, the circuit region including a plurality of conductive layers and a plurality of insulating layers between adjacent conductive layers; after the connection electrode and the first metal layer initial structure are formed, the plurality of conducting layers and the plurality of insulating layers located between the adjacent conducting layers are formed, and then the first electrode material layer and the first metal layer initial structure are etched by the same etching liquid.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1A is a schematic plan view of a display substrate;

FIG. 1B is a schematic cross-sectional view of the display substrate of FIG. 1A taken along line A-A;

fig. 2 is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure;

FIG. 3 is a schematic cross-sectional view of the display substrate of FIG. 2 taken along line B-B;

FIG. 4 is a schematic cross-sectional view of the display substrate of FIG. 2 along line C-C;

fig. 5A is a schematic cross-sectional view of a barrier wall in a display substrate according to at least one embodiment of the present disclosure;

fig. 5B is another schematic cross-sectional view of a barrier wall in a display substrate according to at least one embodiment of the present disclosure;

fig. 5C is a schematic cross-sectional view of a connection electrode in a display substrate according to at least one embodiment of the present disclosure;

fig. 5D is another schematic cross-sectional view of a connection electrode in a display substrate according to at least one embodiment of the present disclosure;

fig. 5E is a schematic cross-sectional view of a barrier rib broken light-emitting material layer in a display substrate according to at least one embodiment of the present disclosure;

FIG. 6A is another schematic cross-sectional view of the display substrate of FIG. 2 taken along line B-B;

FIG. 6B is a schematic cross-sectional view of the display substrate of FIG. 2 taken along line B-B;

FIG. 6C is a schematic cross-sectional view of the display substrate of FIG. 2 taken along line B-B;

FIG. 6D is a schematic cross-sectional view of the display substrate shown in FIG. 2 taken along line B-B;

FIG. 7A is another schematic cross-sectional view of the display substrate of FIG. 2 taken along line C-C;

FIG. 7B is a schematic cross-sectional view of the display substrate of FIG. 2 taken along line C-C;

FIG. 8 is a schematic cross-sectional view of the display substrate of FIG. 2 taken along line B-B; and

fig. 9A-13B are schematic cross-sectional views of a display substrate provided in at least one embodiment of the present disclosure during a manufacturing process.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and the like in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In order to maximize the display area of the display device, an image pickup device (imaging device) provided in the display device may be integrated with the display area, and the image pickup device may be disposed in the display area.

For example, fig. 1A is a schematic plan view illustrating a display substrate for a display device, and fig. 1B is a schematic cross-sectional view of the display substrate of fig. 1A taken along a-a line. As shown in fig. 1A, the display substrate 10 includes a display area 12, the display area 12 includes a pixel array and has an opening 11 in the pixel array, the opening 11 reserves a position for an image pickup device (not shown), and the image pickup device may be disposed on a back side of the display substrate 10 opposite to the display side so that the image pickup device can acquire an image through the opening 11. Thereby, the image pickup device is integrated with the display area 12 of the display substrate 10.

The display region 12 has a light emitting device for display, for example, an organic light emitting diode, and the organic material layer 13 and the electrode layer 14 which the plurality of light emitting devices in all or part of the display region 12 have are usually formed in the entire surface of the display region 12, and therefore when the encapsulation is performed using the encapsulation layer 15, the region located in the vicinity of the opening 11 tends to be difficult to be encapsulated, or even if encapsulated, it is difficult to ensure the encapsulation effect of the region. At this time, as shown in fig. 1B, impurities such as water and oxygen may enter the display region 12 from the organic functional layer 13 and the electrode layer 14 formed along the entire surface of the opening 11, contaminate the functional materials in the display region 12, cause performance degradation of the functional materials, and further affect the display effect of the display region 12.

At least one embodiment of the present disclosure provides a display substrate, a method for manufacturing the same, and a display device, the display substrate having a display region, a barrier region, and an open region, and including a substrate base plate, wherein the display region and the barrier region surround the open region, the barrier region is located between the display region and the open region, the barrier region includes at least one barrier wall at least partially surrounding the open region, each of the at least one barrier wall includes a first metal layer structure and a first stacked structure, the first metal layer structure is located on a side of the first stacked structure away from the substrate base plate, and at least one side of the first metal layer structure surrounding the open region has a first recess; the display area comprises a plurality of sub-pixels, each of the plurality of sub-pixels comprises a pixel driving circuit and a light-emitting device, the pixel driving circuit comprises a thin film transistor and a connecting electrode, the thin film transistor comprises a first source drain electrode and a second source drain electrode, the light-emitting device comprises a first electrode, a second electrode and a light-emitting material layer between the first electrode and the second electrode, and the connecting electrode is configured to be electrically connected with the first electrode and the first source drain electrode; the first metal layer structure and the connecting electrode are arranged on the same layer.

The display substrate can utilize the barrier wall to disconnect the functional layers such as the luminescent material layer and the like so as to effectively prevent impurities such as water, oxygen and the like from entering the display area of the display substrate from the open pore area along the functional layers such as the luminescent material layer and the like, thereby improving the reliability of the display substrate; in addition, the first metal layer structure of the barrier wall and the connecting electrode are arranged on the same layer, so that the first metal layer structure and the connecting electrode can be formed by adopting the same composition process in the preparation process, and the preparation process of the display substrate is simplified; on the other hand, the barrier wall comprises the first laminated structure and the first metal layer structure arranged on the first laminated structure, so that the height of the first metal layer structure relative to the substrate base plate is higher, and when the first metal layer structure of the barrier wall is formed by adopting a composition process, the problems that the first notch of the first metal layer structure is difficult to etch due to the fact that photoresist is too thick and the like can be avoided.

The display substrate, the method for manufacturing the same, and the display device of the present disclosure are described below with reference to several specific examples.

At least one embodiment of the present disclosure provides a display substrate, in which fig. 2 illustrates a schematic plan view of the display substrate, fig. 3 illustrates a schematic cross-sectional view of the display substrate along a line B-B, and fig. 4 illustrates a schematic cross-sectional view of the display substrate along a line C-C.

As shown in fig. 2 and 3, the display substrate has a display region 101, a barrier region 201, and an open region 301, and includes a substrate 1011. As shown in fig. 2, the display area 101 and the blocking area 201 surround the opening area 301, and the blocking area 201 is located between the display area 101 and the opening area 301.

For example, as shown in fig. 3, the blocking region 201 includes at least one blocking wall 202 (five blocking walls 202 are shown as an example) at least partially surrounding (e.g., completely surrounding) the open region 301, each blocking wall 202 includes a first metal layer structure 202A and a first stacked structure 202B, the first metal layer structure 202A is located on a side of the first stacked structure 202B away from the substrate base plate 1011, and at least one side of the first metal layer structure 202A surrounding the open region 301 has a first recess 202C.

For example, the side of the first metal layer structure 202A facing the open region 301 has the first recess 202C, or the side of the first metal layer structure 202A facing the display region 101 has the first recess 202C, or both the side of the first metal layer structure 202A facing the open region 301 and the side facing the display region 101 have the first recess 202C, which is the case shown in fig. 3.

In the embodiment of the disclosure, the barrier ribs 202 may block off a functional layer formed on the entire surface of the display substrate, such as a light emitting material layer of the light emitting device (described in detail later), so that impurities such as water and oxygen may be effectively prevented from entering the display region 101 of the display substrate from the opening region 301 along the functional layer such as the light emitting material layer, and thus reliability of the display substrate may be improved.

For example, as shown in fig. 4, the display region 101 includes a plurality of sub-pixels each including a pixel driving circuit including a thin film transistor 102, a storage capacitor 103, a connection electrode CEL, and the like, and a light emitting device 104. For example, the thin film transistor 102 includes an active layer 1021, and a first source-drain electrode 1023 and a second source-drain electrode 1024, and one of the first source-drain electrode 1023 and the second source-drain electrode 1024 is a source and the other is a drain. The storage capacitor 103 comprises a first capacitor plate 1031 and a second capacitor plate 1032.

For example, the light emitting device 104 includes a first electrode 1041, a second electrode 1043, and a light emitting material layer 1042 between the first electrode 1041 and the second electrode 1043, and a connection electrode CEL is configured to electrically connect the first electrode 1041 and a first source-drain electrode 1023. For example, the first electrode 1041 is implemented as an anode of the light emitting device 104, and the second electrode 1043 is implemented as a cathode of the light emitting device 104. The light emitting material layer 1042 may include an organic light emitting layer and an auxiliary light emitting layer including one or more of an electron transport layer, an electron injection layer, a hole transport layer, a hole injection layer, and the like.

For example, the first metal layer structure 202A of the barrier wall 202 is disposed in the same layer as the connection electrode CEL.

In the embodiments of the present disclosure, the "same layer arrangement" means that two (or more) functional layers or structural layers are formed in the same layer and the same material in the hierarchical structure of the display substrate, that is, in the manufacturing process, the two functional layers or structural layers may be formed by the same material layer, and the required patterns and structures may be formed by the same patterning process. Thereby, the manufacturing process of the display substrate can be simplified.

For example, in some embodiments, as shown in fig. 5A, the first metal layer structure 202A includes a first metal sub-layer 2021 and a second metal sub-layer 2022 disposed on a side of the first metal sub-layer 2021 away from the substrate 1011, and in a direction parallel to the plane of the substrate 1011, i.e., in a horizontal direction in the figure, the first metal sub-layer 2021 is retracted relative to the second metal sub-layer 2022 to form a first recess 202C; alternatively, in other embodiments, as shown in fig. 5B, the first metal layer structure 202A includes a first metal sub-layer 2021, a second metal sub-layer 2022 disposed on a side of the first metal sub-layer 2021 away from the substrate 1011, and a third metal sub-layer 2023 disposed on a side of the first metal sub-layer 2021 close to the substrate 1011, where the first metal sub-layer 2021 is retracted relative to the second metal sub-layer 2022 and the third metal sub-layer 2023 in a direction parallel to the plane of the substrate 1011 to form the first recess 202C, which is also the case shown in fig. 3.

For example, for the first metal layer structure 202A shown in fig. 5A, as shown in fig. 5C, the connection electrode CEL at this time includes the first sublayer CEL1 and the second sublayer CEL2, and the first metal sublayer 2021 and the second metal sublayer 2022 of the first metal layer structure 202A are respectively disposed in a one-to-one correspondence layer with the first sublayer CEL1 and the first sublayer CEL 2. For example, for the first metal layer structure 202A shown in fig. 5B, as shown in fig. 5D, the connection electrode CEL at this time includes the first sublayer CEL1, the second sublayer CEL2 and the third sublayer CEL3, and the first metal sublayer 2021, the second metal sublayer 2022 and the third metal sublayer 2023 of the first metal layer structure 202A are respectively disposed in one-to-one correspondence with the first sublayer CEL1, the second sublayer CEL2 and the third sublayer CEL 3. The multilayer structure connecting the electrodes CEL is not shown in fig. 4 for clarity and simplicity of illustration.

For example, for the embodiment of fig. 5A and 5C, the two-layer metal layer structure connecting the electrode CEL and the first metal layer structure 202A may be, for example, titanium/aluminum, molybdenum/aluminum, titanium/copper, or molybdenum/copper, etc., for the embodiment of fig. 5B and 5D, the three-layer metal layer structure connecting the electrode CEL and the first metal layer structure 202A may be, for example, titanium/aluminum/titanium, molybdenum/aluminum/molybdenum, titanium/copper/titanium, or molybdenum/copper/molybdenum, etc., and the embodiment of the present disclosure does not limit the specific materials of the connecting electrode CEL and the first metal layer structure 202A.

For example, in some embodiments, the light emitting material layer 1042 and the second electrode 1043 are formed on the entire surface of the display substrate, at this time, as shown in fig. 5E, the barrier wall 202 may disconnect the light emitting material layer 1042 and the second electrode 1043, when the light emitting material layer 1042 and the second electrode 1043 located at a side close to the opening region 301 are contaminated by impurities such as water, oxygen, and the like, since the light emitting material layer 1042 and the second electrode 1043 are disconnected by the barrier wall 202, the contamination impurities do not extend into the light emitting material layer 1042 and the second electrode 1043 located in the portion of the display region 101 for emitting light. For example, portions of the light emitting material layer 1042 and the second electrode 1043 are also formed on the top of the barrier wall 202, but these portions are separated from other portions.

For example, in some embodiments, as shown in fig. 4, the display region 101 further includes a first planarization layer 1016 disposed on a side of the first source-drain electrode 1023 and the second source-drain electrode 1024 away from the substrate 101, the first planarization layer 1016 having a first via 1016A, and the connection electrode CEL is disposed on a side of the first planarization layer 1016 away from the substrate 1011 and electrically connected to the first source-drain electrode 1023 through the first via 1016A. For example, as shown in fig. 3, the first stacked structure 202B of the barrier wall 202 includes a first insulating sub-layer 2016 disposed on the substrate base 1011, and the first insulating sub-layer 2016 is disposed on the same layer as the first planarization layer 1016.

For example, in some embodiments, as shown in fig. 4, the display region 101 may further include a first passivation layer 1019 disposed on a side of the first planarization layer 1016 away from the substrate 1011, the first passivation layer 1019 having a second via 1019A penetrating the first via 1016A, and the connection electrode CEL disposed on a side of the first passivation layer 1019 away from the substrate 1011 and electrically connected to the first source-drain electrode 1023 through the first via 1016A and the second via 1019A. For example, as shown in fig. 3, the first stacked structure 202B further includes a second insulating sublayer 2019 disposed on a side of the first insulating sublayer 2016A away from the substrate 1011, the second insulating sublayer 2019 being disposed in the same layer as the first passivation layer 1019.

For example, in some embodiments, as shown in fig. 3, the at least one barrier wall 202 includes a plurality of barrier walls 202. For example, the first metal layer structures 202A of the plurality of barrier ribs 202 are disposed at intervals on the same layer, and the first stacked structures 202B of the plurality of barrier ribs 202 are disposed on the same layer and are integrated. Therefore, the plurality of barrier ribs 202 can fully realize the function of disconnecting the functional layers such as the light emitting material layer 1042 and the second electrode 1043, and the first stacked structure 202B can be higher than the first metal layer structure 202A, so that the first metal layer structure 202A has a higher height relative to the substrate 1011.

For example, in some embodiments, as shown in fig. 6A, the first stacked structure 202B of the plurality of barrier walls 202 forms a unitary structure having barrier grooves 202D between the first metal layer structures 202A of the adjacent barrier walls 202. The isolation groove 202D is further helpful to cut off the whole functional layers such as the light emitting material layer 1042 and the second electrode 1043.

For example, in some embodiments, as shown in fig. 6A, the first insulating sublayer 2016 has a groove 2016B between the first metal layer structures 202A of adjacent barrier walls 202, and the second insulating sublayer 2019 is formed of equal thickness on a side of the first insulating sublayer 2016 remote from the substrate 1011 to form a barrier groove 202D at the groove 2016B.

For example, in some embodiments, as shown in fig. 3 and 6A, the first stacked structure 202B may further include a first metal layer 2023, and the first metal layer 2023 is disposed on a side of the first insulating sublayer 2016 near the substrate 1011. For example, the first metal layer 2023 is disposed in the same layer as the first source-drain electrode 1023 and the second source-drain electrode 1024.

For example, in some embodiments, as shown in fig. 4, the thin film transistor 102 further includes a first gate electrode 1022, the first gate electrode 1022 is disposed on a side of the first source-drain electrode 1023 and the second source-drain electrode 1024 close to the substrate 1011, the first capacitor plate 1031 of the storage capacitor 103 is disposed on a same layer as the first gate electrode 1022, and the second capacitor plate 1032 is disposed on a side of the first capacitor plate 1031 away from the substrate 1011. For example, as shown in fig. 3, the first stacked structure 202B may further include a second metal layer 2032 and a third metal layer 2031 disposed on a side of the first metal layer 2023 close to the substrate base 1011, and the second metal layer 2032 is disposed on a side of the third metal layer 2031 far from the substrate base 1011. For example, the second metal layer 2032 is disposed on the same layer as the second capacitor plate 1032, and the third metal layer 2031 is disposed on the same layer as the first capacitor plate 1031.

For example, as shown in fig. 4, the display region 101 further includes a gate insulating layer 1014B disposed between the first gate 1022 and the second capacitor plate 1032, the gate insulating layer 1014B further extending into the barrier region 201 and being disposed between the second metal layer 2032 and the third metal layer 2031, as shown in fig. 3.

For example, as shown in fig. 4, the display region 101 further includes an interlayer insulating layer 1015 disposed on a side of the second capacitor plate 1032 away from the substrate 101, and the interlayer insulating layer 1015 further extends into the barrier region 201 and is disposed on a side of the second metal layer 2032 away from the substrate 1011, as shown in fig. 3.

For example, in other embodiments, as shown in fig. 7A, the thin film transistor may further include a second gate 1025, that is, the thin film transistor is formed as a dual-gate thin film transistor, in which case, the first gate 1022 and the second gate 1025 are respectively located at two opposite sides of the active layer 1021, for example, the first gate 1022 is located at a side of the active layer 1021 close to the substrate 1011, and the second gate 1025 is located at a side of the active layer 1021 far from the substrate 1011. For example, as shown in fig. 7A, the second gate electrode 1025 is provided on the side of the interlayer insulating layer 1015 away from the substrate 1011. For example, as shown in fig. 8, the first stacked structure 202B may further include a fourth metal layer 2025 disposed between the first metal layer 2023 and the second metal layer 2032, the fourth metal layer 2025 being disposed in the same layer as the second gate 1025.

For example, as shown in fig. 7A, the display region 101 further includes another interlayer insulating layer 1020 disposed on a side of the second gate 1025 away from the substrate 101, and the interlayer insulating layer 1020 further extends into the barrier region 201 and is disposed on a side of the fourth metal layer 2025 away from the substrate 1011, as shown in fig. 8.

Thus, the first stacked structure 202B includes a stack of a plurality of insulating layers and metal layers and has a high thickness, and therefore the height of the first metal layer structure 202A provided on the first stacked structure 202B with respect to the substrate is high. For example, in the process of manufacturing the display substrate, the first recess 202C of the first metal layer structure 202A and the first electrode 1041 may be formed by using the same etching solution through the same etching process, and during etching, a photoresist pattern with a certain thickness is usually formed on the display substrate, for example, a plurality of conductive layers 4011 and insulating layers 4012 (described in detail later) that need to cover the circuit region 401, at this time, because the distance between the first metal layer structure 202A and the substrate is relatively long, the problem that the first recess 202C of the first metal layer structure 202A cannot be accurately formed due to over-thick photoresist and incomplete etching can be avoided.

For example, in some embodiments, as shown in fig. 6B, the first metal layer structures 202A of the plurality of barrier walls 202 are disposed at the same layer and at intervals, and the first stacked structures 202B of the plurality of barrier walls 202 are also disposed at the same layer and at intervals.

For example, in the embodiment of fig. 6B, the first stack structure 202B includes a plurality of sublayers disposed in the same layer as the gate insulating layer 1014A, the gate insulating layer 1014B, the interlayer insulating layer 1015, and the first planarization layer 1016.

For example, in other embodiments, as shown in fig. 6C, the first stacked structure 202B includes a plurality of sub-layers disposed in layers with the gate insulating layer 1014A, the first gate 1021, the gate insulating layer 1014B, the second capacitor plate 1032, the interlayer insulating layer 1015, the first source drain 1023, and the first planarization layer 1016.

For example, in still other embodiments, as shown in fig. 7B and 6D, the display region further includes a second passivation layer 1029 disposed on a side of the first source-drain electrode 1023 and the second source-drain electrode 1024 away from the substrate base 1011, the second passivation layer 1029 has a third via 1029A, and the connection electrode CEL is disposed on a side of the second passivation layer 1029 away from the substrate base 1011 and electrically connected to the first source-drain electrode 1023 through the third via 1029A. For example, the first planarization layer 1016 is disposed on a side of the second passivation layer 1029 away from the substrate 1011, the first via 1016A and the third via 1029A in the first planarization layer 1016 penetrate each other, and the connection electrode CEL is electrically connected to the first source-drain electrode 1023 through the first via 1016A and the third via 1029A.

For example, as shown in fig. 6D, the first stacked structure 202B includes a third insulating sub-layer 2029 disposed on the substrate 1011, and the third insulating sub-layer 2029 is disposed on the same layer as the second passivation layer 1029.

For example, as shown in fig. 6D, the barrier region includes a plurality of barrier ribs 202, the first metal layer structures 202A of the plurality of barrier ribs 202 are disposed at intervals on the same layer, and the first stacked structures 202B of the plurality of barrier ribs 202 are disposed on the same layer and are integrated. For example, the third insulating sublayer 2029 in the integral structure has a barrier groove 202D between the first metal layer structures 202A of the adjacent barrier walls 202. For example, in other embodiments, the first stacked structures 202B of the plurality of barrier walls 202 may also be disposed at the same layer and interval, so as to have a structure similar to that shown in fig. 6B or fig. 6C.

For example, in some embodiments, as shown in fig. 4, the display substrate may further include a pixel defining layer 1017 and spacers 1018. The pixel define layer 1017 is disposed on a side of the first planarizing layer 1016 away from the thin film transistor 102, the pixel define layer 1017 including a plurality of sub-pixel openings for defining a light emitting region of the light emitting device 104. Spacers 1018 are disposed on a side of the pixel definition layer 1017 away from the planarization layer 1016 to define an encapsulation space.

For example, in some embodiments, as shown in fig. 3, the blocking region 201 may further include at least one blocking wall 203, such as a plurality of blocking walls 203 (two are shown as an example), disposed on a side of the blocking wall 202 near the open region 301, the plurality of blocking walls 203 at least partially surrounding (e.g., completely surrounding) the open region 301, such as for blocking organic materials formed in the display region 101 during the manufacturing process from flowing out. For example, the blocking wall 203 includes a plurality of insulating sub-layers respectively disposed in layers with at least two of the planarization layer 1016, the pixel defining layer 1017, and the spacers 1018.

For example, as shown in fig. 3, the blocking wall 203A includes two insulating sublayers, which may be respectively disposed in one-to-one correspondence and in the same layer with two of the planarization layer 1016, the pixel defining layer 1017, and the spacer 1018. For example, the barrier wall 203B includes three insulating sublayers, which are disposed in one-to-one correspondence and in the same layer as the planarization layer 1016, the pixel defining layer 1017, and the spacer 1018, respectively. Therefore, the functional layers arranged on the same layer in the preparation process can be formed by adopting the same material layer and the same composition process, so that the preparation process of the display substrate is simplified.

For example, as shown in fig. 4, the display substrate further includes an encapsulation layer 105, and the encapsulation layer 105 includes a first inorganic encapsulation layer 1051, a first organic encapsulation layer 1052, and a second inorganic encapsulation layer 1053, which are sequentially stacked. For example, the first inorganic encapsulation layer 1051 and the second inorganic encapsulation layer 1053 may be formed on the entire surface of the display substrate, and the first organic encapsulation layer 1052 may be terminated at the barrier wall 203 due to the barrier effect of the barrier wall 203.

For example, in some embodiments, as shown in fig. 3, the blocking region 201 may further include at least one crack blocking dam 204, such as a plurality of crack blocking dams 204, disposed on a side of the blocking wall 203 near the open region 301, where the plurality of crack blocking dams 204 at least partially surround (e.g., completely surround) the open region 301, for example, to prevent cracks from forming and extending toward the display region 101 when the open region 301 is formed by a stamping or cutting process during a manufacturing process, thereby protecting the display substrate.

For example, as shown in fig. 3, the crack stop dam 204 includes a second metal layer structure 204A and a second stacked structure 204B, the second metal layer structure 204A being disposed in a same layer as the first metal layer structure 202A and having substantially the same structure, and the second stacked structure 204B including a plurality of metal sub-layers disposed in a same layer as the first gate 1022 and the second capacitor plate 1032, respectively, for example, or, in other embodiments, in a same layer as at least two of the first gate 1022, the second capacitor plate 1032, and the second gate 1025, respectively, as shown in fig. 8.

For example, in some embodiments, as shown in fig. 2 and 3, the display substrate further includes a circuit region 401 disposed between the display region 101 and the barrier region 201 and at least partially surrounding the display region 101, the circuit region 401 including a plurality of conductive layers 4011 and a plurality of insulating layers 4012 respectively located between adjacent conductive layers 4011. For example, circuit region 401 further includes conductive layer 4011A, and conductive layer 4011A is provided in the same layer as connection electrode CEL and first metal layer structure 202A, but the sidewall of conductive layer 4011A has no recess but has a sidewall structure that is flush.

For example, a transparent metal oxide such as ITO or IZO, or a metal material such as copper, aluminum, or molybdenum, or an alloy material may be used for the conductive layers 4011, and an organic insulating material such as polyimide or resin may be used for the insulating layers 4012. For example, the circuit pattern formed by the plurality of conductive layers 4011 may be a circuit pattern for providing a display signal, such as a scan signal or a data signal, to the display region 101, or a circuit pattern for providing a driving signal to the image sensor/infrared sensor 501 formed in the opening region 301, and embodiments of the present disclosure do not limit the specific form of the plurality of conductive layers 4011.

For example, the entirety of the plurality of conductive layers 4011 and the plurality of insulating layers 4012 has a relatively high thickness, and the entirety of the plurality of conductive layers 4011 and the plurality of insulating layers 4012 needs to be covered and protected by a photoresist when the first metal layer structure 202A of the barrier wall 202 is formed by etching. In the embodiment of the disclosure, by disposing the first stacked structure 202B under the first metal layer structure 202A, the first metal layer structure 202A can also be located at a higher position, so that the photoresist on the first metal layer structure 202A is not too thick to be accurately etched, thereby facilitating the formation of the first recess of the subsequent first metal layer structure 202A.

For example, in some embodiments, as shown in fig. 3, the display substrate may further include an image sensor and/or an infrared sensor 501, the image sensor and/or the infrared sensor 501 is coupled to the substrate 1011 and is coupled to the non-display side of the display substrate, and a front projection on the substrate 1011 at least partially overlaps the open area 301. Thus, the image sensor and/or the infrared sensor 501 may perform various functions such as photographing, face recognition, infrared sensing, etc. through the opening area 301.

In the embodiment of the present disclosure, the display substrate may be a flexible display substrate, in which case, the substrate 1011 may be a flexible substrate such as Polyimide (PI), or the display substrate may also be a rigid substrate, in which case, the substrate 1011 may be a rigid substrate such as glass or quartz.

For example, a barrier layer 1012 and a buffer layer 1013 may also be provided on the substrate base 1011. For example, the barrier layer 1012 and the buffer layer 1013 may be formed on the entire surface of the substrate 1011, and the barrier layer 1012 and the buffer layer 1013 are not shown in fig. 3, 6A, 8, and the like for clarity and simplicity of illustration. For example, the barrier layer 1012 may be formed of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and the barrier layer 1012 may prevent impurities such as water and oxygen from penetrating from the substrate 1011 into the functional structure such as the thin film transistor 102. For example, the buffer layer 1013 may be formed using an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. Buffer layer 1013 may provide a flat surface to facilitate the placement of other functional layers of the display substrate. The barrier layer 1012 and the buffer layer 1013 may together provide protection for other functional structures on the substrate base 1011.

For example, the materials of the first gate 1022, the second gate 1025, the first capacitor plate 1031, and the second capacitor plate 1032 may include metals such as aluminum, titanium, copper, and cobalt, or alloy materials, and may be formed in a single-layer metal structure or a multi-layer metal structure, such as a three-layer metal layer structure of titanium/aluminum/titanium, molybdenum/aluminum/molybdenum, titanium/copper/titanium, or molybdenum/copper/molybdenum. The active layer 1021 may be made of polysilicon, metal oxide, or the like, the other gate insulating layer 1014A is provided on the active layer 1021, and the gate insulating layer 1014A, the gate insulating layer 1014B, and the interlayer insulating layer 1015 may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

For example, the connection electrode CEL is further provided with a second planarization layer PL having a third via hole therein, and the first electrode 1041 is electrically connected to the connection electrode CEL through the third via hole. For example, the materials of the first planarizing layer 1016, the second planarizing layer PL, the pixel defining layer 1017, the spacers 1018, and the first organic encapsulation layer 1052 may be polyimide, epoxy, or other organic insulating materials. The first inorganic encapsulating layer 1051 and the second inorganic encapsulating layer 1053 may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

For example, the material of the first electrode 1041 includes a metal oxide such as ITO or IZO, or a metal such as Ag, Al, or Mo, or an alloy thereof. The material of the organic light emitting layer in the light emitting material layer 1042 can be selected to emit light of a certain color (e.g., red, blue, or green). The material of the second electrode 1043 may include metal such as Mg, Ca, Li, or Al, or an alloy thereof, or metal oxide such as IZO, ZTO, or an organic material having conductive properties such as PEDOT/PSS (poly 3, 4-ethylenedioxythiophene/polystyrene sulfonate).

The material of each functional layer is not limited to the above examples, and the material of each functional layer is not limited to the above examples.

At least one embodiment of the present disclosure further provides a display device, which includes the display substrate provided in the embodiment of the present disclosure. For example, the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator, which is not limited in this respect.

At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate, including: and forming a display area, a barrier area and an open area, wherein the display area and the barrier area surround the open area, and the barrier area is positioned between the display area and the open area. Forming the barrier region includes: forming at least one barrier wall at least partially surrounding the open region, each of the at least one barrier wall comprising a first metal layer structure and a first laminated structure, the first metal layer structure being formed on a side of the first laminated structure remote from the substrate base plate, at least one side of the first metal layer structure surrounding the open region having a first recess; the forming of the display area includes: forming a plurality of sub-pixels, each of the plurality of sub-pixels including a pixel driving circuit and a light emitting device, the pixel driving circuit including a thin film transistor and a connection electrode, the thin film transistor including a first source-drain electrode and a second source-drain electrode, the light emitting device including a first electrode, a second electrode and a light emitting material layer between the first electrode and the second electrode, the connection electrode being formed to electrically connect the first electrode and the first source-drain electrode. For example, the first metal layer structure and the connection electrode are formed in the same layer.

For example, in some embodiments, the first metal layer structure includes a first metal sub-layer and a second metal sub-layer formed on a side of the first metal sub-layer away from the substrate base plate, and in a direction parallel to the plate surface of the substrate base plate, the first metal sub-layer is formed to be retracted relative to the second metal sub-layer to form a first recess, refer to fig. 5A; or, the first metal layer structure includes a first metal sublayer, a second metal sublayer formed on a side of the first metal sublayer far from the substrate base plate, and a third metal sublayer formed on a side of the first metal sublayer near the substrate base plate, and in a direction parallel to the plate surface of the substrate base plate, the first metal sublayer is formed to be retracted relative to the second metal sublayer and the third metal sublayer to form a first recess, referring to fig. 5B.

Next, a method for manufacturing a display substrate provided in an embodiment of the present disclosure is exemplarily described with reference to fig. 9A to 11B, and for example, the method for manufacturing the display substrate is described by taking the display substrate illustrated in fig. 3 and 4 as an example.

As shown in fig. 9A, first, a substrate 1011 is provided, for example, when the display substrate is a flexible display substrate, the substrate 1011 provided may be a flexible substrate such as Polyimide (PI), and when the display substrate is a rigid substrate, the substrate 1011 may be a rigid substrate such as glass or quartz.

As shown in fig. 9A, first, functional layers for the display region 101, the barrier region 201, and the circuit region 401 are formed on the substrate base substrate 1011, and positions are reserved for the opening region 301, so that after the functional layers for the display region 101, the barrier region 201, and the circuit region 401 are formed, the opening region 301 is formed by, for example, punching or cutting.

For example, the barrier layer 1012 and the buffer layer 1013 may be formed in this order on the substrate base 1011 by deposition or the like. For example, the barrier layer 1012 and the buffer layer 1013 may be formed entirely on the substrate 1011. For example, the barrier layer 1012 may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and the buffer layer 1013 may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

For example, after the formation of the barrier layer 1012 and the buffer layer 1013, as shown in fig. 9A, the structures of the thin film transistor 102, the storage capacitor 103, and the first planarizing layer 1016 are formed in the display region 101, and as shown in fig. 9B, the first stacked structure 202B of the barrier wall 202 and the second stacked structure 204B of the crack stop dam 204 are formed in the barrier region 201. These structures may be formed using a patterning process, for example, a single patterning process including formation of a photoresist, exposure, development, and etching.

For example, as shown in fig. 9A and 9B, an active layer 1021 is formed on a substrate 1011 using a patterning process; a gate insulating layer 1014A is formed on the active layer 1021 by deposition or the like; simultaneously forming a first gate 1022, a first capacitor plate 1031, a third metal layer 2031 of the first stacked structure and a metal sublayer 2041 of the second stacked structure on the gate insulating layer 1014A by adopting a patterning process; then, a gate insulating layer 1014B is formed by, for example, deposition; then, a patterning process is adopted to simultaneously form a second capacitor plate 1032, a second metal layer 2032 of the first stacked structure 202B, and a metal sub-layer 2042 of the second stacked structure 204B; then, an interlayer insulating layer 1015 is formed by deposition or the like, and a via hole exposing the active layer 1021 is formed in the gate insulating layers 1014A and 1014B and the interlayer insulating layer 1015.

For example, the materials of the first gate 1022, the first capacitor plate 1031, the third metal layer 2031 of the first stacked structure 202B, and the metal sub-layer 2041 in the second stacked structure 204B include metals such as aluminum, titanium, and cobalt, or alloy materials. During the preparation, a gate material layer is formed by sputtering or evaporation, and then a patterning process is performed on the gate material layer to form the patterned gate 211, the first plate 1031, the second metal layer 2032 of the first stacked structure 202B, and the metal sub-layer 2041 in the second stacked structure 204B. The formation of other structures formed in the same layer is similar, and thus will not be described again.

For example, the active layer 1021 may be made of polysilicon, metal oxide, or other materials, the gate insulating layers 1014A and 1014B may be made of silicon oxide, silicon nitride, or silicon oxynitride, or other inorganic insulating materials, the second capacitor plate 1032, the second metal layer 2032 of the first stacked structure 202B, and the metal sub-layer 2042 of the second stacked structure 204B may be made of aluminum, titanium, cobalt, or other metals or alloy materials, and the interlayer insulating layer 1015 may be made of silicon oxide, silicon nitride, or silicon oxynitride, or other inorganic insulating materials. The material of each functional layer is not limited to the above examples, and the material of each functional layer is not limited to the above examples.

As shown in fig. 9A, after the formation of the via holes in the gate insulating layers 1014A/1014B and the interlayer insulating layer 1015, the first source drain 1023 and the second source drain 1024 as well as the first metal layer 2023 of the first stacked structure 202B of the barrier wall 202 are formed.

For example, the first source drain 1023 and the second source drain 1024 may be formed as a multi-layer metal structure, such as a three-layer metal layer structure. For example, in one example, a titanium material layer, an aluminum material layer, and a titanium material layer may be sequentially formed by sputtering or evaporation, and then the three material layers may be patterned by the same patterning process, so as to form a titanium/aluminum/titanium three-layer metal structure constituting the first source drain 1023 and the second source drain 1024. For clarity and brevity, the three-layer metal layer structure is not shown in some of the figures.

For example, as shown in fig. 9A and 9B, a first planarization layer 1016 and a first insulating sub-layer 2016 of a first stacked structure for a barrier wall are formed on the side of the first source-drain electrode 1023 and the second source-drain electrode 1024 away from the substrate 1011, for example, by a patterning process, and a groove 2016B is formed in the first insulating sub-layer 2016. For example, at the same time as the first planarizing layer 1016 is formed, an insulating sublayer 203A1 of the blocking wall 203A and an insulating sublayer 203B1 of the blocking wall 203B are formed.

As shown in fig. 10A and 10B, a first passivation layer 1019 and a second insulating sub-layer 2019 are formed in the same layer on the first planarization layer 1016 and the first insulating sub-layer 2016. For example, a first passivation layer 1019 is formed on the first planarization layer 1016, and a penetrating second via 1019A and a first via 1016A exposing the first source and drain electrodes 1023 are formed in the first passivation layer 1019 and the first planarization layer 1016, at which time, a second insulating sub-layer 2019 is formed, for example, with a uniform thickness on the first insulating sub-layer 2016 of the first stack structure 202B of the barrier wall, and a barrier groove 202D is formed at the position of the groove 2016B.

For example, in some embodiments, the display substrate has a plurality of barrier ribs 202, and the first stacked structure 202B of the plurality of barrier ribs 202 is formed on the same layer and as a unitary structure that forms the barrier recess 202D between adjacent first metal layer structures.

For example, in other embodiments, corresponding to the structures shown in fig. 6D and 7B, a second passivation layer 1029 is formed on the first source-drain electrode 1023 and the side of the second source-drain electrode 1024 away from the substrate 1011, the second passivation layer 1029 has a third via 1029A, a first planarization layer 1016 is formed on the side of the second passivation layer 1029 away from the substrate 1011, a first via 1016A penetrating the third via 1029A is formed in the first planarization layer 1016, and the connection electrode CEL is formed on the side of the second passivation layer 1029 away from the substrate 1011, more specifically on the side of the first planarization layer 1016 away from the substrate 1011, and is electrically connected to the first source-drain electrode 1023 through the third via 1029A and the first via 1016A. For example, the third insulating sub-layer 2029 of the first stack structure 202B is formed in the same layer while forming the second passivation layer 1029, and a barrier groove 202D is formed in the third insulating sub-layer 2029, as shown in fig. 6D.

For example, as shown in fig. 10A and 10B, a connection electrode material layer is formed on the first passivation layer 1019 by, for example, sputtering or deposition, and then patterned to form a connection electrode CEL and a first metal layer initial structure 201A0, for example, a second metal layer initial structure 2040 of the crack stop dam 204 and a conductive layer 4011A located in the circuit region 401 are also formed at the same time. At this time, the first metal layer initial structure 201A0, the second metal layer initial structure 2040, and the conductive layer 4011A in the circuit region 401 have a structure in which the sidewalls are flush.

For example, the first metal layer initial structures 201a0 of the plurality of barrier walls 202 are formed at the same layer and interval, so that the finally formed first metal layer structures 202A of the plurality of barrier walls 202 are formed at the same layer and interval. For example, the second metal layer initiation structures 2040 of the plurality of crack stop dams 204 are also formed in layers and spaced apart.

For example, as shown in fig. 11A and 11B, a second planarization layer PL is formed on the connection electrode CEL and the side of the first metal layer preliminary structure 201A0 away from the substrate 1011, the second planarization layer PL including a third via PLH exposing the connection electrode CEL and an opening PLO exposing the first metal layer preliminary structure 201A 0; a first electrode material layer 10410 is formed on a side of the second planarization layer PL away from the substrate base plate 1011, the first electrode material layer 10410 and the first metal layer initial structure 202A0 are etched by using the same etching solution to form a first electrode 1041 and a first notch 202C, for example, a second notch 204C in the second metal layer structure is also formed at the same time, and the first electrode 1041 is electrically connected to the electrode CEL through the third via PLH, as shown in fig. 12A and 12B.

For example, the etching solution used above has an etching effect on the intermediate layer of the first metal layer structure 202A and the second metal layer structure 204A or the etching rate on the intermediate layer is greater than that on other layers, so that the etching process can form the recess in the first metal layer structure 202A and the second metal layer structure 204A.

For example, in some embodiments, a circuit region 401 is further formed on the display substrate, for example, the circuit region 401 is formed between the display region 101 and the barrier region 201 and at least partially surrounds the display region 101, and the circuit region 401 includes a plurality of conductive layers 4011 and a plurality of insulating layers 4012 located between adjacent conductive layers 4011; for example, after the connection electrode CEL and the first metal layer initial structure 202a0 are formed, a plurality of conductive layers 4011 and a plurality of insulating layers 4012 located between adjacent conductive layers are formed, and then the first electrode material layer 10410 and the first metal layer initial structure 202a0 are etched using the same etching solution.

For example, the entirety of the plurality of conductive layers 4011 and the plurality of insulating layers 4012 has a relatively high thickness, and when the first metal layer structure 202A of the barrier wall 202 is formed by etching, the entirety of the plurality of conductive layers 4011 and the plurality of insulating layers 4012 needs to be covered and protected by a photoresist, for example, the coating range of the photoresist is shown by a dashed box in fig. 12B. In the embodiment of the disclosure, by disposing the first stacked structure 202B under the first metal layer structure 202A, the first metal layer structure 202A can also be located at a higher position, so that the photoresist on the first metal layer structure 202A is not too thick to be accurately etched, thereby facilitating the formation of the first recess 202C of the subsequent first metal layer structure 202A.

For example, after the first electrode 1041 is formed, the pixel defining layer 1017, the spacers 1018, the light emitting material layer 1042, the second electrode 1043, the encapsulation layer 105, and the like are sequentially formed, and other insulating sub-layers of the barrier walls 203 are formed at the same time, as shown in fig. 13A and 13B.

For example, the pixel defining layer 1017 and the insulating sub-layer 203A2 of the banks 203A and the insulating sub-layer 203B2 of the banks 203B are formed at the same layer through a patterning process. The pixel defining layer 1017 has a sub-pixel opening therein to expose the first electrode 1041, so as to form a light emitting material layer 1042 and a second electrode 1043 of the light emitting device. For example, the material of the pixel defining layer 1017 may include polyimide, epoxy, or other organic insulating materials.

For example, the spacers 1018 and the insulating sub-layer 203B3 of the blocking wall 203B are formed in the same layer by a patterning process. The material of the spacer 1018 includes an organic insulating material such as polyimide, epoxy resin, or the like.

For example, the light-emitting material layer 1042 may be formed in the sub-pixel opening of the pixel defining layer 1017 by inkjet printing, evaporation, or the like, and then the second electrode 1043 may be formed by sputtering or the like, for example. For example, the light emitting material layer 1042 and the second electrode 1043 are formed on the entire surface of the display substrate and are disconnected at the barrier walls 202 and the crack barrier dam 204.

For example, the material of the light-emitting material layer 1042 may be selected to be an organic light-emitting material capable of emitting light of a certain color (e.g., red light, blue light, green light, etc.) according to requirements. The material of the second electrode 1043 may include metal such as Mg, Ca, Li, or Al, or an alloy thereof, or metal oxide such as IZO, ZTO, or an organic material having conductive properties such as PEDOT/PSS (poly 3, 4-ethylenedioxythiophene/polystyrene sulfonate).

For example, after the light emitting device 104 is formed, the encapsulation layer 105 is formed. For example, encapsulation layer 105 includes a first inorganic encapsulation layer 1051, a first organic encapsulation layer 1052, and a second inorganic encapsulation layer 1053. For example, the first inorganic encapsulation layer 1051 and the second inorganic encapsulation layer 1053 are formed by deposition or the like. The first organic encapsulation layer 1052 is formed by inkjet printing. For example, the first organic encapsulation layer 1052 may terminate at the interception wall 203 due to the interception function of the interception wall 203.

For example, the first inorganic encapsulating layer 1051 and the second inorganic encapsulating layer 1053 may be formed using an inorganic material such as silicon nitride, silicon oxide, or silicon oxynitride, and the first organic encapsulating layer 1052 may be formed using an organic material such as Polyimide (PI) or epoxy. Thus, the first inorganic encapsulation layer 1051, the first organic encapsulation layer 1052 and the second inorganic encapsulation layer 1053 are formed as a composite encapsulation layer, thereby having a better encapsulation effect.

For example, after the display region 101 is formed, the opening region 301 may be formed by laser cutting or mechanical punching. The opening area 301 penetrates through the substrate 1011, and an image sensor, an infrared sensor and other structures can be mounted at the opening area 301 and connected with a signal such as a central processing unit. For example, the image sensor or the infrared sensor may be disposed on a side of the substrate 1011 away from the light emitting device (i.e., a non-display side of the display substrate), and may perform various functions such as photographing, face recognition, infrared sensing, and the like through the opening area 301.

For example, after the opening region 301 is formed, a polarizer, a cover plate, and other structures may be formed on the display substrate, which is not limited in this disclosure.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) For purposes of clarity, the thickness of layers or regions in the figures used to describe embodiments of the present disclosure are exaggerated or reduced, i.e., the figures are not drawn on a true scale. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

(3) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be determined by the scope of the claims.

Claims (17)

1. A display substrate having a display region, a barrier region and an open region, and comprising a substrate, wherein the display region and the barrier region surround the open region, the barrier region is located between the display region and the open region,

the barrier region comprises at least one barrier wall at least partially surrounding the opening region, each of the at least one barrier wall comprises a first metal layer structure and a first laminated structure, the first metal layer structure is positioned on one side of the first laminated structure far away from the substrate base plate, and at least one side of the first metal layer structure surrounding the opening region is provided with a first notch;

the display area comprises a plurality of sub-pixels, each of the plurality of sub-pixels comprises a pixel driving circuit and a light-emitting device, the pixel driving circuit comprises a thin film transistor and a connecting electrode, the thin film transistor comprises a first source drain electrode and a second source drain electrode, the light-emitting device comprises a first electrode, a second electrode and a light-emitting material layer between the first electrode and the second electrode, and the connecting electrode is configured to be electrically connected with the first electrode and the first source drain electrode;

the first metal layer structure and the connecting electrode are arranged on the same layer.

2. The display substrate according to claim 1, wherein the first metal layer structure comprises a first metal sub-layer and a second metal sub-layer disposed on a side of the first metal sub-layer away from the substrate, and in a direction parallel to a plane of the substrate, the first metal sub-layer is retracted relative to the second metal sub-layer to form the first notch; or

The first metal layer structure comprises a first metal sublayer, a second metal sublayer and a third metal sublayer, wherein the second metal sublayer is arranged on one side, far away from the substrate base plate, of the first metal sublayer, the third metal sublayer is arranged on one side, close to the substrate base plate, of the first metal sublayer, and the first metal sublayer is retracted relative to the second metal sublayer and the third metal sublayer in the direction parallel to the plate surface of the substrate base plate so as to form the first notch.

3. The display substrate according to claim 1, wherein the display region further comprises a first planarization layer disposed on a side of the first source/drain electrode and the second source/drain electrode away from the substrate, the first planarization layer having a first via hole, the connection electrode disposed on a side of the first planarization layer away from the substrate and electrically connected to the first source/drain electrode through the first via hole,

the first stack structure includes a first insulating sub-layer disposed on the base substrate,

the first insulating sublayer and the first planarization layer are arranged on the same layer.

4. The display substrate of claim 3, wherein the at least one barrier wall comprises a plurality of barrier walls;

the first metal layer structures of the multiple barrier walls are arranged at intervals on the same layer, and the first laminated structures of the multiple barrier walls are arranged at intervals on the same layer; or

The first metal layer structures of the multiple barrier walls are arranged on the same layer at intervals, and the first laminated structures of the multiple barrier walls are arranged on the same layer and are of an integral structure.

5. The display substrate of claim 4, wherein the integrated structure has barrier grooves between the first metal layer structures of adjacent barrier walls.

6. The display substrate of claim 5, wherein the display region further comprises a first passivation layer disposed on a side of the first planarization layer away from the substrate base plate, the first passivation layer having a second via penetrating the first via, the connection electrode disposed on a side of the first passivation layer away from the substrate base plate and electrically connected to the first source/drain electrode through the first via and the second via,

the first stack structure further comprises a second insulating sub-layer arranged on a side of the first insulating sub-layer remote from the substrate base plate,

the second insulating sublayer and the first passivation layer are arranged on the same layer.

7. The display substrate of claim 6, wherein the first insulating sub-layer has a groove between the first metal layer structures of the adjacent barrier walls, and the second insulating sub-layer is formed with equal thickness on a side of the first insulating sub-layer away from the substrate to form a barrier groove at the groove.

8. The display substrate according to claim 1, wherein the display region further comprises a second passivation layer disposed on a side of the first and second source/drain electrodes away from the substrate, the second passivation layer having a third via hole, the connection electrode being disposed on a side of the second passivation layer away from the substrate and electrically connected to the first source/drain electrode through the third via hole,

the first stack structure includes a third insulating sub-layer disposed on the substrate base plate,

the third insulating sublayer and the second passivation layer are arranged on the same layer.

9. The display substrate of claim 8, wherein the at least one barrier wall comprises a plurality of barrier walls;

the first metal layer structures of the multiple barrier walls are arranged at intervals on the same layer, and the first laminated structures of the multiple barrier walls are arranged at intervals on the same layer; or

The first metal layer structures of the multiple barrier walls are arranged on the same layer at intervals, and the first laminated structures of the multiple barrier walls are arranged on the same layer and are of an integral structure.

10. The display substrate of claim 9, wherein the third insulating sub-layer in the integrated structure has barrier grooves between the first metal layer structures of adjacent barrier walls.

11. The display substrate according to claim 3, wherein the first stacked structure further comprises a first metal layer disposed on a side of the first insulating sub-layer adjacent to the substrate,

the first metal layer is arranged on the same layer as the first source/drain electrode and the second source/drain electrode.

12. The display substrate according to claim 8 or 11, wherein the pixel driving circuit further comprises a storage capacitor, the thin film transistor further comprises a first gate disposed on a side of the first source-drain electrode and the second source-drain electrode close to the substrate,

the storage capacitor comprises a first capacitor polar plate and a second capacitor polar plate, the first capacitor polar plate and the first grid electrode are arranged on the same layer, the second capacitor polar plate is arranged on one side of the first capacitor polar plate far away from the substrate base plate,

the first laminated structure further comprises a second metal layer and a third metal layer, the second metal layer is arranged on one side of the third metal layer far away from the substrate base plate,

the second metal layer and the second capacitor plate are arranged on the same layer, and the third metal layer and the first capacitor plate are arranged on the same layer.

13. The display substrate of claim 12, wherein the display region further comprises a gate insulating layer disposed between the first gate electrode and the second capacitor plate, the gate insulating layer further extending into the barrier region and disposed between the second metal layer and the third metal layer.

14. The display substrate of claim 12, wherein the display region further comprises an interlayer insulating layer disposed on a side of the second capacitor plate away from the substrate, the interlayer insulating layer further extending into the blocking region and disposed on a side of the second metal layer away from the substrate.

15. The display substrate according to claim 14, wherein the thin film transistor further comprises a second gate electrode provided on a side of the interlayer insulating layer away from the base substrate,

the first laminated structure further comprises a fourth metal layer, and the fourth metal layer and the second grid electrode are arranged on the same layer.

16. The display substrate according to claim 1 or 2, further comprising: a circuit region disposed between the display region and the blocking region and at least partially surrounding the display region,

the circuit region includes a plurality of conductive layers and a plurality of insulating layers between adjacent conductive layers.

17. A display device comprising the display substrate according to any one of claims 1 to 16.

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