CN216649324U

CN216649324U - High-real-time modular converter control system

Info

Publication number: CN216649324U
Application number: CN202122902406.7U
Authority: CN
Inventors: 袁凯南; 崔壮平; 荀庆来; 罗志斌
Original assignee: China Machinery International Engineering Design and Research Institute Co Ltd
Current assignee: China Machinery International Engineering Design and Research Institute Co Ltd
Priority date: 2021-11-23
Filing date: 2021-11-23
Publication date: 2022-05-31
Anticipated expiration: 2031-11-23

Abstract

The utility model discloses a high-real-time modular converter control system, wherein a real-time communication network topology of the whole modular converter system adopts a star-shaped structure taking a main controller module as a core, a plurality of power unit modules are directly in communication connection with the main controller module, the step-by-step forwarding and transparent transmission links of the existing series topology structure are reduced, each power unit module is directly in real-time communication with the main controller module, the data transmission efficiency is brought into play to the utmost extent, and the real-time synchronism of the whole converter system is greatly improved. On the basis, an optical fiber communication link is additionally designed, the main controller module and each power unit module are connected in series in a ring mode and are specially used for fault chain protection of each module, only hundreds of nanoseconds are needed from the moment of fault occurrence to the moment that all the modules receive fault signals, and the reliability and timeliness of the fault protection action of the whole converter system are greatly improved.

Description

High-real-time modular converter control system

Technical Field

The utility model relates to the technical field of converters, in particular to a modular converter control system with high real-time performance.

Background

In the prior art, when designing some large-scale converter systems with high power or high voltage, due to the limitations of small power and low voltage-withstanding grade of a single power device, a topological structure design of modular multi-power units is usually adopted in the industry, that is, power devices in a plurality of power unit modules are connected in a series, parallel or series-parallel combination manner to meet the output requirement of high current or high voltage. In recent years, as the real-time performance requirement of users on large-scale converter systems is continuously increased, the control period is required to be shortened as much as possible during design so as to improve the response speed of the systems. In order to improve the real-time performance of the whole converter system, the real-time synchronous communication control among all the power unit modules becomes important, and the quality of a real-time synchronous communication control mechanism directly determines the system response speed of the whole converter. However, in the existing large-scale converter system, a plurality of modular multi-power units are connected in series or in series-parallel, so that real-time synchronism among all power unit modules is poor.

In addition, as a set of large-scale converter system with excellent real-time performance, a set of complete protection mechanism is indispensable, and in the application of the large-scale converter, if the protection action is not timely, the load equipment and the converter equipment can be damaged or even destroyed, and under the most serious condition, casualties can be caused, so the timely response of the protection action is particularly important. The common practice in the industry at present is that after a fault occurs, a power unit transmits a data frame containing a fault state word to a main controller module through a real-time synchronous communication link, and after receiving the fault state word, the main controller analyzes the data frame, takes a protective measure, and then transmits the data frame containing a protective control instruction to the power unit. The fault information is sent out from the power unit with the fault until all the power unit modules receive the protection instruction and complete the protection action, the whole protection process takes longer time, and at least the cost is dozens of us to dozens of us.

SUMMERY OF THE UTILITY MODEL

The utility model provides a high-instantaneity modular converter control system, which aims to solve the technical problem that real-time synchronism among a plurality of power unit modules is poor in the existing converter system.

According to one aspect of the utility model, a high-real-time modular converter control system is provided, which comprises a main controller module and a plurality of power unit modules, wherein a real-time communication network topology of the whole modular converter system adopts a star-shaped structure with the main controller module as a core, and the plurality of power unit modules are directly in communication connection with the main controller module.

Furthermore, the communication transmission medium between the power unit module and the main controller module adopts optical fibers, the main controller module and the power unit module both comprise an optical fiber converter, an FPGA/CPLD and an MCU/DSP, the FPGA/CPLD is respectively connected with the optical fiber converter and the MCU/DSP, the optical fiber converter is used for converting electric signals and optical signals, the FPGA/CPLD is used as a serial communication transceiver, and the MCU/DSP is used for processing signals.

Furthermore, the power unit module further comprises an analog signal conditioning circuit, a hardware protection circuit and an IGBT driving module, wherein the input end of the analog signal conditioning circuit is connected with the sensor, the output end of the analog signal conditioning circuit is respectively connected with an ADC pin of the MCU/DSP and the input end of the hardware protection circuit, the output end of the hardware protection circuit is connected with the FPGA/CPLD, the FPGA/CPLD is also connected with the IGBT driving module, the analog signal conditioning circuit is used for conditioning analog quantity signals collected by the sensor into standard signals and respectively transmitting the standard signals to the MCU/DSP and the hardware protection circuit, the MCU/DSP is used for locking PWM pulse signals sent by an internal pulse generator and sending protection action signals to the FPGA/CPLD when the detection value of the sensor exceeds a preset protection threshold value, and the hardware protection circuit outputs signals which are overturned when the detection value of the sensor exceeds the preset protection threshold value, the IGBT driving module is used for driving an IGBT to conduct and operate, and the FPGA/CPLD is used for controlling the IGBT driving module to stop driving the IGBT to operate when receiving a protection action signal transmitted by the MCU/DSP or turning over an output signal of the hardware protection circuit, so that the power unit module is protected.

Furthermore, the hardware protection circuit comprises a digital potentiometer and a comparator, wherein the digital potentiometer is connected with one input end of the comparator, the other input end of the comparator is connected with the sensor, the output end of the comparator is connected with the FPGA/CPLD, the digital potentiometer is used for providing reference voltage for the comparator, and the comparator outputs signals to be overturned when analog quantity signals exceed the reference voltage.

Further, the sensors comprise a temperature sensor for collecting the temperature of the IGBT, a current sensor for collecting the output current of the power unit module and a voltage sensor for collecting the bus voltage.

Furthermore, the power unit module includes two hardware protection circuits, wherein an input terminal of one of the hardware protection circuits is connected to the current sensor, and an input terminal of the other hardware protection circuit is connected to the voltage sensor.

Further, the MCU/DSP is connected with the digital potentiometer through an SPI interface or an IIC communication interface of the MCU/DSP, and the MCU/DSP is also used for adjusting the potential of the digital potentiometer so as to adjust the reference voltage of the comparator.

Furthermore, the digital potentiometer is provided with a nonvolatile memory for storing the potential parameters output by the MCU/DSP.

Furthermore, the FPGA/CPLD is provided with an interlock protection input port and an interlock protection output port, in the FPGA/CPLD of the main controller module and the plurality of power unit modules, the interlock protection output port of one FPGA/CPLD is connected to the interlock protection input port of another FPGA/CPLD, the plurality of FPGA/CPLDs are sequentially connected in series to form an interlock protection loop, any one power unit module generates a protection action, and the other power unit modules generate a protection action one by one along the loop.

Furthermore, only high and low level signals are transmitted in the chain protection loop, when all the power unit modules work normally, high level signals are transmitted in the chain protection loop, and when at least one power unit module performs a protection action, low level signals are transmitted in the chain protection loop.

The utility model has the following effects:

according to the high-real-time modular converter control system, the network topology of the whole modular converter system adopts a star-shaped structure with the main controller module as a core, the plurality of power unit modules are directly in communication connection with the main controller module, the step-by-step forwarding and transparent transmission links of the existing series topology structure are reduced, each power unit module is directly in real-time communication with the main controller module, the data transmission efficiency is brought into play to the utmost extent, and the real-time synchronism of the whole converter system is greatly improved.

In addition, an annular interlocking protection link is additionally designed, the main controller module and each power unit module are connected in series in an annular mode and are specially used for fault interlocking protection of each module, only hundreds of nanoseconds are needed from the moment of fault occurrence to the moment that all modules receive fault signals, and the reliability and timeliness of fault protection actions of the whole converter system are greatly improved.

In addition to the objects, features and advantages described above, other objects, features and advantages of the present invention are also provided. The present invention will be described in further detail below with reference to the drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the utility model and, together with the description, serve to explain the utility model and not to limit the utility model. In the drawings:

fig. 1 is a schematic diagram of a topology of a modular converter control system with high real-time performance according to a preferred embodiment of the present invention.

Fig. 2 is a schematic diagram of a real-time communication topology of a high real-time modular converter control system according to a preferred embodiment of the present invention.

Fig. 3 is a schematic diagram illustrating the principle of serial communication transceiving between a main controller module and a plurality of power cell modules according to a preferred embodiment of the present invention.

Fig. 4 is a schematic circuit block diagram of a power cell module according to a preferred embodiment of the present invention.

Fig. 5 is a schematic diagram of an interlock protection loop of a modular converter control system with high real-time performance according to a preferred embodiment of the present invention.

Detailed Description

The embodiments of the utility model will be described in detail below with reference to the accompanying drawings, but the utility model can be embodied in many different forms, which are defined and covered by the following description.

As shown in fig. 1 and fig. 2, a preferred embodiment of the present invention provides a high real-time modular converter control system, which includes a main controller module and a plurality of power unit modules, wherein a real-time communication network topology of the entire modular converter system adopts a star-shaped structure with the main controller module as a core, and the plurality of power unit modules are directly in communication connection with the main controller module. The main controller module is responsible for the core control function of the whole converter system, for example, issuing control data to each power unit module, and the power unit module can acquire an analog quantity signal of each control period and feed back the analog quantity signal to the main controller module, so that the main controller module adjusts the control data of the next control period based on the feedback data acquired by each power unit module in the current period. And at the beginning of each control period, the main controller module simultaneously issues control data to all the power unit modules, and the control data frame comprises a control command, the control data and the like. After each power unit module receives the control data frame, the received time node is taken as a synchronous time point of all the power unit modules, and the power device is immediately conducted according to the control instruction and the control data. The power unit module collects analog quantity signals of the current control period, such as voltage, current, temperature and the like, then sends the analog quantity data to the main controller module, and the main controller module receives the analog quantity data of all the power unit modules, obtains the control data of the next control period after calculation and waits for entering the next control period.

It can be understood that, in the high real-time modular converter control system of the embodiment, the network topology of the whole modular converter system adopts a star-shaped structure with the main controller module as a core, the plurality of power unit modules are directly in communication connection with the main controller module, so that the step-by-step forwarding and transparent transmission links of the existing series topology structure are reduced, each power unit module is directly in real-time communication with the main controller module, the data transmission efficiency is brought into play to the utmost, the real-time synchronism of the whole converter system is greatly improved, and the system response speed is high.

The communication transmission medium between the power unit module and the main controller module adopts optical fibers, the transmission mode is serial transmission, the baud rate is preferably 5 Mbps-50 Mbps, the data frame format adopts a self-defined fixed format, and the length of the data frame is fixed to be 20-30 bytes. Because the data frame adopts a fixed frame format and a fixed length, and the data receiving and sending are all in a fixed time and a fixed interval period, no additional frame head and frame tail are needed, the data volume is reduced as much as possible, and the data transmission efficiency is improved. In addition, check words can be added to the data frames to improve the reliability of the data.

It can be understood that, as shown in fig. 3, the main controller module and the power unit module both include an optical fiber converter, an FPGA/CPLD and an MCU/DSP, the FPGA/CPLD is respectively connected with the optical fiber converter and the MCU/DSP, the optical fiber converter is used for converting between electrical signals and optical signals, the FPGA/CPLD is used as a serial communication transceiver, and the MCU/DSP is used for processing signals. The FPGA/CPLD of the power unit module can convert a plurality of acquired analog quantity signals into optical signals through the optical fiber converter and then transmit the optical signals to the main controller module, and the FPGA/CPLD of the main controller module can transmit the analog quantity signals transmitted by the plurality of power unit modules to the MCU/DSP.

It can be understood that, as shown in fig. 4, the power unit module further includes an analog signal conditioning circuit, a hardware protection circuit, and an IGBT driver module, where an input end of the analog signal conditioning circuit is connected to the sensor, an output end of the analog signal conditioning circuit is connected to an ADC pin of the MCU/DSP and an input end of the hardware protection circuit, an output end of the hardware protection circuit is connected to the FPGA/CPLD, and the FPGA/CPLD is further connected to the IGBT driver module. The power unit module adopts a MCU/DSP + FPGA/CPLD dual-core control scheme, wherein the MCU/DSP is responsible for analog-to-digital conversion of analog quantity signals, adjustment of protection threshold values of a digital potentiometer, generation of PWM pulses, software protection and main control work, and the FPGA/CPLD is responsible for hardware protection real-time synchronous communication control, control of PWM pulse driving signals, acquisition of fault signals, acquisition and output of interlock protection action signals, protection fault signal latching, control output of protection logic and the like. Specifically, the analog signal conditioning circuit is configured to condition an analog quantity signal collected by the sensor into a standard signal and respectively transmit the standard signal to the MCU/DSP and the hardware protection circuit, the MCU/DSP is configured to lock a PWM pulse signal sent by an internal pulse generator of the sensor when a detection value of the sensor exceeds a preset protection threshold and send a protection action signal to the FPGA/CPLD, the hardware protection circuit turns over an output signal when the detection value of the sensor exceeds the preset protection threshold, the IGBT driving module is configured to drive the IGBT to turn on and operate, and the FPGA/CPLD is configured to control the IGBT driving module to stop driving the IGBT to operate when receiving the protection action signal transmitted by the MCU/DSP or the output signal of the hardware protection circuit turns over, so as to protect the power unit module. For example, the analog signal conditioning circuit may adopt an existing amplifying circuit, and because the signal value output by the sensor is small, the signal value cannot be directly sampled by the ADC of the MCU/DSP and converted into a digital signal, and after the signal output by the sensor is amplified into a standard signal by the analog signal conditioning circuit, the signal is sampled by the ADC of the MCU/DSP and converted into a digital signal; for another example, the IGBT driving module may adopt an existing switching circuit with an MOS transistor, and control whether the IGBT is turned on or off by controlling on/off of the MOS transistor. The IGBT is an insulated gate bipolar transistor, namely a power device of the power unit module.

Specifically, the analog signal conditioning circuit conditions the signal output by the sensor into a standard signal and then divides the standard signal into two paths which are simultaneously sent to an ADC sampling pin of the MCU/DSP and an input end of the hardware protection circuit. After the analog quantity signal is sent into the MCU/DSP, the analog quantity value is obtained through calculation, filtering processing is carried out according to a filtering strategy, then the analog quantity value is compared with a preset software protection threshold value, if the analog quantity value exceeds the software protection threshold value, the MCU/DSP locks a PWM pulse signal sent by an internal pulse generator, the IGBT driving module stops working if no PWM pulse signal is input, the IGBT is disconnected and does not run, and meanwhile, the MCU/DSP sends a protection action signal to the FPGA/CPLD through a parallel bus to inform the FPGA/CPLD of the protection action, so that the software protection function is realized. The software protection has the advantages of high protection precision, configurable filtering parameters, settable protection threshold value and the like. After the analog quantity signal is input into the hardware protection circuit, the hardware protection circuit compares the analog quantity signal with a preset threshold voltage in real time, if the analog quantity signal exceeds the preset threshold voltage, the output signal of the hardware protection circuit can be automatically turned over, for example, under normal conditions, the hardware protection circuit outputs a high level signal, and when the power unit module breaks down, the analog quantity signal exceeds the preset threshold voltage, the hardware protection circuit outputs a low level signal, so that the hardware protection function is realized. The hardware protection circuit can normally work without the intervention of the MCU/DSP during the working period, even if software in the MCU/DSP runs away or crashes, the hardware protection circuit can accurately and rapidly act, and the hardware protection has the advantages of high real-time performance of protection action, no action rejection, no misoperation and the like. And the FPGA/CPLD only needs to latch a protection fault signal and quickly lock the output of the PWM pulse signal when receiving a protection action signal transmitted by the MCU/DSP or when the output signal of the hardware protection circuit is overturned, namely, the IGBT driving module is controlled to stop driving the IGBT to operate, so that the protection effect on the power unit module is achieved.

Therefore, the power unit module of the embodiment adopts the software and hardware dual protection channel, and integrates the advantages of the software and hardware dual protection channel into a whole, so that the converter system has the advantages of high reliability of protection action, high protection precision, high response speed, configurable filtering time, settable protection threshold value and the like, and the software and hardware dual protection of protection functions such as overvoltage, overcurrent, overtemperature and the like is realized.

It is understood that the sensors include a temperature sensor for collecting the temperature of the IGBT, a current sensor for collecting the magnitude of the output current of the power cell module, and a voltage sensor for collecting the bus voltage. The power unit module comprises two hardware protection circuits, wherein the input end of one hardware protection circuit is connected with the current sensor, and the input end of the other hardware protection circuit is connected with the voltage sensor, so that a hardware overvoltage protection circuit and a hardware overcurrent protection circuit are formed.

The hardware protection circuit specifically comprises a digital potentiometer and a comparator, wherein the digital potentiometer is connected with one input end of the comparator, the other input end of the comparator is connected with a sensor, the output end of the comparator is connected with the FPGA/CPLD, the digital potentiometer is used for providing reference voltage for the comparator, namely a hardware protection threshold value, and the comparator outputs a signal to be overturned when an analog quantity signal exceeds the reference voltage. In addition, the MCU/DSP is connected with the digital potentiometer through an SPI interface or an IIC communication interface of the MCU/DSP, and the MCU/DSP is further used for adjusting the potential of the digital potentiometer so as to adjust the reference voltage of the comparator and play a role in adjusting the hardware protection threshold. Preferably, the digital potentiometer is provided with a nonvolatile memory for storing the potential parameters output by the MCU/DSP, and can normally work without the intervention of the MCU/DSP during the working period.

Optionally, the FPGA/CPLD is provided with an interlock protection input port and an interlock protection output port, in the FPGA/CPLD of the main controller module and the plurality of power unit modules, the interlock protection output port of one FPGA/CPLD is connected to the interlock protection input port of another FPGA/CPLD, the plurality of FPGA/CPLDs are sequentially connected in series to form an interlock protection loop, any one power unit module performs a protection action, and the other power unit modules perform the protection actions one by one along the loop. The FPGA/CPLD of the power unit module with the fault outputs a protection action signal at the interlock protection output port while locking the PWM pulse signal of the power unit module, the FPGA/CPLD of the power unit module connected with the FPGA/CPLD also immediately locks the PWM pulse signal output after receiving the protection action signal, and simultaneously outputs a protection action signal at the interlock protection output port, and the protection action signals are transmitted in sequence, so that an annular software and hardware interlock protection link is formed between the main controller module and the plurality of power unit modules. The chain protection loop only transmits high and low level signals, when all power unit modules work normally, the chain protection loop transmits the high level signals, and when at least one power unit module performs protection action, the chain protection loop transmits the low level signals.

For example, as shown in fig. 5, when each power unit module in the converter system normally operates without a protection action, the ring-shaped chain protection link keeps transmitting a high level, each power unit module can normally output a PWM pulse signal, and the IGBT driving module can normally drive the IGBT to operate in an on state. If the power unit module 1 is in protection action, the interlock protection output port of the FPGA/CPLD outputs a protection action signal, the output is changed from high level to low level, the FPGA/CPLD latches the protection action signal in fault, the FPGA/CPLD continuously outputs low level, and the power unit module is latched to play a role in protecting the power unit module. Since the interlock protection output port of the power unit module 1 is connected to the interlock protection input port of the power unit module 2, the power unit module 2 will also latch output and continue outputting low level at its interlock protection output port; since the interlock protection output port of the power unit module 2 is connected to the interlock protection input port of the power unit module 3, the power unit module 3 also outputs the latch and continuously outputs the low level at the interlock protection output port; and looping back the protection action signal in such a way until the protection action signal loops back to the interlocking protection input port of the power unit module 1, thereby completing the annular interlocking protection function. In order to improve the timeliness of protection action, a chain protection link uses high-speed optical fiber transmission to transmit high and low level signals only, a simple logic gate is used in an FPGA/CPLD of each power unit module to process the signals, and only hundreds of nanoseconds are needed from the moment when a certain power unit module generates protection action to the moment when all power unit modules receive the protection action signals.

In addition, once the converter system is protected in an interlocking manner, the fault states of all the power unit modules can be unlocked only by giving a fault reset instruction through the main controller module on the premise that all the power unit modules are restored to be normal, at the moment, the level in the annular interlocking protection link is changed into a normal high level, and all the power unit modules enter a Ready state again to run normally.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. The modularized converter control system with high real-time performance is characterized by comprising a main controller module and a plurality of power unit modules, wherein a real-time communication network topology of the whole modularized converter system adopts a star-shaped structure with the main controller module as a core, and the plurality of power unit modules are directly in communication connection with the main controller module.

2. The high-real-time modular converter control system of claim 1, wherein the communication transmission medium between the power unit module and the main controller module is made of optical fiber, the main controller module and the power unit module each include an optical fiber converter, an FPGA/CPLD, and an MCU/DSP, the FPGA/CPLD is connected to the optical fiber converter and the MCU/DSP, respectively, the optical fiber converter is used for converting between electrical signals and optical signals, the FPGA/CPLD is used as a serial communication transceiver, and the MCU/DSP is used for processing signals.

3. The high real-time modular converter control system of claim 2, wherein the power unit module further comprises an analog signal conditioning circuit, a hardware protection circuit and an IGBT driving module, the input end of the analog signal conditioning circuit is connected to the sensor, the output end of the analog signal conditioning circuit is connected to the ADC pin of the MCU/DSP and the input end of the hardware protection circuit, the output end of the hardware protection circuit is connected to the FPGA/CPLD, the FPGA/CPLD is further connected to the IGBT driving module, the analog signal conditioning circuit is used for conditioning the analog quantity signal collected by the sensor into a standard signal and transmitting the standard signal to the MCU/DSP and the hardware protection circuit, the MCU/DSP is used for locking the PWM pulse signal sent by the internal pulse generator and sending a protection action signal to the FPGA/CPLD when the detection value of the sensor exceeds a preset protection threshold value, the hardware protection circuit outputs a signal to turn over when a detection value of the sensor exceeds a preset protection threshold value, the IGBT driving module is used for driving the IGBT to conduct and operate, and the FPGA/CPLD is used for controlling the IGBT driving module to stop driving the IGBT to operate when receiving a protection action signal transmitted by the MCU/DSP or the output signal of the hardware protection circuit turns over so as to protect the power unit module.

4. The high real-time modular converter control system of claim 3, wherein the hardware protection circuit comprises a digital potentiometer and a comparator, the digital potentiometer is connected with one input end of the comparator, the other input end of the comparator is connected with a sensor, the output end of the comparator is connected with the FPGA/CPLD, the digital potentiometer is used for providing a reference voltage for the comparator, and the comparator outputs a signal inversion when the analog quantity signal exceeds the reference voltage.

5. The high real-time modular converter control system of claim 4 wherein said sensors include temperature sensors for collecting IGBT temperature, current sensors for collecting magnitude of output current of said power cell modules and voltage sensors for collecting bus voltage.

6. The high real-time modular converter control system of claim 5 wherein said power cell module includes two hardware protection circuits, wherein one of said hardware protection circuits has an input connected to said current sensor and the other of said hardware protection circuits has an input connected to said voltage sensor.

7. The high real-time modular converter control system of claim 4, wherein said MCU/DSP is connected to said digital potentiometer through its SPI interface or IIC communication interface, said MCU/DSP is further used to adjust the potential of said digital potentiometer to adjust the reference voltage of said comparator.

8. The high real-time modular converter control system of claim 7 wherein said digital potentiometer is self-contained with non-volatile memory for storing the potential parameters outputted by said MCU/DSP.

9. The high real-time modular converter control system of claim 3, wherein said FPGA/CPLD is provided with an interlock protection input port and an interlock protection output port, and in said FPGA/CPLD of the master controller module and the plurality of said power unit modules, the interlock protection output port of one FPGA/CPLD is connected to the interlock protection input port of another FPGA/CPLD, the plurality of FPGAs/CPLDs are sequentially connected in series to form an interlock protection loop, any one power unit module generates a protection action, and the remaining power unit modules generate a protection action one by one along the loop.

10. The system as claimed in claim 9, wherein only high and low level signals are transmitted in the chain protection loop, when all the power unit modules are working normally, high level signals are transmitted in the chain protection loop, and when at least one power unit module is performing a protection action, low level signals are transmitted in the chain protection loop.