CN216624281U - Semiconductor memory device with a plurality of memory cells - Google Patents
Semiconductor memory device with a plurality of memory cells Download PDFInfo
- Publication number
- CN216624281U CN216624281U CN202123046574.7U CN202123046574U CN216624281U CN 216624281 U CN216624281 U CN 216624281U CN 202123046574 U CN202123046574 U CN 202123046574U CN 216624281 U CN216624281 U CN 216624281U
- Authority
- CN
- China
- Prior art keywords
- sub
- side wall
- sidewall
- semiconductor memory
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The application discloses a semiconductor memory device, which can reduce the probability of electric damage of the semiconductor memory device caused by charges of a bit line grid. A semiconductor memory device, comprising: a substrate; the contact window is positioned on the surface of the substrate and exposes the inside of the substrate; the stacking structure is positioned in the contact window and protrudes out of the upper surface of the substrate; the side wall is positioned on the surface of the side wall of the stacked structure, and the side wall at least comprises: the first sub-side wall is positioned on the surface of the side wall of the stacked structure; the second sub-side wall is positioned on the surface of the first sub-side wall; the third sub-side wall is at least partially positioned on the surface of the second sub-side wall, wherein the third sub-side wall is obtained by the second sub-side wall through nitridation treatment; the first sub-side wall is connected with the third sub-side wall.
Description
Technical Field
The present application relates to the field of semiconductor memory devices, and more particularly, to semiconductor memory devices.
Background
In a semiconductor memory device, bit line structures and bit line gates are provided, and the bit line structures connect the bit line gates in the same row in series, thereby realizing a memory function. In the prior art, when the semiconductor memory device is used, the movement of charges in the bit line gate can cause breakdown of the semiconductor memory device if the charges flow to an undesired place, and the irreversible electrical damage is caused to the semiconductor memory device.
SUMMERY OF THE UTILITY MODEL
Accordingly, the present application provides a semiconductor memory device, which can reduce the probability of the electrical damage of the semiconductor memory device caused by the charges of the bit line gate.
The application provides a semiconductor storage device, including:
a substrate;
the contact window is positioned on the surface of the substrate and exposes the inside of the substrate;
the stacking structure is positioned in the contact window and protrudes out of the upper surface of the substrate;
the side wall is positioned on the surface of the side wall of the stacked structure, and the side wall at least comprises:
the first sub-side wall is positioned on the surface of the side wall of the stacked structure;
the second sub-side wall is positioned on the surface of the first sub-side wall;
the third sub-side wall is at least partially positioned on the surface of the second sub-side wall, wherein the third sub-side wall is obtained by the second sub-side wall through nitridation treatment;
the first sub-side wall is connected with the third sub-side wall.
Optionally, the first sub-side wall and the third sub-side wall have the same composition.
Optionally, the second sub-sidewall portion is discontinuous.
Optionally, the thickness of the third sub-sidewall is 0.5nm to 2 nm.
Optionally, the thickness of the second sub-sidewall is one fifth to one third of the thickness of the first sub-sidewall.
Optionally, the first sub-sidewall spacer includes at least one of a silicon layer, a silicon oxide layer, and a silicon nitride layer, and the second sub-sidewall spacer includes at least one of a silicon layer and a silicon oxide layer.
Semiconductor memory device in this application is right the side wall has carried out the nitrogenize treatment, consequently can strengthen the dielectric strength of side wall at least, makes and is using during the semiconductor memory device, the charge change in the stacked structure can the side wall is isolated, and prevention and cure electric charge escapes, causes this semiconductor memory device to be punctured, takes place the electrical property and destroys.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of the semiconductor memory device according to an embodiment of the present application before nitridation processing.
Fig. 3 is a schematic structural diagram of the semiconductor memory device after performing nitridation process according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of the semiconductor memory device according to another embodiment of the present application before nitridation process is performed.
Fig. 5 is a schematic structural diagram of the semiconductor memory device according to another embodiment of the present application before nitridation process is performed.
Fig. 6 is a schematic structural diagram of the semiconductor memory device shown in fig. 5 after nitridation processing.
Detailed Description
The semiconductor memory device will be further described with reference to the drawings and the embodiments.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present application.
In this embodiment, the method for manufacturing a semiconductor memory device includes the steps of:
step S101: providing a substrate 101, wherein a plurality of contact windows are formed on the surface of the substrate 101, a stacked structure (132a or 132b) is formed in each contact window, and the upper surface of each stacked structure (132a or 132b) is higher than the upper surface of the substrate 101;
step S102: a sidewall 161 is formed on the sidewall surface of the stacked structure (132a or 132b), as shown in fig. 2.
Step S103: the sidewall spacers 161 are nitrided to at least enhance the insulating strength of the surface of the sidewall spacers 161, as shown in fig. 3.
In this embodiment, since the sidewall 161 is nitrided, the insulating strength of the sidewall 161 can be at least enhanced, so that when the semiconductor memory device is used, the charge change in the stacked structure (132a or 132b) can be isolated by the sidewall 161 to prevent the charge from escaping, which causes the semiconductor memory device to be broken down and electrically damaged.
The substrate 101 includes a semiconductor base. The material of the semiconductor substrate may include silicon (Si), such as crystalline Si, polycrystalline silicon, or amorphous Si. In some embodiments, the semiconductor substrate may comprise a semiconductor material, such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).
In some embodiments, conductive regions, such as impurity-doped wells, or other structures doped with impurities, may be formed within the substrate 101.
An isolation structure 102 is formed in the substrate 101, and the substrate 101 is divided into a plurality of active regions 1021, and the active regions 1021 may be arranged at equal intervals. The isolation structure 102 may be a Shallow Trench Isolation (STI) structure, and the isolation structure 102 is formed by etching the substrate 101 to form a trench and then filling the trench with an insulating material. The insulating material used for the isolation structure 102 may be at least one of insulating dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.
The active regions 1021 may have regular shapes, such as long stripes, and be arranged regularly. A gate structure is formed in the active region 1021.
Word lines are also formed in the substrate 101 and intersect the active area 1021. The bit lines and the word lines are arranged perpendicular to each other and intersect the active region 1021, and the bit line gates are located at the intersections and connected to the bit lines. The bit lines are partially located on the bit line grid and partially located on the surface of other areas of the substrate 101.
In one embodiment, the stacked structure (132a or 132b) includes a bit line structure. In the embodiment shown in fig. 2, the bit line structure at least includes a metal layer 151, and the metal layer 151 includes a single conductive metal material layer or multiple conductive metal material layers. In the embodiment shown in fig. 3, the metal layer 151 only includes a tungsten layer, and actually, in other embodiments, the metal layer 151 may further include a titanium nitride layer. In some embodiments, the metal layer 151 includes a titanium nitride layer and a tungsten layer sequentially stacked in a direction perpendicular to an upper surface of the substrate 101.
In the embodiment shown in fig. 3, the bitline structure further includes a liner 130 disposed under the metal layer 151. The liner 130 includes at least one of an amorphous silicon layer and a phosphorus-doped silicon layer. In fact, in other embodiments, the specific material of the liner 130 may be set as desired.
In fact, please refer to fig. 4, which is a schematic structural diagram of the semiconductor memory device according to another embodiment of the present application before the nitridation process is performed.
In this embodiment, at other positions of the semiconductor memory device, the stacked structure (132a or 132b) may further include a first insulating layer 103, a second insulating layer 104, a third insulating layer 105, and a first conductive layer 106, which are disposed below the metal layer 151 and upward along a direction perpendicular to the surface of the substrate 101.
The material of the first insulating layer 103 and the third insulating layer 105 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, and other insulating materials. The first insulating layer 103 and the third insulating layer 105 may have a single-layer structure or a multilayer structure.
The material of the second insulating layer 104 may also include, but is not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxycarbide, and silicon oxynitride; moreover, the material of the second insulating layer 104 is different from the materials of the first insulating layer 103 and the third insulating layer 105, and the second insulating layer is subsequently used as an etching stop layer, and has different etching selectivity from the first insulating layer 103 and the third insulating layer 105.
In an embodiment, the sidewall spacers 161 include at least one of silicon sidewall spacers 161 and silicon oxide sidewall spacers 161. In fact, the specific material of the sidewall 161 may also be set as required, and a material having an insulating property and capable of being nitrided is a preferred material.
The nitriding treatment refers to a chemical heat treatment process for making nitrogen atoms penetrate into a target object in a certain medium at a certain temperature. The target object subjected to nitriding treatment has excellent properties of wear resistance, fatigue resistance, corrosion resistance and high temperature resistance at least on the surface thereof. When the object is an insulator, the nitriding treatment can further enhance the insulation strength of the object.
In the nitridation treatment, the nitridation treatment may be performed by selecting a self-limiting growth and a quasi-saturation thickness of a thermal nitridation or plasma-enhanced thermal silicon nitride film, or by selecting a plasma anodic nitridation technique or the like. It should be noted that, when the plasma anodic nitridation technology and other methods are adopted, the surface of the sidewall 161 needs to be pre-etched to remove the natural oxide layer on the surface of the sidewall 161, so that the film growth efficiency is improved.
In one embodiment, the nitriding treatment comprises nitriding treatment, and the nitriding depth of the nitriding treatment is 0.5 nm-2 nm. The depth of nitriding is related to the thickness of the nitrided surface that is finally formed. Research shows that the nitrided surface can show better insulating property when the thickness of the nitrided surface is 0.5 nm-2 nm.
In one embodiment, the nitriding treatment is carried out at a working temperature of 500 ℃ to 600 ℃. The operating temperature may in fact be set as desired. Researches show that when the working temperature is 500-600 ℃, a better nitriding effect can be achieved, and excessive energy loss is avoided.
In an embodiment, the method for forming the sidewall spacer 161 on the sidewall surface of the stacked structure (132a or 132b) at least includes the following steps: at least one sub-sidewall is formed on the sidewall surface of the stacked structure (132a or 132 b).
In this embodiment, a plurality of sub-spacers may be formed on the surface of the sidewall of the stacked structure (132a or 132b), and the sidewall 161 including the plurality of sub-spacers may be subjected to a nitridation process. Each sub-sidewall can play a separate insulating role, and therefore, in this embodiment, the insulating performance of the sidewall of the stacked structure (132a or 132b) can be enhanced by forming a plurality of sub-sidewalls.
Referring to fig. 5, fig. 5 is a schematic structural diagram of the semiconductor memory device according to another embodiment of the present application before nitridation process is performed.
In the embodiment shown in fig. 5, the semiconductor memory device includes two sub-spacers, namely a first sub-spacer 164 and a second sub-spacer 163.
In an embodiment, when performing the nitridation on the sidewall spacer 161 having the plurality of sub-sidewall spacers, the method for performing the nitridation on the sidewall spacer 161 at least includes the following steps: and nitriding the outermost sub-side wall to at least enhance the insulation strength of the outermost sub-side wall.
Referring to fig. 6, fig. 6 is a schematic structural diagram illustrating the semiconductor memory device of the embodiment shown in fig. 5 after nitridation.
In this embodiment, the second sub-sidewall spacers 163 are processed to obtain a strengthened nitrided surface 165. The nitrided surface 165 has a stronger dielectric strength than the first and second sub-spacers 164, 163 and, in fact, has a greater hardness. The nitrided surface 165 can enhance the insulating strength of the sidewall 161 formed by the first sub-sidewall 164 and the second sub-sidewall 163, and further prevent the electrical variation in the stacked structure (132a or 132b) from being conducted to an adjacent region through the sidewall 161, which may cause breakdown of the semiconductor memory device.
Moreover, since the depth that the nitridation can reach is related to the temperature, the pressure, and the like, in this embodiment, only the second sub-sidewall 163 located at the outer side is processed, which is beneficial to reducing the difficulty of the nitridation and reducing the requirements on the temperature and the pressure in the nitridation process.
In an embodiment, the method for forming the sidewall spacer 161 on the sidewall surface of the stacked structure (132a or 132b) at least includes the following steps: and sequentially forming two sub-side walls which are stacked on the surface of the side wall of the stacked structure (132a or 132 b). In this embodiment, the sidewall 161 at least includes two sub-sidewalls, and the arrangement of the sub-sidewalls effectively protects charges of the stacked structure (132a or 132b) from being conducted to the surrounding area through the sidewall 161, which may cause the semiconductor memory device to be broken down and damaged.
In an embodiment, the two sub-sidewalls include a first sub-sidewall 164 and a second sub-sidewall 163, the first sub-sidewall 164 is disposed on a sidewall surface of the stacked structure (132a or 132b), and the second sub-sidewall 163 is disposed on a surface of the first sub-sidewall 164; the first sub-side walls 164 include at least one of a silicon layer, a silicon oxide layer, and a silicon nitride layer, and the second sub-side walls 163 include at least one of a silicon layer and a silicon oxide layer.
The silicon layer, the silicon oxide layer and the silicon nitride layer are all material layers with strong insulating property, so that the initial good insulating property can be achieved by arranging the two sub-side walls.
In some embodiments, in order to ensure that the total thickness of the side walls 161 is within a reasonable range and meet the requirement of the subsequent nitridation process, the thickness of the second sub-side walls 163 is one fifth to one third of the thickness of the first sub-side walls 164.
The embodiment of the application also provides a semiconductor storage device.
Fig. 6 is a schematic structural diagram of a semiconductor memory device according to an embodiment of the present application. In this embodiment, the semiconductor memory apparatus includes: a substrate 101; a contact window located on the surface of the substrate 101, wherein the contact window exposes the inside of the substrate 101; a stacked structure (132a or 132b) located in the contact window and protruding from the upper surface of the substrate 101; a sidewall 161 located on a sidewall surface of the stacked structure (132a or 132b), wherein the sidewall 161 at least includes: a first sub-sidewall 164 on a sidewall surface of the stacked structure (132a or 132 b); the second sub-sidewall 163 is located on the surface of the first sub-sidewall 164; a third sub-sidewall at least partially located on the surface of the second sub-sidewall 163, wherein the third sub-sidewall is obtained by performing a nitridation process on the second sub-sidewall 163; the first sub-side wall is connected with the third sub-side wall.
In this embodiment, the sidewall 161 at least includes three sub-sidewalls, and the arrangement of the sub-sidewalls effectively protects the charges of the stacked structure (132a or 132b) from being conducted to the surrounding area through the sidewall, which may cause the semiconductor memory device to be broken down and damaged. And, the third sub-sidewall is partially connected to the first sub-sidewall, and the surface of the third sub-sidewall is subjected to nitridation treatment on the second sub-sidewall 163 to obtain the third sub-sidewall, and the nitridation depth can reach the first sub-sidewall 164, so that sufficient insulation strength is obtained.
In this embodiment, after the second sub-sidewall spacer 163 is processed, a strengthened nitrided surface 165 corresponding to the third sub-sidewall spacer is obtained. The nitrided surface 165 has a stronger dielectric strength than the first and second sub-sidewall spacers 164, 163 and, in fact, has a greater hardness. The nitrided surface 165 can enhance the insulating strength of the sidewall 161 formed by the first sub-sidewall 164 and the second sub-sidewall 163, and further prevent the electrical variation in the stacked structure (132a or 132b) from being conducted to an adjacent region through the sidewall 161, which may cause breakdown of the semiconductor memory device.
Moreover, since the depth that the nitridation can reach is related to the temperature, the pressure, and the like, in this embodiment, only the second sub-sidewall 163 located at the outer side is processed, which is beneficial to reducing the difficulty of the nitridation and reducing the requirements on the temperature and the pressure in the nitridation process.
In an embodiment, the first sub-spacers 164 include at least one of a silicon layer, a silicon oxide layer, and a silicon nitride layer, and the second sub-spacers 163 include at least one of a silicon layer and a silicon oxide layer.
The first sub-sidewall 164 and the third sub-sidewall have the same composition. In some embodiments, the first sub-sidewall spacers 164 and the third sub-sidewall spacers are made of silicon nitride.
In one embodiment, the second sub-sidewall 163 is partially discontinuous, so as to achieve the effect of protecting the sidewall without increasing the parasitic capacitance. In addition, in some embodiments, the thickness of the second sub-sidewall spacers 163 is one fifth to one third of the thickness of the first sub-sidewall spacers 164, so as to ensure that the total thickness of the sidewall spacers 161 is within a reasonable range and meet the requirements of the subsequent nitridation treatment.
In an embodiment, the thickness of the third sub-sidewall is 0.5nm to 2 nm. Research shows that the nitrided surface can show better insulating property when the thickness of the nitrided surface is 0.5 nm-2 nm. In fact, the thickness of the third sub-sidewall may also be set as needed.
The above-mentioned embodiments are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by the contents of the specification and the drawings, such as the combination of technical features between the embodiments and the direct or indirect application to other related technical fields, are also included in the scope of the present application.
Claims (7)
1. A semiconductor memory device, comprising:
a substrate;
the contact window is positioned on the surface of the substrate and exposes the inside of the substrate;
the stacking structure is positioned in the contact window and protrudes out of the upper surface of the substrate;
the side wall is positioned on the surface of the side wall of the stacked structure, and the side wall at least comprises:
the first sub-side wall is positioned on the surface of the side wall of the stacked structure;
the second sub-side wall is positioned on the surface of the first sub-side wall;
the third sub-side wall is at least partially positioned on the surface of the second sub-side wall, wherein the third sub-side wall is obtained by the second sub-side wall through nitridation treatment;
the first sub-side wall is connected with the third sub-side wall.
2. The semiconductor memory device according to claim 1, wherein the first sub-sidewall and the third sub-sidewall have the same composition.
3. The semiconductor memory device according to claim 1, wherein the second sub-sidewall portion is discontinuous.
4. The semiconductor memory device according to claim 1, wherein the thickness of the third sub-sidewall is 0.5nm to 2 nm.
5. The semiconductor memory device according to claim 1, wherein the thickness of the second sub-sidewall spacer is one fifth to one third of the thickness of the first sub-sidewall spacer.
6. The semiconductor memory device according to claim 1, wherein the first sub-sidewall spacer comprises at least one of a silicon layer, a silicon oxide layer, and a silicon nitride layer.
7. The semiconductor memory device according to claim 1, wherein the second sub-sidewall spacer comprises at least one of a silicon layer and a silicon oxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123046574.7U CN216624281U (en) | 2021-12-06 | 2021-12-06 | Semiconductor memory device with a plurality of memory cells |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123046574.7U CN216624281U (en) | 2021-12-06 | 2021-12-06 | Semiconductor memory device with a plurality of memory cells |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216624281U true CN216624281U (en) | 2022-05-27 |
Family
ID=81701408
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202123046574.7U Active CN216624281U (en) | 2021-12-06 | 2021-12-06 | Semiconductor memory device with a plurality of memory cells |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216624281U (en) |
-
2021
- 2021-12-06 CN CN202123046574.7U patent/CN216624281U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10998326B2 (en) | Integrated assemblies and methods of forming integrated assemblies | |
| US20190206886A1 (en) | Semiconductor memory devices | |
| US8163617B2 (en) | Vertical channel type non-volatile memory device and method for fabricating the same | |
| US11139304B2 (en) | Manufacturing method of semiconductor memory device | |
| WO2020206997A1 (en) | Three-dimensional vertical single transistor ferroelectric memory and manufacturing method thereof | |
| US20150187790A1 (en) | Methods of forming vertical type semiconductor devices including oxidation target layers | |
| US20150214240A1 (en) | Nonvolatile memory device and method for fabricating the same | |
| CN110301037A (en) | Three-dimensional memory structure and its manufacturing method | |
| US9236439B2 (en) | Semiconductor device and method for forming the same | |
| US20150104934A1 (en) | Semiconductor device and method for fabricating the same | |
| CN216624281U (en) | Semiconductor memory device with a plurality of memory cells | |
| US20180211961A1 (en) | Semiconductor memory device and manufacturing method thereof | |
| CN102637647B (en) | The forming method of the memory cell of flash memory | |
| CN114334837A (en) | Semiconductor memory device and method of manufacturing the same | |
| US9269618B2 (en) | Semiconductor device and method for manufacturing the same | |
| CN1191624C (en) | Method for combination of self alignment contact procedure with self aligned silicon compound procedure | |
| CN114664846A (en) | Semiconductor memory structure and preparation method | |
| CN102842580B (en) | Dynamic random access memory and manufacturing method thereof | |
| CN114678469A (en) | Semiconductor structure and forming method thereof | |
| CN111668231B (en) | 3D NAND memory and forming method thereof | |
| US11871564B2 (en) | Semiconductor structure and manufacturing method thereof | |
| US20060079064A1 (en) | Fabrication method for a trench capacitor having an insulation collar which on one side is electrically connected to a substrate via a buried contact, in particular for a semiconductor memory cell, and corresponding trench capacitor | |
| US8748299B2 (en) | Semiconductor devices having an epitaxial layer on active regions and shallow trench isolation regions | |
| CN114068546B (en) | Semiconductor structure and manufacturing method thereof | |
| CN116097919A (en) | Preparation method of three-dimensional memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |