CN216491273U - Core plate based on T507 - Google Patents
Core plate based on T507 Download PDFInfo
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- CN216491273U CN216491273U CN202123092552.4U CN202123092552U CN216491273U CN 216491273 U CN216491273 U CN 216491273U CN 202123092552 U CN202123092552 U CN 202123092552U CN 216491273 U CN216491273 U CN 216491273U
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Abstract
The utility model discloses a core board based on T507, which comprises a circuit board; the circuit board is provided with a main control module, a power management module, a memory chip module, a storage chip and a field bus chip; the model of the main control module is T507; one side of the circuit board is provided with a plug-in golden finger; through with CPU, power management, the memory, five kinds of main functional moduleization of storage and field bus, but provide novel interface function and promoted T507 core board's developability, and set up multiunit memory chip, and with memory chip layering setting, not only core board data processing ability has been improved, but also the volume that has reduced core board improves core board's integrated level, and simultaneously, one side of circuit is provided with the grafting golden finger, make T507 core board can peg graft with other equipment more conveniently, thereby satisfy current user to core board's functional requirement.
Description
Technical Field
The utility model relates to an electronic component field especially relates to a nuclear core plate based on T507.
Background
The core board is an electronic motherboard that integrates a CPU, memory devices, pins, and other hardware elements. The pins and the matched bottom plate are connected to realize the functions of various different requirements, so that the core plate can realize a system chip in a certain field and is applied to different scenes. The system is called a single chip microcomputer or an embedded development platform.
At present, most of core boards based on T507 chips in the prior art adopt stamp hole type interfaces. The core board needs to be connected with the main board in a welding mode, and although reliability is guaranteed to a certain extent, the core board is inconvenient to maintain and disassemble. Meanwhile, the T507 main CPU can emit larger heat during working, and passive heat dissipation or active heat dissipation is required, so that a reliable heat dissipation device needs to be additionally arranged on the stamp hole type core board. In order to arrange the heat sink, screw holes must be added to the core module and the engineering main board, and it is difficult to leave screw hole sites on the core board with a small area. Therefore, it is less versatile and thus cannot satisfy the functional requirements of the core board for the current users.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem that: the core board based on the T507 is provided, and the universality and the expandability of the core board are improved.
In order to solve the technical problem, the utility model discloses a technical scheme be:
a core board based on T507 comprises a circuit board;
the circuit board is provided with a main control module, a power management module, a memory chip module, a storage chip and a field bus chip; the model of the main control module is T507;
one side of the circuit board is provided with a plug-in golden finger;
the memory chip module comprises memory chips with the number more than one; the memory chips are arranged in a layered mode;
the main control module is respectively connected with each memory chip, each storage chip, each field bus chip, each power management module and each golden finger;
the power management module is connected with the golden finger.
Further, the distance between the feet of the golden finger is 0.5 mm.
Further, the power management module has a model number of AXP 853T; the power supply comprises an SWOUT pin, a power supply input pin, a plurality of groups of DC/DC pins, a plurality of groups of ALDO pins and a plurality of groups of BLDO pins;
the power input pin is connected with the golden finger;
the SWOUT pin, the multiple groups of DC/DC pins, the multiple groups of ALDO pins and the multiple groups of BLDO pins are used for outputting different voltages, wherein the DC/DC pins are connected with the main control module.
Further, the memory chip module comprises a first memory chip, a second memory chip, a third memory chip and a fourth memory chip;
the first memory chip and the second memory chip are positioned on the top layer of the circuit board, and the third memory chip and the fourth memory chip are positioned on the bottom layer of the circuit board.
Further, the package models of the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are FPGA 96.
Further, the memory chip is an EMMC chip;
the EMMC chip comprises a signal line pin, a CLK pin, a CMD pin, a DS pin and a RESET pin, and is respectively connected with a function pin corresponding to the main control module.
Further, the type of the fieldbus chip is MCP 2515;
the MCP2515 includes a CS pin, an SCK pin, an SI pin, an SO pin, and an INT pin, and is connected to a corresponding function pin of the main control module, respectively.
The beneficial effects of the utility model reside in that: through with CPU, power management, the memory, five kinds of main functional moduleizations of storage and field bus, but provide novel interface function and promoted T507 core board's developability, and set up multiunit memory chip, and with memory chip layering setting, core board data processing ability has not only been improved, and the volume that has reduced core board improves core board's integrated level, and simultaneously, one side of circuit is provided with the grafting golden finger, make T507 core board can peg graft with other equipment more conveniently, thereby satisfy the functional requirement of current user to core board.
Drawings
Fig. 1 is a schematic structural diagram of a core board based on T507 in an example of the present invention;
fig. 2 is a schematic diagram of module connection of a core board based on T507 in an example of the present invention;
fig. 3 is a schematic top view of a core board based on T507 according to an example of the present invention;
fig. 4 is a schematic bottom structure diagram of a core board based on T507 in an example of the present invention;
fig. 5 is a schematic pin connection diagram of a main control module of a core board based on T507 according to an example of the present invention;
fig. 6 is a pin connection diagram of a memory module of a core board based on T507 according to an example of the present invention;
fig. 7 and fig. 8 are schematic pin connection diagrams of a gold finger of a T507-based core board according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a power management module of a core board based on T507 in an example of the present invention;
fig. 10 is a pin connection diagram of a power management module based on a T507 core board according to an example of the present invention;
fig. 11 is a pin connection diagram of a memory chip based on a T507 core board according to an example of the present invention;
fig. 12 is a pin connection diagram of a fieldbus chip based on a T507 core board according to an example of the present invention;
description of reference numerals:
1. a circuit board; 2. a main control module; 3. a power management module; 4. a memory chip module; 41. a first memory chip; 42. a second memory chip; 43. a third memory chip; 44. a fourth memory chip; 5. a memory chip; 6. a field bus chip; 7. a golden finger.
Detailed Description
In order to explain the technical content, the objects and the effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1, a core board based on T507 includes a circuit board;
the circuit board is provided with a main control module, a power management module, a memory chip module, a storage chip and a field bus chip; the model of the main control module is T507;
one side of the circuit board is provided with a plug-in golden finger;
the memory chip module comprises memory chips with the number more than one; the memory chips are arranged in a layered mode;
the main control module is respectively connected with each memory chip, each storage chip, each field bus chip, each power management module and each golden finger;
the power management module is connected with the golden finger.
As can be seen from the above description, the utility model has the advantages that: through with CPU, power management, the memory, five kinds of main functional moduleization of storage and field bus, but provide novel interface function and promoted T507 core board's developability, and set up multiunit memory chip, and with memory chip layering setting, not only core board data processing ability has been improved, but also the volume that has reduced core board improves core board's integrated level, and simultaneously, one side of circuit is provided with the grafting golden finger, make T507 core board can peg graft with other equipment more conveniently, thereby satisfy current user to core board's functional requirement.
Further, the distance between the feet of the golden finger is 0.5 mm.
As can be seen from the above description, the angular distance between the gold fingers is set to 0.5mm, so that the core board can be connected to the AHD camera control board and other devices in a matching manner, and some specific functions of the core board are connected to the AHD camera control board through the gold finger connectors, so that the performance of the plugged device is improved.
Further, the power management module has a model number of AXP 853T; the power supply comprises an SWOUT pin, a power supply input pin, a plurality of groups of DC/DC pins, a plurality of groups of ALDO pins and a plurality of groups of BLDO pins;
the power input pin is connected with the golden finger;
the SWOUT pin, the multiple groups of DC/DC pins, the multiple groups of ALDO pins and the multiple groups of BLDO pins are used for outputting different voltages, wherein the DC/DC pins are connected with the main control module.
It can be known from the above description, through adopting the power management module of AXP853T chip as nuclear core plate for power management module can provide the voltage of multiple different demands, and carries out stable power supply for different functional modules on nuclear core plate, thereby has also strengthened the expansibility of nuclear core plate when guaranteeing nuclear core plate stabilizing action.
Further, the memory chip module comprises a first memory chip, a second memory chip, a third memory chip and a fourth memory chip;
the first memory chip and the second memory chip are positioned on the top layer of the circuit board, and the third memory chip and the fourth memory chip are positioned on the bottom layer of the circuit board.
According to the above description, by arranging the plurality of memory chips, arranging the first memory chip and the second memory chip on the top layer of the circuit board, and arranging the third memory chip and the fourth memory chip on the bottom layer of the circuit board, the volume of the core board is reduced, and the integration level of the core board is improved.
Further, the package models of the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are FPGA 96.
According to the description, the memory chips with the same type are integrated, so that the matching degree of the memories is improved, and the memory performance is improved.
Further, the memory chip is an EMMC chip;
the EMMC chip comprises a signal line pin, a CLK pin, a CMD pin, a DS pin and a RESET pin, and is respectively connected with a function pin corresponding to the main control module.
As can be seen from the above description, the EMMC chip is used as the memory chip, and the corresponding clock pin, the command pin, the reset pin, and other functional pins are respectively connected to the main control module, so that the EMMC chip can be stably used for storing system software and application software required by the core board, and the performance of the core board is improved.
Further, the type of the fieldbus chip is MCP 2515;
the MCP2515 includes a CS pin, an SCK pin, an SI pin, an SO pin, and an INT pin, and is connected to a corresponding function pin of the main control module, respectively.
As can be seen from the above description, a chip with the model number of MCP2515 is used as a field bus, and corresponding functional pins, such as a CS pin, an SCK pin, an SI pin, and the like, are respectively connected to corresponding functional pins of the main control module, so that the function of efficiently controlling the bus is achieved, and the data communication capability of the core board is improved.
The core board based on T507 of the present embodiment can be applied to various types of electronic devices such as an AHD camera control board, and connects a specific function of the core board to the AHD camera control board, and the following description is made by way of specific embodiments:
referring to fig. 1 and 2, a core board based on T507 includes a circuit board 1;
the circuit board 1 is provided with a main control module 2, a power management module 3, a memory chip module 4, a storage chip 5 and a field bus chip 6; the model of the main control module 2 is T507; one side of the circuit board 1 is provided with a plug-in golden finger 7, and the pin pitch of the golden finger 7 is 0.5 mm; the main control module 2 is respectively connected with each memory chip, the storage chip 5, the field bus chip 6, the power management module 3 and the golden finger 7; the power management module 3 is connected with the golden finger 7; referring to fig. 2, the gold finger 7 is connected to multiple groups of pins of the main control module 2 and the power management module 3, such as 5VDC, USB2.0, UART, HDMI, and the like;
referring to fig. 3 and 4, the memory chip module 4 includes memory chips whose number is greater than one, and the memory chips are arranged in layers; the memory chip module 4 comprises a first memory chip 41, a second memory chip 42, a third memory chip 43 and a fourth memory chip 44, and the packaging model is FPGA 96; the specific type of the memory chip is changed according to specific product requirements, and the adopted packaging type is FPGA96, such as a DDR3 memory chip; the first memory chip 41 and the second memory chip 42 are located on the top layer of the circuit board 1, and the third memory chip 43 and the fourth memory chip 44 are located on the bottom layer of the circuit board 1;
referring to fig. 5, the main control module 2 has a model number of T507 and is a 64-bit processor; the memory is a 32-bit data bus, and is shown as SDQ0-SDQ 31; the memory chip adopts a first memory chip 41 and a second memory chip 42 with 2 pieces of 16bit width to realize a first group of 32bit wide memories; a second group of 32-bit wide memories are realized by adopting 2 third memory chips 43 and fourth memory chips 44 with the width of 16 bits, and the second group of memories can be free of mounting;
referring to fig. 6, the specific connection between the memory chip and the main control module 2 is as follows: the control signal lines SA0-SA15/SBA0-SBA2/SWE/SRAS/SCAS/SCKE0/SODT0/SODT1/SCKE1/SCKP/SCKN of the main control module 2 are respectively connected with the a0-a15/BA0-BA2/WE/RAS/CAS/CKE/ODT 1/CKE1/CK pins of the first memory chip 41 and the second memory chip 42;
a control signal line SDQS1P _ SDQS1N/SDQS0P _ SDQS0N of the main control module 2 is connected to DQSL _ DQSL/DQSU _ DQSU pins of the first memory chip 41, respectively; the control signal line SQDM1/0 of the main control module 2 is connected to the DML/DMU of the first memory chip 41;
a control signal line SDQS2P _ SDQS2N/SDQS3P _ SDQS 3N/of the main control module 2 is respectively connected with a DQSL _ DQSL/DQSU _ DQSU pin of the second memory chip 42; the control signal line SQDM2/3 of the main control module 2 is connected to the DML/DMU of the second memory chip 42, respectively;
the control signal line SA0-SA15/SBA0-SBA2/SWE/SRAS/SCAS/SCKE0/SODT0/SCKP/SCKN of the main control module 2 is connected with pins a0-a15/BA0-BA2/WE/RAS/CAS/CKE/ODT/CK of the third memory chip 43 and the fourth memory chip 44, respectively;
a control signal line SDQS1P _ SDQS1N/SDQS0P _ SDQS0N of the main control module 2 is connected to DQSL _ DQSL/DQSU _ DQSU pins of the third memory chip 43, respectively; the control signal line SQDM1/0 of the main control module 2 is connected to the DML/DMU pin of the third memory chip 43, respectively;
a control signal line SDQS2P _ SDQS2N/SDQS3P _ SDQS 3N/of the main control module 2 is respectively connected with a DQSL _ DQSL/DQSU _ DQSU pin of the fourth memory chip 44; the control signal line SQDM2/3 of the main control module 2 is connected to the DML/DMU pin of the fourth memory chip 44, respectively;
the data signal lines of the main control module 2 are divided into four groups, and 8 data signal lines are one group; wherein the SDQ0-SDQ7 are a group which is connected with DQU0-DQU7 of the first memory chip 41 and the third memory chip 43; SDQ8-SDQ15 are a group, which is connected to DQL0-DQL7 of the first memory chip 41 and the third memory chip 43; SDQ15-SDQ23 are a group, which is connected to DQL0-DQL7 of the second memory chip 42 and the fourth memory chip 44; SDQ24-SDQ31 are a group that is connected to DQU0-DQU7 of the second memory chip 42 and the fourth memory chip 44;
referring to fig. 7 to 10, the power management module 3 has a model number AXP 853T; the power supply comprises an SWOUT pin, a power supply input pin, a plurality of groups of DC/DC pins, a plurality of groups of ALDO pins and a plurality of groups of BLDO pins; the power input PIN is connected with the golden finger 7, that is, a system power-on function PMU-PWRON of the power management module 3 is connected with the PIN246 of the golden finger 7;
the SWOUT pin, the multiple groups of DC/DC pins, the multiple groups of ALDO pins and the multiple groups of BLDO pins are used for outputting different voltages, wherein the DC/DC pins are connected with the main control module 2; specifically, the BLDO5 power output of the power management module 3 is connected to the PIN65 of the gold finger 7; the ALDO5 power output of the power management module 3 is connected with the PIN67 of the golden finger 7; the BLDO4 power output of the power management module 3 is connected with the PIN69/PIN71 of the golden finger 7; the BLDO3 power output of the power management module 3 is connected with the PIN73/PIN75 of the golden finger 7; the GPIO1 function of the power management module 3 is connected with the PIN79 of the golden finger 7; a system power-on function PMU-PWRON of the power management module 3 is connected with the PI246 of the golden finger 7; the CLDO2 power output of the power management module 3 is connected with the PIN180/182 of the golden finger 7; the DCDC1 power output of the power management module 3IC-U1 is connected with the PIN237/239/241/243 of the golden finger 7; the VIN1/VIN2/VIN3_1/VIN3_2/VIN4/VIN5/VIN6/ALDOIN/BLDOIN/CLDOIN power input of the power management module 3 is connected with the PIN245/247/249/251/253/255/257/259 of the golden finger 7; the SWOUT power supply output of the power management module 3 is connected with the PIN250 of the golden finger 7;
referring to fig. 11, the memory chip 5 is an EMMC chip; the EMMC chip comprises a signal line pin, a CLK pin, a CMD pin, a DS pin and a RESET pin, and is respectively connected with a corresponding functional pin of the main control module 2; specifically, 8 signal lines of the SDC2_ D0-D7 signals of the main control module 2 are sequentially connected with the DAT0-7 of the memory chip 5; the SDC2 — CMD signal of the main control module 2 is connected with the CMD signal of the memory chip 5; the SDC2_ CLK signal of the main control module 2 is connected with the CLK signal of the memory chip 5; the SDC2_ DS signal of the main control module 2 is connected with the DS signal of the memory chip 5; the SDC2_ RST signal of the main control module 2 is connected with the RESET # signal of the memory chip 5;
referring to fig. 12, the fieldbus chip 6 is of the MCP2515 type; the MCP2515 comprises a CS pin, an SCK pin, an SI pin, an SO pin and an INT pin, and is respectively connected with a corresponding functional pin of the main control module 2; the concrete connection is as follows:
the SPI1_ CS0 signal of the main control module 2 is connected with the CS signal of the field bus chip 6; the SPI1_ CLK signal of the main control module 2 is connected with the SCK signal of the field bus chip 6; the SPI1_ MOSI signal of the main control module 2 is connected with the SI signal of the field bus chip 6; the SPI1_ MISO signal of the main control module 2 is connected with the SO signal of the field bus chip 6; the PH9 signal of the main control module 2 is connected with the INT signal of the field bus chip 6;
in an optional embodiment, the screw hole positions of the radiating fins and the fixing half hole positions of the core board are added on the circuit board 1, so that the problems of convenient connection and vibration resistance reliability are solved; the interface also meets the current requirements for novel interfaces, so that the expandability of the core board is enhanced.
The above mentioned is only the embodiment of the present invention, and not the limitation of the patent scope of the present invention, all the equivalent transformations made by the contents of the specification and the drawings, or the direct or indirect application in the related technical field, are included in the patent protection scope of the present invention.
Claims (7)
1. A core board based on T507 is characterized by comprising a circuit board;
the circuit board is provided with a main control module, a power management module, a memory chip module, a storage chip and a field bus chip; the model of the main control module is T507;
one side of the circuit board is provided with a plug-in golden finger;
the memory chip module comprises memory chips with the number more than one; the memory chips are arranged in a layered mode;
the main control module is respectively connected with each memory chip, each storage chip, each field bus chip, each power management module and each golden finger;
the power management module is connected with the golden finger.
2. The T507-based core board as recited in claim 1 wherein a pitch of said gold fingers is 0.5 mm.
3. The T507-based core board of claim 1 wherein the power management module has a model number AXP 853T; the power supply comprises an SWOUT pin, a power supply input pin, a plurality of groups of DC/DC pins, a plurality of groups of ALDO pins and a plurality of groups of BLDO pins;
the power input pin is connected with the golden finger;
the SWOUT pin, the multiple groups of DC/DC pins, the multiple groups of ALDO pins and the multiple groups of BLDO pins are used for outputting different voltages, wherein the DC/DC pins are connected with the main control module.
4. The T507-based core board of claim 1, wherein the memory chip modules comprise a first memory chip, a second memory chip, a third memory chip and a fourth memory chip;
the first memory chip and the second memory chip are positioned on the top layer of the circuit board, and the third memory chip and the fourth memory chip are positioned on the bottom layer of the circuit board.
5. The T507-based core board of claim 4, wherein a package model of the first memory chip, the second memory chip, the third memory chip and the fourth memory chip is FPGA 96.
6. The T507-based core board of claim 1, wherein the memory chips are EMMC chips;
the EMMC chip comprises a signal line pin, a CLK pin, a CMD pin, a DS pin and a RESET pin, and is respectively connected with a function pin corresponding to the main control module.
7. The T507 based core board of claim 1 wherein the fieldbus chip is of the type MCP 2515;
the MCP2515 includes a CS pin, an SCK pin, an SI pin, an SO pin, and an INT pin, and is connected to a corresponding function pin of the main control module, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123092552.4U CN216491273U (en) | 2021-12-09 | 2021-12-09 | Core plate based on T507 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123092552.4U CN216491273U (en) | 2021-12-09 | 2021-12-09 | Core plate based on T507 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216491273U true CN216491273U (en) | 2022-05-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202123092552.4U Active CN216491273U (en) | 2021-12-09 | 2021-12-09 | Core plate based on T507 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216491273U (en) |
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2021
- 2021-12-09 CN CN202123092552.4U patent/CN216491273U/en active Active
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