CN216486180U - Strain signal synchronous acquisition analog front end and reference circuit - Google Patents
Strain signal synchronous acquisition analog front end and reference circuit Download PDFInfo
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- CN216486180U CN216486180U CN202220033512.8U CN202220033512U CN216486180U CN 216486180 U CN216486180 U CN 216486180U CN 202220033512 U CN202220033512 U CN 202220033512U CN 216486180 U CN216486180 U CN 216486180U
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Abstract
The utility model relates to a strain signal synchronous acquisition analog front end and a reference circuit, belonging to the electronic measurement field; the strain signal synchronous acquisition analog front end and reference circuit consists of a voltage input end, a differential amplifying circuit, a level translation module, a reference circuit, a switch selection module and an external ADC reference unit; the utility model discloses strain signal synchronous acquisition simulation front end and reference circuit, MCU's functioning speed can come the apolegamy model according to sampling rate and passageway number, still can survey absolute voltage, has two kinds of modes, and two kinds of modes can switch wantonly, and application scope is wider among the practical application.
Description
Technical Field
The utility model relates to a strain signal synchronous acquisition analog front end and reference circuit belongs to the electron measurement field.
Background
From ancient times, metrological measures have been closely related to human life and socioeconomic performance. A weighing apparatus is a tool of a weighing device, and refers to a measuring instrument for determining the mass of an object by the gravity acting on the object. In modern society, the use of electronic weighing apparatus has been widely applied to the fields of our daily life, trade calculation, automatic weighing system and automatic packaging. The accuracy and resolution of the electronic weighing apparatus directly influence the accuracy of a metering result in scientific research and are related to the personal interests of consumers, and the aim of the project is to develop a strain signal synchronous acquisition analog front end and a reference circuit, which can be applied to the weighing field of industrial production and meet the domestic market demand; the system can also be used as a strain signal acquisition system in scientific experiments.
SUMMERY OF THE UTILITY MODEL
To the technical problem, the utility model discloses a strain signal synchronous acquisition simulation front end and reference circuit, MCU's functioning speed can come the apolegamy model according to sampling rate and channel number, still can survey absolute voltage, has two kinds of modes, and two kinds of modes can switch wantonly, and application scope is wider among the practical application.
The purpose of the utility model is realized like this:
a strain signal synchronous acquisition analog front end and reference circuit is composed of a voltage input end, a differential amplification circuit, a level translation module, a reference circuit, a switch selection module and an external ADC reference unit;
the voltage input end is coupled to AGND through a filter capacitor EA3 by AVDD, coupled to AGND through a filter capacitor CA3, and passes through a zener diode ground protection circuit to generate INA + and INA-signals and VMID;
the differential amplifying circuit consists of a double operational amplifier OPA2188, a plurality of resistors and a plurality of capacitors; the AIA + and AIA-signals are respectively input into a pin 5 and a pin 3 of an OPA2188, and a pin 2 of the OPA2188 is connected with 5 same resistors in series and connected to a pin 1 output terminal of the OPA 2818; the 6 pins are connected with 5 same resistors in series to the 7-pin output end of the OPA2118, a circuit formed by connecting 10 same resistors in parallel is connected between the 2 pins and the 6 pins, and therefore a differential amplification circuit is formed, and INA + and INA-are amplified;
the level translation module consists of a dual operational amplifier OPA2277, a plurality of resistors and a plurality of capacitors; the output is carried out by pins 1 and 7 of the OPA2188, five resistors with the same resistance are respectively connected in series into pins 2 and 6 of the OPA2277, OUTA + is connected in series with five resistors with the same resistance into pin 2 of the OPA2277 to form negative feedback, pin 7 of the OPA2277 is connected in series with five resistors with the same resistance into pin 6 of the OPA2277 to form negative feedback, pin 3 and pin 5 of the OPA2277 are both connected with VCOM, and VCOM is grounded through a capacitor CA 18; according to the circuit symmetry characteristic, VCOM is equal to half of the sum of OUTA-and OUTA +, and level shifting can be realized by changing the value of VCOM; VMID and VC16 are connected in series with 6 resistors with the same resistance, one line is connected between the third resistor and the fourth resistor to obtain a VCOM value, and the obtained VCOM value is different due to the difference of VC16, namely level translation is realized;
the reference circuit consists of absolute contrast value and relative value circuits; the absolute ratio circuit consists of an ADR03BR chip, a plurality of resistors and a plurality of capacitors; the 2 pin of the ADR03BR is connected with the AVDD, and then is coupled into the 4 pin of the ADR03BR through a parallel circuit formed by C1 and E1, and is grounded; the 6 pins of the ADR03BR are output ends, are connected with VR23 and are connected in series with 6 resistors with equal resistance to ground, VR16 is connected between the second resistor and the third resistor, VR12 is connected between the third resistor and the fourth resistor, namely three outputs with different voltage values are obtained, and the output ends are also connected with AGND through a parallel circuit formed by C2 and E2 in a coupling mode; the relative value circuit is formed by dividing voltage of a plurality of resistors, the AVDD provides voltage, 12 resistors with the same resistance value are connected in series and then connected with the AGND, the PM25 is connected between the sixth resistor and the seventh resistor, the PM16 is connected between the eighth resistor and the ninth resistor, and the PM12 is connected between the ninth resistor and the tenth resistor, so that three voltages with different amplitudes are provided;
the switch selection module comprises a 3-path two-way alternative analog switch chip 74HC4053 with a common enable input control bit, pins 9, 10 and 11 of the chip are connected with SMOD, pins 12 are connected with VR25, pins 13 are connected with PM25, pins 2 are connected with VR12, pins 1 are connected with PM12, pins 5 are connected with VR16, pins 3 are connected with PM16, pins 14 and 16 are connected with TP25, pins 4 are connected with TP12 and pins 16, and voltage value selection is completed;
the ADC reference unit consists of a 74HC4053 analog switch chip, a double operational amplifier OPA2277, a plurality of resistors and a plurality of capacitors; a pin 3 of 74HC4053 is connected with TP16, a pin 5 is connected with TP25, a pin 4 is connected with a non-inverting input end of OPA2277B, a pin 7 of OPA2277B is connected with a resistor of 100 omega, and then a resistor of 2k omega is connected with an inverting input end to form a voltage follower, so that VC16 is obtained; the pin 13 of 74HC4053 is connected with TP12, the pin 12 is connected with TP25, the pin 14 is connected with the non-inverting input terminal of OPA2277A, the pin 1 of OPA2277A is connected with a resistor of 100 omega, and then the resistor of 2k omega is connected with the inverting input terminal to form a voltage follower, and VREF is obtained.
Has the advantages that:
first, the utility model relates to a strain signal synchronous acquisition simulation front end and reference circuit, MCU's functioning speed can come the apolegamy model according to sampling rate and passageway quantity, still can measure absolute voltage.
Secondly, the utility model discloses a strain signal synchronous acquisition simulation front end and reference circuit have two kinds of modes, and two kinds of modes can be switched over wantonly, and application scope is wider in the practical application; the method comprises the following specific steps:
the first mode is suitable for directly simulating synchronous acquisition of resources by using an MCU (microprogrammed control Unit), such as STM32G4 and STM32G7, wherein VREF and AVDD of the MCU use A3V3, VCOM uses 1V65, and the sampling rate is highest;
the second mode is suitable for external 5V work synchronous sampling ADC, such as ADS141A02, 04 of TI company, at this time, 2V5 is used for supplying AVDD and VREF to ADC, VCOM is 2V5, and the sampling rate is higher.
Drawings
Fig. 1 is a circuit diagram of the voltage input terminal in the strain signal synchronous acquisition analog front end and the reference circuit of the present invention.
Fig. 2 is a circuit diagram of the differential amplifier circuit in the strain signal synchronous acquisition analog front end and the reference circuit of the present invention.
Fig. 3 is a circuit diagram of the level shift module in the strain signal synchronous acquisition analog front end and the reference circuit of the present invention.
Fig. 4 is a circuit diagram of the reference circuit in the strain signal synchronous acquisition analog front end and the reference circuit of the present invention.
Fig. 5 is a circuit diagram of the switch selection module in the strain signal synchronous acquisition analog front end and the reference circuit of the present invention.
Fig. 6 is a circuit diagram of the external ADC reference unit in the strain signal synchronous acquisition analog front end and the reference circuit of the present invention.
Detailed Description
The following describes the present invention in further detail with reference to the attached drawings.
The strain signal synchronous acquisition analog front end and reference circuit in the specific embodiment comprises a voltage input end, a differential amplification circuit, a level translation module, a reference circuit, a switch selection module and an external ADC reference unit;
the voltage input terminal is coupled to AGND through filter capacitor EA3 by AVDD, AGND through filter capacitor CA3, and ground protection circuit by a zener diode, as shown in fig. 1, to generate INA + and INA-signals and VMID;
the differential amplifying circuit is composed of a double operational amplifier OPA2188, a plurality of resistors and a plurality of capacitors as shown in FIG. 2; the AIA + and AIA-signals are respectively input into a pin 5 and a pin 3 of an OPA2188, and a pin 2 of the OPA2188 is connected with 5 same resistors in series and connected to a pin 1 output terminal of the OPA 2818; the 6 pins are connected with 5 same resistors in series to the 7-pin output end of the OPA2118, a circuit formed by connecting 10 same resistors in parallel is connected between the 2 pins and the 6 pins, and therefore a differential amplification circuit is formed, and INA + and INA-are amplified;
the level shift module is composed of a dual operational amplifier OPA2277, a plurality of resistors and a plurality of capacitors, as shown in fig. 3; the output is carried out by pins 1 and 7 of the OPA2188, five resistors with the same resistance are respectively connected in series into pins 2 and 6 of the OPA2277, OUTA + is connected in series with five resistors with the same resistance into pin 2 of the OPA2277 to form negative feedback, pin 7 of the OPA2277 is connected in series with five resistors with the same resistance into pin 6 of the OPA2277 to form negative feedback, pin 3 and pin 5 of the OPA2277 are both connected with VCOM, and VCOM is grounded through a capacitor CA 18; according to the circuit symmetry characteristic, VCOM is equal to half of the sum of OUTA-and OUTA +, and level shifting can be realized by changing the value of VCOM; VMID and VC16 are connected in series with 6 resistors with the same resistance, one line is connected between the third resistor and the fourth resistor to obtain a VCOM value, and the obtained VCOM value is different due to the difference of VC16, namely level translation is realized;
the reference circuit is composed of an absolute ratio and a relative value circuit as shown in fig. 4; the absolute ratio circuit consists of an ADR03BR chip, a plurality of resistors and a plurality of capacitors; the 2 pin of the ADR03BR is connected with the AVDD, and then is coupled into the 4 pin of the ADR03BR through a parallel circuit formed by C1 and E1, and is grounded; the 6 pins of the ADR03BR are output ends, are connected with VR23 and are connected in series with 6 resistors with equal resistance to ground, VR16 is connected between the second resistor and the third resistor, VR12 is connected between the third resistor and the fourth resistor, namely three outputs with different voltage values are obtained, and the output ends are also connected with AGND through a parallel circuit formed by C2 and E2 in a coupling mode; the relative value circuit is formed by dividing voltage of a plurality of resistors, the AVDD provides voltage, 12 resistors with the same resistance value are connected in series and then connected with the AGND, the PM25 is connected between the sixth resistor and the seventh resistor, the PM16 is connected between the eighth resistor and the ninth resistor, and the PM12 is connected between the ninth resistor and the tenth resistor, so that three voltages with different amplitudes are provided;
the switch selection module is shown in fig. 5, and comprises a 3-way alternative analog switch chip 74HC4053 with a common enable input control bit, pins 9, 10 and 11 of the chip are connected with SMOD, pin 12 is connected with VR25, pin 13 is connected with PM25, pin 2 is connected with VR12, pin 1 is connected with PM12, pin 5 is connected with VR16, pin 3 is connected with PM16, pin 14 is connected with TP25, pin 16 is connected with TP12, and pin 4 is connected with TP16, so that voltage value selection is completed;
the ADC reference unit is composed of a 74HC4053 analog switch chip, a dual operational amplifier OPA2277, a plurality of resistors and a plurality of capacitors, as shown in fig. 6; a pin 3 of 74HC4053 is connected with TP16, a pin 5 is connected with TP25, a pin 4 is connected with a non-inverting input end of OPA2277B, a pin 7 of OPA2277B is connected with a resistor of 100 omega, and then a resistor of 2k omega is connected with an inverting input end to form a voltage follower, so that VC16 is obtained; the pin 13 of 74HC4053 is connected with TP12, the pin 12 is connected with TP25, the pin 14 is connected with the non-inverting input terminal of OPA2277A, the pin 1 of OPA2277A is connected with a resistor of 100 omega, and then the resistor of 2k omega is connected with the inverting input terminal to form a voltage follower, and VREF is obtained.
A description of the circuit principle for the two modes is given below:
in the first mode, the MCU is directly used for simulating synchronous acquisition of resources, such as STM32G4 and STM32G7, at the moment, VREF and AVDD of the MCU are used for A3V3, VCOM is used for 1V65, and the sampling rate is highest.
The mode utilizes the ADC carried by the MCU to process the output signal OUTA +/OUTA-, and the ADC has higher clock frequency, so the sampling rate is the highest compared with the other two. The 1.65V voltage VCOM required by the ADC is formed by serially connecting 6 resistors with the same resistance value with the VMID and the VC16, and a line is connected between the third resistor and the fourth resistor to obtain the value of VCOM, wherein the obtained value of VCOM is different due to the difference of VC 16. The 3.3V voltages VREF and AVDD will be provided by pin number 4 TP16 of 74HC 4053.
And in the second mode, the sampling ADC is suitable for external 5V work synchronous sampling, such as ADS141A02 and ADS 04 of TI company, at the moment, 2V5 is used for supplying power to AVDD and VREF by the ADC, VCOM is 2V5, and the sampling rate is higher.
The mode utilizes an external ADC to process an output signal OUTA +/OUTA-, and the ADC of the mode obtains an input signal from 4 analog front-end circuits with the same structure and separated mutually, so that multi-path strain signal measurement can be realized. The 2.5V voltage VCOM required by the ADC is formed by serially connecting 6 resistors with the same resistance value with the VMID and the VC16, and a line is connected between the third resistor and the fourth resistor to obtain the value of VCOM, wherein the obtained value of VCOM is different due to the difference of VC 16. The 2.5V voltages VREF and AVDD will be provided by pin number 14 TP25 of 74HC 4053.
Claims (1)
1. A strain signal synchronous acquisition analog front end and reference circuit is characterized in that: the voltage-level-shifting circuit is composed of a voltage input end, a differential amplifying circuit, a level shifting module, a reference circuit, a switch selection module and an external ADC reference unit;
the voltage input end is coupled to AGND through a filter capacitor EA3 by AVDD, coupled to AGND through a filter capacitor CA3, and passes through a zener diode ground protection circuit to generate INA + and INA-signals and VMID;
the differential amplifying circuit consists of a double operational amplifier OPA2188, a plurality of resistors and a plurality of capacitors; the AIA + and AIA-signals are respectively input into a pin 5 and a pin 3 of an OPA2188, and a pin 2 of the OPA2188 is connected with 5 same resistors in series and connected to a pin 1 output terminal of the OPA 2818; the 6 pins are connected with 5 same resistors in series to the 7-pin output end of the OPA2118, a circuit formed by connecting 10 same resistors in parallel is connected between the 2 pins and the 6 pins, and therefore a differential amplification circuit is formed, and INA + and INA-are amplified;
the level translation module consists of a dual operational amplifier OPA2277, a plurality of resistors and a plurality of capacitors; the output is carried out by pins 1 and 7 of the OPA2188, five resistors with the same resistance are respectively connected in series into pins 2 and 6 of the OPA2277, OUTA + is connected in series with five resistors with the same resistance into pin 2 of the OPA2277 to form negative feedback, pin 7 of the OPA2277 is connected in series with five resistors with the same resistance into pin 6 of the OPA2277 to form negative feedback, pin 3 and pin 5 of the OPA2277 are both connected with VCOM, and VCOM is grounded through a capacitor CA 18; according to the circuit symmetry characteristic, VCOM is equal to half of the sum of OUTA-and OUTA +, and level shifting can be realized by changing the value of VCOM; VMID and VC16 are connected in series with 6 resistors with the same resistance, one line is connected between the third resistor and the fourth resistor to obtain a VCOM value, and the obtained VCOM value is different due to the difference of VC16, namely level translation is realized;
the reference circuit consists of absolute contrast value and relative value circuits; the absolute ratio circuit consists of an ADR03BR chip, a plurality of resistors and a plurality of capacitors; a pin 2 of the ADR03BR is connected with AVDD, and is coupled into a pin 4 of the ADR03BR through a parallel circuit formed by C1 and E1 and is grounded; the 6 pins of the ADR03BR are output ends, are connected with VR23 and are connected in series with 6 resistors with equal resistance to ground, VR16 is connected between the second resistor and the third resistor, VR12 is connected between the third resistor and the fourth resistor, namely three outputs with different voltage values are obtained, and the output ends are also connected with AGND through a parallel circuit formed by C2 and E2 in a coupling mode; the relative value circuit is formed by dividing voltage of a plurality of resistors, the AVDD provides voltage, 12 resistors with the same resistance value are connected in series and then connected with the AGND, the PM25 is connected between the sixth resistor and the seventh resistor, the PM16 is connected between the eighth resistor and the ninth resistor, and the PM12 is connected between the ninth resistor and the tenth resistor, so that three voltages with different amplitudes are provided;
the switch selection module comprises a 3-path two-way alternative analog switch chip 74HC4053 with a common enable input control bit, pins 9, 10 and 11 of the chip are connected with SMOD, pins 12 are connected with VR25, pins 13 are connected with PM25, pins 2 are connected with VR12, pins 1 are connected with PM12, pins 5 are connected with VR16, pins 3 are connected with PM16, pins 14 and 16 are connected with TP25, pins 4 are connected with TP12 and pins 16, and voltage value selection is completed;
the ADC reference unit consists of a 74HC4053 analog switch chip, a double operational amplifier OPA2277, a plurality of resistors and a plurality of capacitors; a pin 3 of the 74HC4053 is connected with TP16, a pin 5 is connected with TP25, a pin 4 is connected with the non-inverting input end of the OPA2277B, a pin 7 of the OPA2277B is connected with a resistor of 100 ohms and then connected with a resistor of 2k ohms to be connected with the inverting input end to form a voltage follower, and VC16 is obtained; the pin 13 of 74HC4053 is connected with TP12, the pin 12 is connected with TP25, the pin 14 is connected with the non-inverting input terminal of OPA2277A, the pin 1 of OPA2277A is connected with a resistor of 100 omega, and then the resistor of 2k omega is connected with the inverting input terminal to form a voltage follower, and VREF is obtained.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220033512.8U CN216486180U (en) | 2022-01-08 | 2022-01-08 | Strain signal synchronous acquisition analog front end and reference circuit |
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| CN202220033512.8U CN216486180U (en) | 2022-01-08 | 2022-01-08 | Strain signal synchronous acquisition analog front end and reference circuit |
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| CN216486180U true CN216486180U (en) | 2022-05-10 |
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| CN202220033512.8U Expired - Fee Related CN216486180U (en) | 2022-01-08 | 2022-01-08 | Strain signal synchronous acquisition analog front end and reference circuit |
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Granted publication date: 20220510 |