CN216451451U - Multi-channel video and audio processing device - Google Patents

Abstract

The application relates to a multichannel audio processing apparatus that looks includes: a master card; the main card is provided with a line-field synchronous separation chip, a phase-locked clock generation chip, a clock debouncing chip and a processing chip, a reference input signal RFF IN is processed by the line-field synchronous separation chip, a travel synchronous signal and a field synchronous signal are extracted, and then the reference input signal RFF IN is sent to a later-stage phase-locked clock generation chip, a video coding clock required by later-stage SDI serial coding is generated by the reference input signal RFF IN according to the line-field synchronous signal and the field synchronous signal, and the clock signal after being debounced by the clock debounce chip is input to a special clock input port of the FPGA processing chip and is used for SDI coding output, so that the jitter index of an output signal is reduced. The plurality of first signal interfaces are adapted for input and output of signals.

Description

Multi-channel video and audio processing device

Technical Field

The application relates to the technical field of audio and video processing, in particular to a multi-channel video and audio processing device.

Background

With the rapid development and evolution of high definition to ultra high definition video and audio technology, the demand of international and domestic television and television industry clients and high-end clients in the field of professional video and audio editing on the processing capacity of ultra high definition video and audio materials is continuously improved. The manufacturers of the known professional video and audio equipment at home and abroad continuously provide own multi-channel ultra-high definition video and audio processing equipment. In terms of hardware circuit architecture design, the devices basically use the FPGA as a main processing chip, and are equipped with a DDR memory and a video/audio processing dedicated interface chip.

However, most of the multi-channel ultra-high definition video and audio processing equipment on the market at present have the problem that the jitter index of 12G SDI output signals exceeds the standard.

Disclosure of Invention

In view of the above, the present application provides a multi-channel video/audio processing apparatus capable of reducing jitter index of 12G SDI output signal.

According to an aspect of the present application, there is provided a multi-channel video and audio processing apparatus including:

a master card;

a line-field synchronous separation chip, a phase-locked clock generation chip, a clock debounce chip and an FPGA processing chip are integrated on the main card;

the input end of the line-field synchronous separation chip is suitable for receiving input signals, the output end of the line-field synchronous separation chip is electrically connected with the input end of the phase-locked clock generation chip, the output end of the phase-locked clock generation chip is electrically connected with the input end of the clock debounce chip, the output end of the clock debounce chip is electrically connected with the input end of the FPGA processing chip, and the output end of the FPGA processing chip is suitable for outputting processed signals;

the main card is also provided with a plurality of first signal interfaces, the input end of the line-field synchronous separation chip and the output end of the processing chip are electrically connected with the plurality of first signal interfaces, so that the line-field synchronous separation chip receives the input signals through the first signal interfaces, and the FPGA processing chip outputs the processed signals through the first signal interfaces.

IN one possible implementation, the plurality of first signals includes four 12G-SDI interfaces and one REF IN interface.

In a possible implementation manner, the system further comprises a first sub-card and a second sub-card;

the first sub card and the second sub card are both electrically connected with the main card;

the first daughter card is configured with a plurality of second signal interfaces;

the plurality of second signal interfaces are electrically connected with the main card, so that the line-field synchronous separation chip on the main card receives the input signal through an input interface in the plurality of second signal interfaces, and the FPGA processing chip outputs the processed signal through an output interface in the plurality of second signal interfaces;

the second sub card is configured with a first expansion interface and a second expansion interface;

the first expansion interface and the second expansion interface are electrically connected with the main card.

In one possible implementation manner, the first daughter card is electrically connected with the main card through a high-speed signal board-to-board connector;

the second daughter card is electrically connected with the main card through a signal cable.

In one possible implementation, the plurality of second signal interfaces includes a four-way 3G-SDI interface, an HDMI input interface, and an HDMI output interface.

In a possible implementation manner, the second daughter card is further configured with a first interface extender and a second interface extender;

the first interface expander is matched with the first expansion interface and is expanded with a plurality of audio interfaces;

the second interface expander is matched with the second expansion interface, and the second interface expander is also expanded with a plurality of audio interfaces and video interfaces.

In one possible implementation, the plurality of audio interfaces extended by the first interface extender includes: four analog audio input interfaces and six analog audio output interfaces.

In one possible implementation, the plurality of audio interfaces and video interfaces extended by the second interface extender include: the device comprises a composite video signal input port, a composite video signal output port, a component input interface, a component output interface, a component video signal input interface, a component video output interface, a four-way digital audio input port and a four-way digital audio output port.

In a possible implementation manner, the main card is further provided with a TALLY interface and an earphone monitoring output interface;

the TALLY interface and the earphone monitoring output interface are electrically connected with the output end of the FPGA processing chip.

In one possible implementation, the first expansion interface and the second expansion interface are both DB26 interfaces.

The utility model adopts the clock scheme of the 3G SDI interface, a reference input signal RFF IN is processed by a line-field synchronization separation chip, a line synchronization signal and a field synchronization signal are extracted, then the extracted line synchronization signal and the extracted field synchronization signal are sent to a subsequent phase-locked clock generating chip, a video coding clock required by the subsequent SDI serial coding is generated by the reference input signal RFF IN according to the line-field synchronization signal and the field synchronization signal and is sent to a special clock input port of a processing chip, and then a serial high-speed clock is generated by a clock phase-locked loop IN a high-speed transceiver of the processing chip and is used for outputting the final SDI coding. The jitter indicator of the SDI encoded output signal is primarily related to the quality of the clock signal input to the dedicated clock input port of the high-speed transceiver. However, in the process of processing the 12G SDI signal, the phase noise table of the clock signal generated by the phase-locked clock generating chip is large, and the requirement of the 12G SDI signal on the quality of the clock signal cannot be met. Therefore, the utility model adds a clock jitter removal chip behind the 27-megaclock signal output by the phase-locked clock generation chip. The clock signal after being subjected to jitter removal by the clock jitter removal chip is input into a special clock input port of the processing chip and is used for SDI coding output, and then the jitter index of the output signal is reduced. The plurality of first signal interfaces are adapted for input and output of signals.

Other features and aspects of the present application will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the application and, together with the description, serve to explain the principles of the application.

Fig. 1 is a main body structure diagram of a multi-channel audio/video processing apparatus according to an embodiment of the present application;

fig. 2 shows a schematic diagram of an input signal processing process according to an embodiment of the present application.

Detailed Description

Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

It will be understood, however, that the terms "central," "longitudinal," "lateral," "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in an orientation or positional relationship indicated in the drawings for convenience in describing or simplifying the description, and do not indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the utility model.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present application. It will be understood by those skilled in the art that the present application may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present application.

Fig. 1 is a diagram illustrating a main body structure of a multi-channel video/audio processing apparatus according to an embodiment of the present application. FIG. 2 shows an input signal processing flow diagram according to an embodiment of the present application. As shown in fig. 1 and 2, the multi-channel video/audio processing apparatus includes: the main card 100 is integrated with a line-field synchronization separation chip 110, a phase-locked clock generation chip 120, a clock debounce chip 130 and an FPGA processing chip 140. The input end of the line-field synchronous separation chip 110 is adapted to receive an input signal, the output end of the line-field synchronous separation chip 110 is electrically connected to the input end of the phase-locked clock generation chip 120, the output end of the phase-locked clock generation chip 120 is electrically connected to the input end of the clock debounce chip 130, the output end of the clock debounce chip 130 is electrically connected to the input end of the FPGA processing chip 140, and the output end of the FPGA processing chip 140 is adapted to output a processed signal. The main card 100 is further configured with a plurality of first signal interfaces 150, the input end of the line-field synchronization separation chip 110 and the output end of the FPGA processing chip 140 are electrically connected to the plurality of first signal interfaces 150, so that the line-field synchronization separation chip 110 receives an input signal through the first signal interfaces 150, and the FPGA processing chip 140 outputs a processed signal through the first signal interfaces 150.

The utility model adopts the clock scheme of the 3G SDI interface, as shown IN fig. 2, a reference input signal RFF IN is processed by a line-field synchronization separation chip 110, then a line synchronization signal and a field synchronization signal are extracted, and then the extracted signals are sent to a rear-stage phase-locked clock generation chip 120, a video coding clock required by the rear-stage SDI serial coding is generated by the reference input signal RFF IN according to the line-field synchronization signal and the field synchronization signal and is sent to a special clock input port of an FPGA processing chip 140, and then a clock phase-locked loop IN a high-speed transceiver of the processing chip 140 generates a serial high-speed clock for outputting the final SDI coding. The jitter indicator of the SDI encoded output signal is primarily related to the quality of the clock signal input to the dedicated clock input port of the high-speed transceiver. However, in the process of processing the 12G SDI signal, the phase noise table of the clock signal generated by the phase-locked clock generating chip 120 is large, which cannot meet the requirement of the 12G SDI signal on the quality of the clock signal. Therefore, the present invention adds a clock debounce chip 130 after the 27 mega clock signal outputted from the phase-locked clock generating chip 120. The clock signal after being dithered by the clock dither elimination chip 130 is input to the special clock input port of the FPGA processing chip 140 for SDI encoding output, thereby reducing the dither index of the output signal. The plurality of first signal interfaces 150 are adapted for input and output of signals.

Here, it should be noted that the clock debounce chip 130 may employ a chip LMK03328, and the chip LMK03328 is an ultra-low noise clock generator having two fractional-N frequency synthesizers, an integrated VCO, flexible clock distribution, and fan-out. The device can generate a plurality of clocks for various trillion serial interfaces and digital equipment, thereby reducing BOM cost and board occupation area, replacing a plurality of oscillators and clock distribution devices and improving the running reliability of the system. Its ultra-low jitter performance reduces the bit error rate in high-speed serial links.

IN one possible implementation, the plurality of first signal interfaces 150 are a four-way 12G-SDI interface and a one-way REF IN interface, respectively. The four-path 12G-SDI interface is suitable for transmitting 12G-SDI signals, the REF IN interface is suitable for transmitting reference input signals, and the four-path 12G-SDI interface can be input or output so as to meet various application scene requirements of clients IN the broadcast television industry and high-end clients IN the field of professional video and audio editing.

In one possible embodiment, a first daughter card 200 and a second daughter card 300 are also included. The first daughter card 200 and the second daughter card 300 are electrically connected to the master card 100. Wherein the first daughter card 200 is configured with a plurality of second signal interfaces 210. The plurality of second signal interfaces 210 are electrically connected to the main card 100, so that the line-field synchronous separation chip 110 on the main card 100 receives an input signal through an input interface of the plurality of second signal interfaces 210, and the FPGA processing chip 140 outputs a processed signal through an output interface of the plurality of second signal interfaces 210. The second daughter card 300 is configured with a first extended interface 330 and a second extended interface 340. The first expansion interface 330 and the second expansion interface 340 are electrically connected to the main card 100. Through setting up first daughter card 200 and second daughter card 300 for set up each signal input output interface and each electronic components respectively, make the space utilization more reasonable, reduce the equipment volume.

In one possible implementation, the plurality of second signal interfaces 210 includes a four-way 3G-SDI interface, an HDMI input interface, and an HDMI output interface. The application range of the application is expanded.

In one possible embodiment, the second daughter card 300 is further configured with a first interface extender 310 and a second interface extender 320; the first interface expander 310 is matched with the first expansion interface 330, and the first interface expander 310 is expanded with a plurality of audio interfaces 311; the second interface extender 320 is matched with the second extension interface 340, and the second interface extender 320 is also extended with a plurality of audio and video interfaces 321. The type of signal interface adapted by the present application is further expanded by providing a first interface extender 310 and a second interface extender 320.

In one possible implementation, the plurality of audio interfaces 311 extended by the first interface extender includes: four analog audio input interfaces and six analog audio output interfaces. The second interface extender 321 also extends a plurality of audio and video interfaces including: the device comprises a composite video signal input port, a composite video signal output port, a component input interface, a component output interface, a component video signal input interface, a component video output interface, a four-way digital audio input port and a four-way digital audio output port. Further expanding the application scope of the application.

Here, it should be noted that the fourth digital audio input port and the fourth digital audio output port are also capable of inputting and outputting LTC signals, respectively.

In a possible implementation, the main card 100 is further provided with a talely interface 170 and an earphone listening output interface 180; the TALLY interface 170 and the earphone monitoring output interface 180 are both electrically connected with the output end of the FPGA processing chip 140. Further expanding the application scope of the application.

In one possible implementation, the first expansion interface 330 and the second expansion interface 340 are both DB26 interfaces. Overall structure is comparatively simple, the effectual manufacturing cost that has reduced.

Here, it should be noted that the signal cable 400 is further included, and cable plugs are provided at both ends of the signal cable 400. The main card 100 and the first sub card 200 are respectively provided with a first cable interface 190 and a second cable interface 350, and two cable plugs are respectively matched with the first cable interface 190 and the second cable interface 350. The input end of the line-field synchronization separation chip 110 and the output end of the processing chip 140 are electrically connected to the first cable interface 190, so as to electrically connect the second daughter card 300 to the main card 100. Two signal cables 400 are provided, and two corresponding first cable interfaces 190 and two corresponding second cable interfaces 350 are provided, so as to increase the signal transmission speed between the main card 100 and the second daughter card 300. Both signal cables 400 are 50-core signal cables 400.

Here, the high-speed signal board-to-board connector interface 160 and the high-speed signal board-to-board connector plug 220 are respectively provided on two opposite sides of the main card 100 and the first sub-card 200. The main card 100 is provided with a plurality of first positioning holes, the first sub-card 200 is provided with a plurality of second positioning holes, the number of the second positioning holes is equal to that of the first positioning holes, the second positioning holes correspond to the first positioning holes one by one, and the positioning columns penetrate through the first positioning holes and the second positioning holes by arranging the positioning columns between the first positioning holes and the second positioning holes which are oppositely arranged, so that the limiting effect on the main card 100 and the first sub-card 200 is achieved, and further the connection of the connector between the high-speed signal boards is stable.

Here, it should be noted that the line-field synchronization separation chip 110 is an LMH1981 chip, the phase-locked clock generation chip 120 is an LMH1983 chip, different types of input signals are respectively input from different pins of the LMH1981 chip for processing, and the processed different types of signals are output through different pins of the FPGA processing chip 140.

That is to say, in the video and audio processing apparatus according to the embodiment of the present application, by setting one RB8 master card and a series of daughter cards, the combination of the master card and each daughter card can meet the needs for the functions of the board card in different scenarios. Specifically, the system comprises an RB8S _ BASE card, an HDMI20_ SDI4X _ SUB card and a VAOP card. The external interface types and the external number specifically include:

a 4-way 12GSDI (all configurable as either an input or an output);

a 4-way 3GSDI (all configurable as either input or output);

1 path of HDMI2.0 output and 1 path of HDMI2.0 input;

1 way REF IN; 12-way TALLY/GPIO;

1 path of CVBS input and 1 path of CVBS output;

1 path of YC input and 1 path of YC output;

1 path of YUV input and 1 path of YUV output;

4 analog audio inputs and 6 analog audio outputs;

4 paths of AES digital audio input and 4 paths of AES digital audio output;

1 way LTC input (same physical interface multiplexed with 4 th way AES digital audio input);

1 path of LTC output (the same physical interface is multiplexed with the 4 th path of AES digital audio output);

and 1 earphone monitors the output.

More specifically, the configuration combination connection mode of the device is shown in fig. 1. The RB8S _ BASE card is the main card 100, and the main processing chip FPGA is on this card and is responsible for performing the main video and audio data processing function. The external signal interface on the card comprises: a 4-way 12GSDI (all configurable as inputs or outputs); 1 way REF IN; 12-way TALLY/GPIO; and 1 earphone monitors the output.

The HDMI20_ SDI4X _ SUB card (i.e., the first daughter card 200) is a card clip, and is connected and fixed with the RB8S _ BASE card through a high-speed signal board-to-board connector and a fixing copper column. The external signal interface on the card comprises: a 4-way 3GSDI (all configurable as either input or output); a 1-way HDMI2.0 output and a 1-way HDMI2.0 input.

The VAOP card (i.e., the second daughter card 300) is a daughter card connected to RB8S _ BASE card by two 50-core signal cables. The external signal interface on the card comprises: 1 path of CVBS input and 1 path of CVBS output; 1 path of YC input and 1 path of YC output; 1 path of YUV input and 1 path of YUV output; 4 analog audio inputs and 6 analog audio outputs; 4 paths of AES digital audio input and 4 paths of AES digital audio output; 1 way LTC input (same physical interface multiplexed with 4 th way AES digital audio input); 1 way LTC output (multiplexing same physical interface with 4 th way AES digital audio output).

Having described embodiments of the present application, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (10)

1. A multi-channel video/audio processing apparatus, comprising:

a master card;

a line-field synchronous separation chip, a phase-locked clock generation chip, a clock debounce chip and an FPGA processing chip are integrated on the main card;

the input end of the line-field synchronous separation chip is suitable for receiving input signals, the output end of the line-field synchronous separation chip is electrically connected with the input end of the phase-locked clock generation chip, the output end of the phase-locked clock generation chip is electrically connected with the input end of the clock jitter removal chip, the output end of the clock jitter removal chip is electrically connected with the input end of the FPGA processing chip, and the output end of the FPGA processing chip is suitable for outputting processed signals;

the main card is also provided with a plurality of first signal interfaces, the input end of the line-field synchronous separation chip and the output end of the processing chip are electrically connected with the plurality of first signal interfaces, so that the line-field synchronous separation chip receives the input signals through the first signal interfaces, and the FPGA processing chip outputs the processed signals through the first signal interfaces.

2. The multi-channel audio-visual processing device of claim 1, wherein the plurality of first signals includes four 12G-SDI interfaces and one REF IN interface.

3. The multi-channel audio-visual processing device according to claim 1, further comprising a first sub-card and a second sub-card;

the first sub card and the second sub card are both electrically connected with the main card;

the first daughter card is configured with a plurality of second signal interfaces;

the plurality of second signal interfaces are electrically connected with the main card, so that the line-field synchronous separation chip on the main card receives the input signal through an input interface in the plurality of second signal interfaces, and the FPGA processing chip outputs the processed signal through an output interface in the plurality of second signal interfaces;

the second sub card is configured with a first expansion interface and a second expansion interface;

the first expansion interface and the second expansion interface are electrically connected with the main card.

4. The multi-channel audio-visual processing device according to claim 3, wherein the first daughter card is electrically connected to the main card through a high-speed signal board-to-board connector;

the second daughter card is electrically connected with the main card through a signal cable.

5. The multi-channel audio-visual processing device of claim 4, wherein the plurality of second signal interfaces includes a four-way 3G-SDI interface, an HDMI input interface, and an HDMI output interface.

6. The multi-channel audio-visual processing device of claim 4, wherein the second daughter card is further configured with a first interface extender and a second interface extender;

the first interface expander is matched with the first expansion interface and is expanded with a plurality of audio interfaces;

the second interface expander is matched with the second expansion interface, and the second interface expander is also expanded with a plurality of audio interfaces and video interfaces.

7. The multi-channel audio-visual processing device according to claim 6, wherein the plurality of audio interfaces extended by the first interface extender include: four analog audio input interfaces and six analog audio output interfaces.

8. The multi-channel audio-visual processing device according to claim 6, wherein the plurality of audio interfaces and video interfaces extended by the second interface extender include: the device comprises a composite video signal input port, a composite video signal output port, a component input interface, a component output interface, a component video signal input interface, a component video output interface, a four-way digital audio input port and a four-way digital audio output port.

9. The multi-channel video and audio processing device according to claim 1, wherein the main card is further provided with a talely interface and an earphone listening output interface;

the TALLY interface and the earphone monitoring output interface are electrically connected with the output end of the FPGA processing chip.

10. The multi-channel audio-visual processing device according to claim 3, wherein the first expansion interface and the second expansion interface are both DB26 interfaces.

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