CN216436881U

CN216436881U - Balanced dual-power supply circuit

Info

Publication number: CN216436881U
Application number: CN202220010614.8U
Authority: CN
Inventors: 翟让海
Original assignee: Fiberhome Telecommunication Technologies Co Ltd
Current assignee: Fiberhome Telecommunication Technologies Co Ltd
Priority date: 2022-01-05
Filing date: 2022-01-05
Publication date: 2022-05-03
Anticipated expiration: 2032-01-05

Abstract

The embodiment of the application discloses balanced dual power supply's circuit relates to the technical field of two DC power supply power supplies, includes: the two switch branches comprise NMOS switch tubes and driving devices for driving the NMOS switch tubes to be turned off, the drain electrodes of the two NMOS switch tubes are both configured to be connected with the grounding end of a load R, the source electrodes are respectively configured to be connected with the power grounding end of one circuit, and the control logics of the two driving devices are opposite; and the control unit is configured to output a Pulse Width Modulation (PWM) signal to the two driving devices so as to synchronously trigger one driving device to drive one NMOS switching tube to be switched on, drive the other NMOS switching tube to be switched off, and enable one of the two power supplies and the load R to form a power supply loop. The embodiment of the application realizes balanced power supply of the double power supplies and improves the stability and reliability of the double power supplies.

Description

Balanced dual-power supply circuit

Technical Field

The application relates to the technical field of double direct current power supply, in particular to a balanced dual-power supply circuit.

Background

With the rapid development of economy, many power devices often use main and standby dual power supplies to supply power in order to ensure the stability of power supply. Namely, the main power supply supplies power to the load under normal conditions, and the standby power supply is started under emergency conditions.

However, when the main and standby dual power supplies are switched, voltage jitter is easily generated on the power supply line, which reduces the reliability of power supply of the power supply. And the main power supply is in a full-load power supply state for a long time, the power supply is heated and aged, the power supply reliability of the power supply is reduced, the service life of the power supply is shortened, and the problem of unbalanced power supply of the main and standby dual power supplies is caused.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a balanced dual-power supply circuit to solve the reliability problem of dual-power supply in the related art.

The embodiment of the application provides a balanced dual power supply's circuit, includes:

the two switch branches comprise NMOS switch tubes and driving devices for driving the NMOS switch tubes to be turned off, the drain electrodes of the two NMOS switch tubes are both configured to be connected with the grounding end of a load R, the source electrodes are respectively configured to be connected with the power grounding end of one circuit, and the control logics of the two driving devices are opposite;

and the control unit is configured to output a Pulse Width Modulation (PWM) signal to the two driving devices so as to synchronously trigger one driving device to drive one NMOS switching tube to be switched on, drive the other NMOS switching tube to be switched off, and enable one of the two power supplies and the load R to form a power supply loop.

In some embodiments, the control unit comprises:

and the PWM port is configured to output a Pulse Width Modulation (PWM) signal with adjustable duty ratio and is connected with the control terminals of the two driving devices.

In some embodiments, further comprising:

one end of the detection branch is connected with the two corresponding power supplies through the two switch branches, and the other end of the detection branch is configured to supply power to the load R; at the same time, the user can select the desired position,

the control unit is also electrically connected with the detection branch and used for adjusting the output PWM signal according to the current acquired by the detection branch.

In some embodiments, the switching leg further comprises:

two ends of one resistor are correspondingly connected with the source electrode and the grid electrode of the NMOS switch tube; one end of the other resistor is configured to be connected with a power supply, and the other end of the resistor is connected with the grid electrode of the NMOS switch tube.

In some embodiments, the switching leg further comprises:

a first capacitor, one end of which is configured to be connected with the output end of a power supply, and the other end of which is configured to be connected with the ground end of the power supply; and/or

And the anode of the diode is configured to be connected with a power supply, and the cathode of the diode is connected with the cathode of the diode in the other switching branch in parallel and then configured to supply power to the load R.

In some embodiments, the control unit further comprises:

and one GPIO port which is connected with the control ends of the two driving devices and is configured to output GPIO signals enabling the other driving device to drive the other NMOS switch tube to be also conducted.

In some embodiments, the GPIO signals include a high level signal, a low level signal, and a high impedance signal, and the switching branch further includes:

one end of the first resistor is connected with the PWM port, and the other end of the first resistor is connected with the control end of one driving device;

one end of the second resistor is used for being connected with the GPIO port, and the other end of the second resistor is used for being connected with the control end of one driving device;

meanwhile, the resistance value of the second resistor is smaller than that of the first resistor.

In some embodiments, the driving device comprises an optocoupler device, and further comprises at least one of a field effect transistor, a triode, or an inverter.

In some embodiments, the driving device comprises a triode and an optocoupler.

In some embodiments, the first end of the triode is connected with the control unit, the positive input end of the optocoupler is connected with a control voltage, the positive output end of the optocoupler is connected with the gate of the NMOS switching tube, and the negative output end of the optocoupler is connected with the power ground; at the same time, the user can select the desired position,

in one switching branch, the second end of the triode is connected with the negative input end of the optocoupler, and the third end of the triode is grounded;

in another switch branch, the second end of the triode is connected with the positive input end of the optocoupler, the third end of the triode is grounded, and the negative input end of the optocoupler is grounded.

The beneficial effect that technical scheme that this application provided brought includes: the balanced power supply of the double power supplies is realized, and the stability and the reliability of the power supply of the double power supplies are improved.

The embodiment of the application provides a balanced dual-power-supply circuit, which is used for providing two paths of power supplies for a load R and comprises a control unit and two switch branches; the switch branch comprises an NMOS switch tube and a driving device for driving the NMOS switch tube to be switched off; the drain electrodes of the two NMOS switching tubes are all configured to be connected with the grounding end of a load R, the source electrodes are respectively configured to be connected with a power ground end, and the control logics of the two driving devices are opposite; the control unit is configured to output a Pulse Width Modulation (PWM) signal to the two driving devices, and the control unit sends out a PWM signal due to the fact that control logics of the two driving devices are opposite, and the two driving devices can be alternately switched on no matter in a high level period or a low level period, so that one driving device is synchronously triggered to drive one N-channel metal oxide semiconductor (NMOS) switching tube to be switched on, the other driving device drives the other NMOS switching tube to be switched off, one of the two power supplies and a load R form a power supply loop, and the load R is always electrified. Therefore, according to the embodiment of the application, the two NMOS switching tubes are controlled to be switched on or switched off simultaneously by one PWM signal, so that the dual power supplies can be balanced, the voltage jitter problem during switching of the two power supplies can be effectively solved, and the power supply received by the load R is stable and reliable.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a circuit diagram of a circuit for equalizing dual power supply according to an embodiment of the present disclosure;

fig. 2 is a circuit diagram of another balanced dual power supply circuit according to an embodiment of the present disclosure.

The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The flow diagrams depicted in the figures are merely illustrative and do not necessarily include all of the elements and operations/steps, nor do they necessarily have to be performed in the order depicted. For example, some operations/steps may be decomposed, combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.

The embodiment of the application provides a balanced dual power supply circuit, realizes the balanced power supply of dual power, improves dual power supply's stability and reliability.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

Referring to fig. 1, an embodiment of the present application discloses a circuit for balancing dual power supplies, including:

In the embodiment of the application, when the load R is powered by two power supplies, the output terminals VCC _1 and VCC _2 of the two power supplies, the ground terminals VSS _1 and VSS _2 of the two power supplies, and the two NMOS switching tubes NMOS _1 and NMOS _2, the power input terminal of the load R is connected to the output terminals VCC _1 and VCC _2 of the two power supplies, and the currents output by VCC _1 and VCC _2 are respectively sent to the drain electrodes of NMOS _1 and NMOS _2 through the load R. If the NMOS _1 is conducted, the current output by the VCC _1 flows to VSS _1 from the source electrode of the NMOS _1 to form a power supply loop, and the VCC _1 supplies power to a load R; if the NMOS _2 is conducted, the current output by the VCC _2 flows to VSS _2 from the source electrode of the NMOS _2 to form another power supply loop, and the VCC _2 supplies power to a load R; if the NMOS _1 is cut off, the current output by the VCC _1 is cut off between the grounding end of the load R and the VSS _1, and the VCC _1 can not supply power to the load R; when NMOS _2 is turned off, the current output from VCC _2 is cut off between the ground terminal of load R and VSS _2, and VCC _2 cannot supply power to load R.

The NMOS _1 and the NMOS _2 are driven and controlled by the driving devices in the switch branches where the NMOS _1 and the NMOS _2 are located, the control unit outputs a Pulse Width Modulation (PWM) signal, namely a duty ratio, the two driving devices receive the PWM signal, and the two driving devices are triggered by the PWM signal to alternately turn on the corresponding NMOS switch tubes at the same time due to the fact that the control logics of the two driving devices are opposite, so that the NMOS switch tubes are turned on and off to supply power to the load R through one power supply.

For example, if the NMOS _1 is turned on, the NMOS _1 controls the current output by the power source VCC _1 to flow back to the power ground VSS _1 from the ground terminal of the load R, so that the power source VCC _1 supplies power to the load R. If the NMOS _1 is turned off and the ground terminal of the load R is disconnected from the power ground terminal VSS _1, the power VCC _1 cannot supply power to the load R. The ground terminal is a signal control ground terminal in this embodiment.

Compared with the on-off of the control voltage of the PMOS switching tube, the NMOS switching tube has smaller on-resistance RDS, the power supply loss is smaller, and the efficiency is higher.

Further, the control unit includes:

In the embodiment of the application, two paths of power supplies alternately supply power for the load R, the on-time proportion of the NMOS _1 and the NMOS _2 can be controlled by changing the duty ratio, the balance of dual-power supply is realized, and the hidden trouble caused by excessive heating of a certain power supply is avoided. Under normal conditions, the duty ratio is kept at 50%, and then the two paths of power supplies can be enabled to supply power in a balanced manner; keeping the duty ratio at 0 or 100% can realize that one of the two power supplies power for a long time, and the other power supply does not supply power for a long time.

As a preferred embodiment of the embodiments of the present application, the method further includes:

In this embodiment, the detection branch specifically includes a current detection resistor Rt, one end of the current detection resistor Rt is connected to the output ends of the two power supplies, the other end is connected to one end of a load R, and the other end of the load R is connected to the drains of the two NMOS switching tubes.

In the embodiment of the application, the output ends of two power supplies are connected with a load R through a current detection resistor Rt, when a load current passes through the current detection resistor Rt, voltage drops are generated at the two ends of the current detection resistor Rt, a detection branch acquires the load current through detecting the voltage drops and sends the load current to a control unit, and the control unit controls the duty ratio of output to be 0 or 100% after determining that the acquired current exceeds a set current threshold value, so that a circuit where one power supply is located forms a complete power supply loop to further realize continuous power supply.

It is worth noting that after each power supply with the same initial parameters is used for a long time, the voltage, temperature, fluctuation, surge, fault and other information of each power supply can be changed, in order to better ensure the stable reliability of the power supply, the duty ratio output by the control unit can be changed according to the comprehensive state of the power supply, so as to control the power supply conditions of the two power supplies, properly reduce the power supply time of the power supply with the poor comprehensive state of the power supply, and not only enable the output of the total power supply to be stable and reliable, but also prolong the service life of the power supply.

The evaluation of the comprehensive state of the power supply can be determined according to any evaluation form in the prior art. After the evaluation result of the power supply comprehensive state of the two power supplies is determined, the duty ratio is adjusted according to the evaluation result to distribute the power supply proportion of the two power supplies, and the adjustment form can be implemented according to the conventional technical means, and is not described in detail herein. The embodiment of the application fully considers the current situation of the power supply, and avoids the risk of increasing the power supply damage caused by continuous power supply when the comprehensive state of the power supply is not good.

Further, the switching branch further comprises:

two ends of one resistor are correspondingly connected with the source electrode and the grid electrode of the NMOS switch tube, one end of the other resistor is configured to be connected with a power supply, and the other end of the other resistor is connected with the grid electrode of the NMOS switch tube.

Still further, the driving device includes an optocoupler device, and further includes at least one of a field effect transistor, a triode, or an inverter.

Still further, the driving device includes a triode and an optocoupler.

Furthermore, the first end of the triode is connected with the control unit, the positive input end of the optocoupler is connected with a control voltage, the positive output end of the optocoupler is connected with the grid electrode of the NMOS switching tube, and the negative output end of the optocoupler is connected with the power ground; at the same time, the user can select the required time,

In this embodiment, if the triode is NPN type, the first terminal is a base, the second terminal is a collector, and the third terminal is an emitter; if the triode is of a PNP type, the first end is a base electrode, the second end is an emitting electrode, and the third end is a collector electrode.

In a specific embodiment, the driving device is mainly formed by combining a triode and an optocoupler, the triode is of NPN type, and the optocoupler isolates a control signal ground from a power ground, where the control signal ground is also the ground. If the driving device is conducted in a high level mode, the collector electrode of the triode is connected with the negative input end of the optocoupler; if the driving device is conducted at a low level, the collector of the triode is connected with the positive input end of the optocoupler, and the negative input end of the optocoupler is grounded.

Specifically, in one switching branch, the driving device includes a first NPN-type transistor Q1 and a first optocoupler OC1, and the one switching branch further includes a resistor R4, a resistor R5, and a resistor R6. One end of the resistor R4 is connected with a control voltage V _ PLL, the size of the control voltage V _ PLL can ensure that the input end of a first optical coupler OC1 is normally conducted, the other end of the resistor R4 is connected with the positive input end of the first optical coupler OC1, the negative input end of the first optical coupler OC1 is connected with the collector of the first triode Q1, the negative output end of the first optical coupler OC1 is connected with a power ground VSS _1, the positive output end of the first optical coupler OC1 and the grid of the NMOS _1 are connected with the resistor R5 and the resistor R6, the other end of the resistor R5 is connected with the power VCC _1, the other end of the resistor R6 is connected with the source electrode of the NMOS _1 and the power ground VSS _1, the base electrode of the first triode Q1 is connected with the PWM port, and the emitter electrode of the first triode Q1 is grounded.

In another switching branch, the driving device includes a second triode Q2 of NPN type and a second optocoupler OC2, the switching branch further includes a resistor R4 ', a resistor R5', a resistor R6 ', one end of the resistor R4' is connected to a control voltage V _ PLL, the control voltage V _ PLL is of a size that ensures that the input end of the second optocoupler OC2 is normally turned on, the other end of the resistor R4 'is connected to a positive input end of the second optocoupler OC2 and a collector of the second triode Q2, a negative input end of the second optocoupler OC2 is connected to an emitter of the second triode Q2, a positive output end of the second optocoupler OC2 is connected to a gate of NMOS _2, the resistor R5', and a resistor R6 ', a negative output end of the second optocoupler OC2 is connected to a power ground VSS _2, a base of the second triode Q2 is connected to the control unit, and the other end of the resistor R5' is connected to a power supply VCC _2, the other end of the resistor R6' is connected to a power ground VSS _ 2.

It is particularly noted that the signal control ground and the power ground VSS _1 and the power ground VSS _2 need to be isolated from each other.

Specifically, the resistance of the resistor R4 is 1k Ω, the resistance of the resistor R5 is 10k Ω, the resistance of the resistor R6 is 10k Ω, the resistance of the resistor R4 ' is 1k Ω, the resistance of the resistor R5 ' is 10k Ω, and the resistance of the resistor R6 ' is 10k Ω.

The control principle of the PWM signal output by the control unit in the present application is explained below with reference to specific embodiments.

The control unit outputs a Pulse Width Modulation (PWM) signal, namely a duty ratio, and the first triode Q1 and the second triode Q2 are NPN type; one end of a load R is connected with output ends VCC _1 and VCC _2 of the two power supplies, the other end of the load R is connected with drains of NMOS _1 and NMOS _2, a source electrode of the NMOS _1 is connected with a power ground terminal VSS _1, a source electrode of the NMOS _2 is connected with the power ground terminal VSS _2, a grid electrode of the NMOS _1 is connected with a forward output end of a first optical coupler OC1, and a grid electrode of the NMOS _2 is connected with a forward output end of a second optical coupler OC 2.

If the first triode Q1 and the second triode Q2 both receive low level signals, the first triode Q1 is cut off, the input end of the first optocoupler OC1 is not connected, the output end of the first optocoupler OC1 is cut off, the gate voltage of the NMOS _1 is VCC _1, and the gate voltage is divided by R5 and R6 to obtain a high level, and VGS of the NMOS _1 is a high level, so that the NMOS _1 is connected, that is, a line from the load R to the power ground terminal VSS _1 is connected, a loop is formed from the output end VCC _1 of one power supply to the power ground terminal VSS _1, and the power supply supplies power to the load R; the second triode Q2 ends, and the collector is high level, and this collector connects the positive input end of second opto-coupler device OC2, and the input of second opto-coupler device OC2 switches on, and the output switches on, and NMOS _ 2's grid voltage is the low level, and NMOS _ 2's VGS is 0 level, and consequently NMOS _2 ends, and then makes load R to the circuit disconnection of power ground terminal VSS _ 2.

Similarly, if the first transistor Q1 and the second transistor Q2 both receive a high level signal and are turned on, the first optocoupler OC1 is turned on, the NMOS _1 is turned off, the second optocoupler OC2 is turned off, the NMOS _2 is turned on, the line from the load R to the power ground VSS _1 is disconnected, and the line from the load R to the power ground VSS _2 is turned on.

Furthermore, the triode in the driving device can be replaced by a field effect transistor with the same control logic, namely the NPN type triode is replaced by an N-channel field effect transistor, the PNP type triode is replaced by a P communication field effect transistor, and the emitter of the triode is equivalent to the source of the N-channel field effect transistor, the collector is equivalent to the drain, and the base is equivalent to the grid no matter what type of triode is. The connection between the transistor and the fet is well known to those skilled in the art and will not be described in detail herein.

Preferably, the switching branch further comprises:

and one end of the first capacitor is configured to be connected with the output end of a power supply, and the other end of the first capacitor is configured to be connected with the ground end of the power supply.

In one embodiment, one switching branch further includes a first capacitor C1, and the other switching branch further includes a first capacitor C1', one end of the first capacitor C1 is connected to the output terminal VCC _1 of one power supply, and the other end is grounded; one end of the first capacitor C1' is connected to the output terminal VCC _2 of one power supply, and the other end is grounded. The first capacitor C1 and the first capacitor C1' are used as energy storage capacitors to smooth fluctuations during power switching.

Preferably, the switching branch further comprises:

In one embodiment, one switch branch further comprises a diode D1, and the other switch branch further comprises a diode D1 ', the anode of the diode D1 is connected to the output terminal VCC _1 of one power supply, the anode of the diode D1 ' is connected to the output terminal VCC _2 of one power supply, the cathodes of the diode D1 and the diode D1 ' are both connected to the load R, and a diode is respectively arranged between the output terminals of the two power supplies and the load R, so that the two power supplies can be effectively prevented from flowing backwards, and the stability and reliability of the dual power supply can be improved.

Still further, one end of the first capacitor C1 is connected to not only the output end of one power supply but also the anode of the diode D1, and the other end of the first capacitor C1 is connected to the corresponding power supply ground end; one end of the first capacitor C1 ' is connected with the output end of another power supply and also connected with the anode of the diode D1 ', and the other end of the first capacitor C1 ' is connected with the corresponding power supply ground end.

In order to further improve the reliability of power supply of the power supply, the method further comprises the following steps:

and one end of a third capacitor C3 is connected to one end of the current detection resistor Rt, the cathode of the diode D1 and the cathode of the diode D1', and the other end is grounded.

Specifically, one end of the third capacitor C3 is connected to one end of the current detection resistor Rt, the cathodes of the diodes D1 and D1', and the other end is grounded, so that the capacitor C3 serves as an energy storage capacitor to stabilize fluctuation during power switching, and stability and reliability of dual power supply are improved.

Further, still include:

and one end of the resistor R3 is connected with the PWM port, and the other ends of the resistors are grounded.

In the embodiment of the present application, one end of the resistor R3 is connected to the PWM port, and the other end of the resistor R3 is connected to ground, specifically, the resistance of the resistor R3 is 10k Ω.

As shown in fig. 2, further, the control unit further includes:

and the GPIO port is connected with the control ends of the two driving devices and is configured to output GPIO signals which enable the other driving device to drive the other NMOS switch tube to be also conducted.

In this embodiment, the GPIO port and the control terminals of the two driving devices are connected to one of the driving devices through the second resistor. When the control unit triggers one driving device to drive one NMOS switch to be conducted and the other driving device drives the other NMOS switch tube to be cut off, the GPIO port outputs a GPIO signal which can trigger the other driving device to drive the other NMOS switch tube to be conducted, so that the two power supplies can simultaneously supply power for the load R, and the power supply capacity is improved to 2 times.

As shown in fig. 2, in one embodiment, the GPIO signals include a high level signal, a low level signal and a high impedance signal, and the switching branch further includes:

Specifically, one switching branch comprises a first triode Q1, a first optocoupler device OC1, a first resistor R1 and a second resistor R2, the other switching branch comprises a second triode Q2, a second optocoupler device OC2, a first resistor R1 'and a second resistor R2', the first triode Q1 and the second triode Q2 are both NPN type, the first transistor Q1 and the second transistor Q2 are commonly connected with the PWM port through a first resistor R1 and a first resistor R1', respectively, the first triode Q1 and the second triode Q2 are respectively connected with the GPIO port through a second resistor R2 and a second resistor R2' when needed, the upper part refers to an access circuit, the resistance of the second resistor R2 is smaller than that of the first resistor R1, and the resistance of the second resistor R2 'is smaller than that of the first resistor R1', specifically, R1 ═ 10k Ω, R2 ═ 0.47k Ω, R1 ═ 10k Ω, and R2 ═ 0.47k Ω. And the larger the difference value between the resistance value of the first resistor and the resistance value of the second resistor is, the stronger the driving capability of the GPIO signal is compared with that of the PWM signal, and more than 20 times of the resistor ratio is recommended to be selected.

The GPIO signals comprise high-level signals, low-level signals and high-resistance state signals, when two paths of power supplies are not needed for supplying power to the load R, the signals output by the GPIO ports are the high-resistance state signals, and at the moment, the GPIO ports are regarded as open circuits.

If the PWM port outputs a high-level signal, the first triode Q1 and the second triode Q2 are conducted, the first optocoupler OC1 is conducted, the NMOS _1 is cut off, and the VCC _1 cannot supply power for the load R; the second optical coupler OC2 is turned off, the NMOS _2 is turned on, and VCC _2 supplies power to the load R. In order to enable two paths of power supplies to supply power to the load R at the same time, the GPIO port outputs a low level signal, and a second resistor R2 connected with the first triode Q1 is connected with a high-voltage circuit, and a first resistor R2' connected with the second triode Q2 is not connected with a high-voltage circuit. The high level signal of PWM port output passes through first resistance R1, second resistance R2 is exported after the GPIO port, supposes that the voltage of high level signal is 3.3V, then the base voltage of first triode Q1 is again according to first resistance R1, confirm to be about 0.15V after the second resistance R2 partial pressure, is less than the turn-on threshold typical value 0.6V of the first triode Q1 of field, and first triode Q1 is in the off-state, and first opto-coupler device OC1 cuts off, and NMOS _1 switches on, and VCC _1 supplies power for load R, realizes that the dual supply is the power for load R promptly.

If the PWM port outputs a low-level signal, the first triode Q1 and the second triode Q2 are cut off, the first optocoupler OC1 is cut off, the NMOS _1 is conducted, and the VCC _1 supplies power to the load R; the second optocoupler device OC2 is turned on, the NMOS _2 is turned off, and VCC _2 cannot supply power to the load R. In order to enable two power supplies to supply power to the load R at the same time, the GPIO port outputs a high-level signal, and the second resistor R2 connected with the first triode Q1 is not connected with the load, and the first resistor R2' connected with the second triode Q2 is connected with the load. The high-level signal output by the GPIO port is output to the PWM port through the second resistor R2 'and the first resistor R1', the voltage of the high-level signal is assumed to be 3.3V, the control voltage V _ PLL is 3.3V, the base voltage of the second triode Q2 is determined to be about 3.15V after voltage division according to the second resistor R2 'and the first resistor R1', the base voltage is higher than the typical value of the conduction threshold of the second triode Q2, at the moment, the second triode Q2 is in a conduction state, the second optocoupler OC2 is cut off, the NMOS _2 is conducted, and the VCC _2 also supplies power to the load R, namely, the dual power supply is realized to supply power to the load R.

It is thus clear that the control unit exports high-low level signal according to PWM port, GPIO port to insert or not insert the circuit with the second resistance according to actual demand, can realize switching on of two NMOS switch tubes, in order to realize that the dual supply is the power supply of load R simultaneously, the load capacity promotes the twice, and realizes that the form is simple, can also reduce the requirement to the large power specification. In other words, when the PWM port outputs a low or high level, the GPIO port of the control unit outputs a high or low control level to turn on the power supply loop of the other power supply, and synchronously supplies power to the load, thereby realizing that the two power supplies supply simultaneously at the peak load current.

In the description of the present application, it should be noted that the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present application. Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly and encompass, for example, both fixed and removable coupling as well as integral coupling; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

It is noted that, in the present application, relational terms such as "first" and "second", and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A circuit for balancing dual power supplies, comprising:

2. The balanced dual power supply circuit of claim 1, wherein the control unit comprises:

3. The balanced dual power supply circuit of claim 1, further comprising:

4. The balanced dual power supply circuit of claim 1, wherein the switching legs further comprise:

5. The balanced dual power supply circuit of claim 1, wherein the switching legs further comprise:

6. The balanced dual power supply circuit of claim 1, wherein the control unit further comprises:

7. The balanced dual power supply circuit of claim 6, wherein the GPIO signals comprise a high level signal, a low level signal and a high impedance state signal, the switching leg further comprising:

8. An equalized dual power supply circuit as claimed in any one of claims 1 to 7, wherein the driving device comprises an optocoupler device, and further comprises at least one of a field effect transistor, a triode or an inverter.

9. The balanced dual power supply circuit of claim 8, wherein the driving devices comprise transistors and optocoupler devices.

10. The balanced dual-power-supply circuit as claimed in claim 9, wherein the first end of the triode is connected to the control unit, the positive input end of the optocoupler is connected to the control voltage, the positive output end is connected to the gate of the NMOS switch tube, and the negative output end is connected to the power ground; at the same time, the user can select the desired position,