CN216436793U

CN216436793U - Switching power supply input over-voltage and under-voltage protection circuit with function of preventing false triggering

Info

Publication number: CN216436793U
Application number: CN202123024881.5U
Authority: CN
Inventors: 黄明元
Original assignee: Jiangsu Huashi Electronic Technology Co ltd
Current assignee: Jiangsu Huashi Electronic Technology Co ltd
Priority date: 2021-12-03
Filing date: 2021-12-03
Publication date: 2022-05-03
Anticipated expiration: 2031-12-03

Abstract

The utility model discloses an under-voltage protection circuit is crossed in switching power supply input with prevent mistake trigger function, including input voltage acquisition end PRO, logic circuit, logic controller and driver, when the voltage that input voltage acquisition end PRO gathered is higher than overvoltage reference Vovp or is less than under-voltage reference Vuvp, logic circuit sends logic 1 signal to logic controller, and logic controller passes through the driver and is connected to the grid of main power pipe Q1 in the switching power supply, logic controller carries out following logic, and when logic circuit output logic 1 signal, main power pipe Q1 in the control switching power supply is shut off; the protection circuit further comprises an enabling module, wherein the enabling module is used for enabling the logic circuits to output logic 0 signals; the protection circuit also collects the voltage drop of a sampling resistor Rcs in the switch power supply and inputs the voltage drop to the logic controller, and the logic controller controls the on-off of the switch SW1 according to the voltage drop of the sampling resistor Rcs.

Description

Switching power supply input over-voltage and under-voltage protection circuit with function of preventing false triggering

Technical Field

The utility model relates to a switching power supply technical field, in particular to switching power supply inputs under-voltage protection circuit with prevent that mistake from triggering function.

Background

In a power supply system, input overvoltage and input undervoltage protection is sometimes used, and under a normal condition, a chip directly samples an input voltage signal in real time and then compares the input voltage signal with an internal overvoltage reference or an internal undervoltage reference, so that overvoltage and undervoltage protection is realized. However, for some special applications, such as under a system architecture with a chip floating, the real-time sampling method cannot be applied, which may result in error protection.

Fig. 1 is a typical input overvoltage/undervoltage protection circuit of a BUCK topology in the prior art, and it can be seen from the figure that the ground of a chip is common to the input, the input voltage is VIN, the VIN is divided by resistors R1 and R2 to obtain a voltage, and the chip detects the voltage in real time by using a PRO pin and compares the voltage with an internal overvoltage reference Vovp and an undervoltage reference Vuvp in real time. When the input voltage VIN rises, the voltage of the PRO pin also rises, and when the voltage of the PRO pin exceeds the reference Vovp, the chip overvoltage protection is triggered. Similarly, when the input voltage VIN decreases, the voltage of the PRO pin also decreases, and when the voltage of the PRO pin is lower than the reference Vuvp, the chip under-voltage protection is triggered. The working waveform diagram of the main device is shown in fig. 2, and it can be seen from the waveform that the VIN voltage is reflected in real time by PRO, which can well play a role in monitoring the VIN voltage.

However, the circuit may cause error protection in a system architecture with a chip floating on the ground. Fig. 3 shows a circuit diagram of the circuit in the floating application, and it can be seen from fig. 3 that since the chip adopts a floating architecture, the chip cannot directly detect VIN voltage in real time by using a PRO pin, but generally detects the voltage between the source and drain of the MOS transistor Q1 plus the voltage across the sampling resistor Rcs. Since the sampling resistor Rcs has only a few ohms and the voltage drop thereof is negligible, it can be considered as directly detecting the source-drain voltage of Q1. When the Q1 is turned off, the source-drain voltage of the Q1 is close to VIN, so that the VIN voltage can be normally detected by PRO, and the protection function is normal; when the Q1 is turned on, the source-drain voltage of the Q1 is close to 0, so the PRO voltage is also close to 0 and is lower than the reference Vuvp, and the chip under-voltage protection can be triggered. The working waveforms of the main devices are shown in fig. 4, and it can be seen from the waveforms that PRO reflects the source-drain voltage of the power switch tube Q1 in real time, but cannot reflect the VIN voltage in real time, and at the stage of turning on Q1, the voltage of PRO is close to 0, and will be lower than the reference Vuvp, triggering the input undervoltage protection.

SUMMERY OF THE UTILITY MODEL

The utility model provides an under-voltage protection circuit is crossed in switching power supply input with prevent mistake trigger function, its advantage is whether use the system architecture that the chip floats the ground, and this protection circuit can all realize the function of input excessive pressure and input under-voltage protection no matter.

The above object of the present invention is achieved by the following technical solution, a switching power supply input overvoltage/undervoltage protection circuit with function of preventing false triggering, the protection circuit includes an input voltage acquisition end PRO, a logic circuit, a logic controller and a driver, the input voltage acquisition end PRO is used for acquiring input voltage of the switching power supply, the logic circuit is internally provided with an overvoltage reference Vovp and an undervoltage reference Vuvp, the logic circuit performs logic operation on signals acquired by the input voltage acquisition end PRO and outputs digital signals, when the voltage acquired by the input voltage acquisition end PRO is higher than the overvoltage reference Vovp or lower than the undervoltage reference Vuvp, the logic circuit sends a logic 1 signal to the logic controller, the logic controller is connected to a gate of a main power tube Q1 in the switching power supply through the driver, the logic controller executes the following logic, when the logic circuit outputs the logic 1 signal, controlling a main power tube Q1 in the switching power supply to be switched off;

the protection circuit further comprises an enabling module, the enabling module is used for enabling the logic circuits to output logic 0 signals, the enabling module comprises a constant current source, a resistor R3 and a switch SW1, the anode of the constant current source is connected with a power supply, the cathode of the constant current source is grounded through a resistor R3, the switch SW1 is connected to two ends of a resistor R3 in parallel, the voltage drop of two ends of a resistor R3 is used as the output ENA of the enabling module to be input into the logic circuits, and the logic controller is connected with the switch SW1 and controls the switch SW1 to be switched on and switched off;

the protection circuit also collects the voltage drop of a sampling resistor Rcs in the switch power supply and inputs the voltage drop to the logic controller, and the logic controller controls the on-off of the switch SW1 according to the voltage drop of the sampling resistor Rcs.

The utility model discloses set up further to, logic circuit includes two comparators, an AND gate and an OR gate, the positive input of one of them comparator is connected with input voltage acquisition end PRO, the negative input end is connected with excessive pressure benchmark Vovp, the positive input end and the undervoltage benchmark Vuvp of another comparator, the negative input end is connected with input voltage acquisition end PRO, the output of one of them comparator is connected to an input of OR gate, the output of another comparator is connected to an input of AND gate, another input of AND gate is connected with the output ENA of enabling the module, the output of AND gate is connected with another input of OR gate, or the output of gate is connected to logic controller.

The utility model discloses set up further to, logic circuit includes two comparators, an OR gate and an AND gate, the positive input of one of them comparator is connected with input voltage acquisition end PRO, the negative input end is connected with excessive pressure benchmark Vovp, the positive input end and the undervoltage benchmark Vuvp of another comparator, the negative input end is connected with input voltage acquisition end PRO, the output of two comparators is connected to two inputs of OR gate respectively, the output of OR gate is connected to an input of AND gate, another input of AND gate is connected with the output ENA of enabling module, the output of AND gate is connected to logic controller.

The utility model discloses further set up to, input voltage gathers end PRO and is connected with divider resistance R1 and R2.

The utility model discloses further set up to, switch SW 1's break-make opportunity does: when the main power tube Q1 in the switch power supply is turned off, the switch SW1 is turned off; when the main power transistor Q1 in the switching power supply is turned on, the switch SW1 is turned on.

The utility model is further arranged that when the main power tube Q1 in the switch power supply is switched on, the switch SW1 is switched on in advance; when the main power transistor Q1 in the switching power supply is turned off, the switch SW1 is turned off with a delay.

To sum up, the beneficial effects of the utility model are that: through the enabling module, when a main power tube Q1 in the switching power supply is turned off, the switch SW1 is controlled to be turned off, so that a low level signal is sent to the logic circuit, the shielding of the input voltage VIN sampling signal of the switching power supply is realized, and the stage that the voltage of an input voltage acquisition end PRO is close to 0 during the turn-on period of the main power tube Q1, so that the input undervoltage protection is triggered by mistake is avoided; the circuit can normally realize the functions of input overvoltage and input undervoltage protection no matter whether the circuit is applied to a system architecture with a chip floating to the ground or not, and the input undervoltage protection cannot be triggered by mistake.

Drawings

Fig. 1 is a circuit diagram of a typical BUCK topology switching power supply input overvoltage/undervoltage protection circuit according to the background art of the present invention;

FIG. 2 is a waveform diagram illustrating the operation of the main components of the system of FIG. 1;

FIG. 3 is a schematic diagram of the system of FIG. 1 applied to a floating BUCK topology;

FIG. 4 is a waveform diagram illustrating the operation of the main components of the system of FIG. 3;

fig. 5 is a schematic diagram of an application of the embodiment of the present invention in a BUCK topology;

fig. 6 is a schematic diagram of an application of the second embodiment of the present invention in a BUCK topology;

FIG. 7 is a waveform diagram illustrating the operation of the main components of the system of FIG. 5 or FIG. 6;

fig. 8 is a schematic diagram of an application of the embodiment of the present invention in a floating-ground BUCK topology;

fig. 9 is a schematic diagram of an application of the second embodiment of the present invention in a floating-ground BUCK topology;

fig. 10 is a waveform diagram showing the operation of the main components of the system of fig. 8 or 9.

Detailed Description

The following detailed description of the embodiments of the present invention will be made with reference to the accompanying drawings.

The first embodiment is as follows: referring to fig. 5, a switching power supply input over-voltage and under-voltage protection circuit with false triggering prevention function, the protection circuit comprises an input voltage acquisition end PRO, a logic circuit, a logic controller and a driver, wherein the input voltage acquisition end PRO is used for acquiring the input voltage of the switching power supply, an overvoltage reference Vovp and an undervoltage reference Vuvp are arranged in the logic circuit, the logic circuit carries out logic operation on the signal acquired by the input voltage acquisition end PRO and outputs a digital signal, when the voltage collected by the input voltage collecting terminal PRO is higher than the overvoltage reference Vovp or lower than the undervoltage reference Vuvp, the logic circuit sends a logic 1 signal to a logic controller, which is connected to the gate of the main power transistor Q1 in the switching power supply through a driver, which performs the following logic, when the logic circuit outputs a logic 1 signal, the main power tube Q1 in the switch power supply is controlled to be switched off;

The logic circuit comprises two comparators, an AND gate and an OR gate, wherein the positive input end of one comparator is connected with the input voltage acquisition end PRO, the negative input end of the other comparator is connected with the overvoltage reference Vovp, the positive input end of the other comparator is connected with the undervoltage reference Vuvp, the negative input end of the other comparator is connected with the input voltage acquisition end PRO, the output end of the one comparator is connected with one input end of the OR gate, the output end of the other comparator is connected with one input end of the AND gate, the other input end of the AND gate is connected with the output ENA of the enabling module, the output end of the AND gate is connected with the other input end of the OR gate, and the output end of the OR gate is connected with the logic controller.

The input voltage acquisition end PRO is connected with voltage dividing resistors R1 and R2, and the input voltage acquisition end PRO is connected between the resistors R1 and R2.

The on-off time of the switch SW1 is: when the main power tube Q1 in the switch power supply is turned off, the switch SW1 is turned off; when the main power transistor Q1 in the switching power supply is turned on, the switch SW1 is turned on.

When a main power tube Q1 in the switch power supply is switched on, a switch SW1 is switched on in advance; when the main power transistor Q1 in the switching power supply is turned off, the switch SW1 is turned off with a delay.

Fig. 7 shows waveforms for operating main devices in the protection circuit in this embodiment.

The application of the protection circuit in the floating-ground BUCK topology in the embodiment is shown in fig. 8, and it can be seen from fig. 8 that since the chip adopts a floating-ground architecture, the chip cannot directly detect the VIN voltage in real time by using the PRO pin, but directly detects the source-drain voltage of Q1. The specific working process is as follows: when the main power tube Q1 is switched on, the SW1 is switched on, and at the moment, the chip shields a source-drain voltage sampling signal of the Q1; when the main power tube Q1 is turned off, after a short time delay, the SW1 is turned off, the chip cancels the shielding of the voltage sampling signal between the source and the drain of the Q1, then, before the main power tube Q1 is turned on, the SW1 is turned on again, and the voltage sampling signal between the source and the drain of the Q1 is continuously shielded.

The operation waveform diagram of the main components of the system in fig. 8 is shown in fig. 10. It can be seen from the waveforms that the protection state can only be activated when the enable ENA is at a high level, and since the enable ENA only changes to a high level during the turn-off of Q1, the stage of false triggering of the undervoltage protection caused by the voltage of PRO approaching 0 during the turn-on of Q1 is avoided. Therefore, no matter the chip is applied to a system structure with the chip floating to the ground or not, the system can normally realize the functions of input overvoltage and input undervoltage protection, and the input undervoltage protection cannot be triggered by mistake.

Example two: the difference between the logic circuit and the first embodiment is that the logic circuit comprises two comparators, an or gate and an and gate, wherein the positive input end of one comparator is connected with an input voltage acquisition end PRO, the negative input end of the one comparator is connected with an overvoltage reference Vovp, the positive input end of the other comparator is connected with an undervoltage reference Vuvp, the negative input end of the other comparator is connected with the input voltage acquisition end PRO, the output ends of the two comparators are respectively connected to the two input ends of the or gate, the output end of the or gate is connected to one input end of the and gate, the other input end of the and gate is connected with an output ENA of an enabling module, and the output end of the and gate is connected to the logic controller.

The protection circuit in the present embodiment is applied to the BUCK topology as shown in fig. 6, and is applied to the floating-ground BUCK topology as shown in fig. 9.

The circuit of the present invention is not limited to use in BUCK topologies, but can also be used in BOOST topologies, BUCK-BOOST topologies and various topology architectures derived from these three topologies.

The utility model discloses an implementation has a lot of, above is just the utility model discloses a wherein two kinds of implementation. If shield the voltage signal of being surveyed during main power tube (Q1 in the picture) opens to avoid the false triggering input undervoltage protection, realize the control mode of input excessive pressure and input undervoltage protection function, all be in the utility model discloses a protection range.

Claims

1. A switch power supply input over-voltage and under-voltage protection circuit with the function of preventing false triggering is characterized in that, the protection circuit comprises an input voltage acquisition end PRO, a logic circuit, a logic controller and a driver, wherein the input voltage acquisition end PRO is used for acquiring the input voltage of the switching power supply, an overvoltage reference Vovp and an undervoltage reference Vuvp are arranged in the logic circuit, the logic circuit carries out logic operation on the signal acquired by the input voltage acquisition end PRO and outputs a digital signal, when the voltage collected by the input voltage collecting terminal PRO is higher than the overvoltage reference Vovp or lower than the undervoltage reference Vuvp, the logic circuit sends a logic 1 signal to a logic controller, which is connected to the gate of the main power transistor Q1 in the switching power supply through a driver, which performs the following logic, when the logic circuit outputs a logic 1 signal, the main power tube Q1 in the switch power supply is controlled to be switched off;

2. The input overvoltage/undervoltage protection circuit of claim 1, wherein the logic circuit comprises two comparators, an and gate and an or gate, wherein a positive input terminal of one comparator is connected to the input voltage acquisition terminal PRO, a negative input terminal is connected to the overvoltage reference Vovp, a positive input terminal of the other comparator is connected to the undervoltage reference Vuvp, and a negative input terminal is connected to the input voltage acquisition terminal PRO, an output terminal of one comparator is connected to an input terminal of the or gate, an output terminal of the other comparator is connected to an input terminal of the and gate, another input terminal of the and gate is connected to the output ENA of the enable module, an output terminal of the and gate is connected to another input terminal of the or gate, and an output terminal of the gate is connected to the logic controller.

3. The input overvoltage/undervoltage protection circuit of switching power supply with false triggering prevention function according to claim 1, wherein the logic circuit comprises two comparators, an or gate and an and gate, wherein the positive input terminal of one comparator is connected with the input voltage acquisition terminal PRO, the negative input terminal is connected with the overvoltage reference Vovp, the positive input terminal of the other comparator is connected with the undervoltage reference Vuvp, the negative input terminal is connected with the input voltage acquisition terminal PRO, the output terminals of the two comparators are respectively connected to the two input terminals of the or gate, the output terminal of the or gate is connected to one input terminal of the and gate, the other input terminal of the and gate is connected with the output ENA of the enable module, and the output terminal of the and gate is connected to the logic controller.

4. The input overvoltage/undervoltage protection circuit of switching power supply with false triggering prevention function according to claim 2 or 3, wherein the input voltage collecting terminal PRO is connected with voltage dividing resistors R1 and R2.

5. The input overvoltage/undervoltage protection circuit of claim 4, wherein the switch SW1 is turned on or off at the following timing: when the main power tube Q1 in the switch power supply is turned off, the switch SW1 is turned off; when the main power transistor Q1 in the switching power supply is turned on, the switch SW1 is turned on.

6. The input under-voltage protection circuit of switching power supply with false triggering prevention function as claimed in claim 5, wherein when the main power transistor Q1 in the switching power supply is turned on, the switch SW1 is turned on in advance; when the main power transistor Q1 in the switching power supply is turned off, the switch SW1 is turned off with a delay.