CN216390999U

CN216390999U - Wireless audio transmission device based on UWB

Info

Publication number: CN216390999U
Application number: CN202123177848.6U
Authority: CN
Inventors: 熊文辉; 林弟; 张常华; 朱正辉; 赵定金
Original assignee: Guangzhou Baolun Electronics Co Ltd
Current assignee: Guangdong Baolun Electronics Co ltd
Priority date: 2021-12-16
Filing date: 2021-12-16
Publication date: 2022-04-26
Anticipated expiration: 2031-12-16

Abstract

The utility model discloses a UWB-based wireless audio transmission device, which comprises a sending end and a receiving end, wherein the sending end comprises an audio acquisition unit, an encoding and decoding unit, a CPU processing unit and a UWB module unit which are sequentially connected, the receiving end comprises the UWB module unit, the CPU processing unit, the encoding and decoding unit and an output playing unit which are sequentially connected, the UWB module unit where the sending end is located is in communication connection with the UWB module unit where the receiving end is located, the audio data acquired by the acquisition unit are analog audio data, the encoding and decoding unit is used for encoding and decoding the audio data, the CPU processing unit is used for encapsulating or decapsulating the audio data, the UWB module unit is used for sending and receiving the audio data, and the output playing unit is used for amplifying and outputting the audio data. The utility model adopts UWB to transmit audio data, and has the advantages of low time delay, low power consumption, strong anti-interference capability and high broadband wireless transmission.

Description

Wireless audio transmission device based on UWB

Technical Field

The utility model relates to the technical field of audio circuits, in particular to a wireless audio transmission device based on UWB.

Background

The existing wireless audio transmission device generally adopts bluetooth or WIFI and the like as transmission media to transmit audio, and then outputs the audio to a playing end to play. The wireless audio equipment is easily interfered by the same frequency equipment in many times, so that the audio file cannot be stably transmitted, or the transmission delay of the audio file is high, the signal is poor, and the problems of high distortion degree, poor tone quality and the like of the audio signal are easily caused. For this reason, it is desirable to have an audio transmission or audio file transmission apparatus or device that is reliable in communication, low in latency, high in accuracy, low in power consumption, and strong in interference resistance.

SUMMERY OF THE UTILITY MODEL

In view of the defects of the prior art, the utility model provides a wireless audio transmission device based on UWB, which can solve the problems that the audio transmission is easy to be interfered and unstable.

The technical scheme for realizing the purpose of the utility model is as follows: a UWB-based wireless audio transmission device comprises a transmitting end and a receiving end, wherein the transmitting end comprises an audio acquisition unit, a coding and decoding unit, a CPU processing unit and a UWB module unit which are connected in sequence, the receiving end comprises a UWB module unit, a CPU processing unit, a coding and decoding unit and an output playing unit which are connected in sequence, the UWB module unit where the transmitting end is located is in communication connection with the UWB module unit where the receiving end is located,

the acquisition unit is used for acquiring audio to obtain audio data, the audio data acquired by the acquisition unit is analog audio data,

the coding and decoding unit is used for amplifying the collected analog audio data and converting the analog audio data into digital audio data, then coding the digital audio data and sending the digital audio data to the CPU processing unit, receiving the audio data from the CPU processing unit and then decoding the audio data, and sending the decoded audio data to the output playing unit,

the CPU processing unit is used for packaging the coded audio data and then sending the audio data to the UWB module unit, and decapsulating the audio data received from the UWB module unit,

the UWB module unit is used for sending out the local audio data and receiving the audio data transmitted from the outside,

the output playing unit is used for converting the received audio data into analog audio data, amplifying the analog audio data and outputting the amplified analog audio data to a playing terminal accessed at the later stage for playing.

Further, the audio acquisition unit comprises an audio interface J1, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, an amplifier U3A and an amplifier U3B, wherein the audio interface is used for receiving audio data, a pin 2 of the audio interface J1 is grounded, a pin 1 of the audio interface J1 serves as an output end to output the audio data to a post circuit, the pin 1 is connected with one end of a first parallel circuit, then is sequentially connected with a capacitor C15 and a resistor R18 in series and then is connected with one end of a second parallel circuit, the other end of the first parallel circuit is grounded, the first parallel circuit comprises a capacitor C17 and a resistor R19 which are connected in parallel, a second parallel circuit comprises a capacitor C16 and a resistor R17 which are connected in parallel, one end of the second parallel circuit is further connected with a pin 2 of the amplifier U3A, the other end of the second parallel circuit is connected with a pin 1 of the amplifier U A, and a pin A of the amplifier U3 is grounded, the output end of the amplifier U3A connected with the other end of the second parallel circuit is also used as an output end AINA-, and is connected with a pin 6 of the amplifier U3B and one end of the third parallel circuit after being connected with a resistor R20 in series, a pin 5 of the amplifier U3B is grounded, a pin 7 of the amplifier U3B is connected with the other end of the third parallel circuit and is used as an output end AINA +, and the third parallel circuit comprises a resistor R21 and a capacitor C18 which are connected in parallel.

Furthermore, the codec unit comprises a codec chip U1, a reset end series resistor R16 of the codec chip U1 is connected with a 3.3V voltage, a pin 15 of the codec chip U1 is connected with one end of a fourth parallel circuit, the other end of the fourth parallel circuit is grounded, the fourth parallel circuit comprises a capacitor C13 and a capacitor C14 which are connected in parallel, a pin 16 and a pin 17 of the codec chip U1 are respectively connected with an output terminal AINA-, an output terminal AINA + of the audio acquisition unit, a pin 20 and a pin 21 of the codec chip U1 are respectively connected with two ends of a fifth parallel circuit, the fifth parallel circuit comprises a capacitor C7 and a capacitor C8 which are connected in parallel, the pin 20 is also connected with a 5V voltage, the pin 21 is connected with one end of the fifth parallel circuit and then grounded, a pin 2 series resistor R2 of the codec chip U1 is connected with a ground, a pin 8 of the codec chip U1 is grounded, and a pin 9 and a pin 10 are connected with one end of the sixth parallel circuit and then connected with a voltage 3.3V, the other end of the sixth parallel circuit is grounded, a pin 11 and a pin 12 are connected with the CPU, a pin 13 of the codec chip U1 is connected with a 3.3V voltage after being connected with a resistor R15 in series, a pin 24 of the codec chip U1 serves as an output terminal AOUTA-, and a pin 25 of the codec chip U1 serves as an output terminal AOUTA +, and the decoded signal is sent to the output playing unit through the pin 24 and the pin 25.

Further, the CPU processing unit includes an audio processing chip U4, a pin 57 and a pin 60 of the audio processing chip U4 are respectively connected to two ends of a seventh parallel circuit, one end of the seventh parallel circuit connected to the pin 57 is grounded, one end connected to the pin 60 is connected to a voltage DVCC, the seventh parallel circuit includes a capacitor C23 and a capacitor C24, an I2C interface formed by a pin 51 and a pin 52 of the audio processing chip U4 is respectively connected to a pin 11 and a pin 12 of the codec chip U1, so that the CPU processing unit is connected to the codec chip U1, the pin 11, the pin 16, the pin 25, the pin 26, the pin 28, and the pin 29 of the audio processing chip U4 are respectively grounded, and the pin 30-the pin 33 of the audio processing chip U4 together form an SPI interface and are connected to the UWB module unit through the SPI interface.

Further, the codec chip U1 has a model ADAU 1961.

Further, UWB module unit includes UWB chip U2, connects a 3.3V voltage after UWB chip U2's pin 5-pin 7 are connected jointly, and pin 8, pin 16, pin 21, pin 23, pin 24 are connected jointly the back ground connection, and pin 9 and pin 10 connect a 3.3V voltage jointly behind resistance R25 and the resistance R24 respectively in series, and pin 17-pin 20 constitute the SPI interface jointly to with audio frequency processing chip U4's SPI interface connection.

Further, a pin 17 of the UWB module unit is connected to a pin 33 of the CPU processing unit, a pin 18 of the UWB module unit is connected to a pin 31 of the CPU processing unit, a pin 19 of the UWB module unit is connected to a pin 32 of the CPU processing unit, and a pin 20 of the UWB module unit is connected to a pin 30 of the CPU processing unit.

Further, the UWB chip U2 is model DW 1000.

Further, the output playing unit includes a resistor R1, a resistor R3, a resistor R5, a resistor R6, a resistor R7, a resistor R9, a resistor R10, a resistor R14, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C11, a capacitor C12, an amplifier U2A, and an amplifier U2B, one end of the resistor R5 is connected to an output terminal AOUTA-of a codec chip U1 of the codec unit, one end of the resistor R9 is connected to an output terminal AOUTA + of a codec chip U1 of the codec unit, the other end of the resistor R5 is connected to one end of a resistor R1, a resistor R6, and a capacitor C1, the other end of the resistor R6 is connected to one end of a pin 2 of an amplifier U2A, one end of a capacitor C3, the other end of the capacitor C1 is grounded, one end of a resistor C1 connected to one end of a resistor R1, a resistor R36 5, and the other end of a resistor R1, a pin 1 and a pin of the amplifier U1 are connected to the amplifier U1, the other end of the resistor R9 is connected in series with a resistor R10 and then connected with a pin 3 of the amplifier U2A, a connection node between the resistor R9 and the resistor R10 is connected with one end of the resistor R14 and then commonly grounded, the other end of the resistor R14 is connected in series with a capacitor C12 and a capacitor C6 in sequence and then connected with a pin 3 of the amplifier U2A, a connection node between the capacitor C12 and the capacitor C6 is further grounded, a pin 5 of the amplifier U2B is grounded, one end of the resistor R7 connected with the amplifier U2B is further connected with one end of an eighth parallel circuit, the other end of the eighth parallel circuit is connected with a pin 7 of the amplifier U2B, the eighth parallel circuit comprises a capacitor C2 and a resistor R3 which are connected in parallel, the pin 7 of the amplifier U2B is connected with the other end of the eighth parallel circuit and then connected with a capacitor C5 in series to be used as an output terminal LINE _ OUT, and the output terminal is used for outputting audio data to a play terminal accessed in a rear stage.

The utility model has the beneficial effects that: the utility model adopts UWB to transmit audio data, and has the advantages of low time delay, low power consumption, strong anti-interference capability, high broadband wireless transmission and the like.

Drawings

FIG. 1 is a circuit schematic of an audio acquisition unit;

FIG. 2 is a circuit schematic of a codec unit;

FIG. 3 is a circuit schematic of a CPU processing unit;

FIG. 4 is a schematic circuit diagram of a UWB module unit;

FIG. 5 is a circuit schematic of an output play unit;

fig. 6 is a schematic view of the frame structure of the present invention.

Detailed Description

The utility model is further described with reference to the accompanying drawings and the specific embodiments.

As shown in fig. 1-6, a wireless audio transmission device based on UWB comprises a sending end and a receiving end, wherein the sending end comprises an audio acquisition unit, a coding and decoding unit, a CPU processing unit and a UWB module unit which are connected in sequence, the receiving end comprises a UWB module unit, a CPU processing unit, a coding and decoding unit and an output playing unit which are connected in sequence, the UWB module unit where the sending end is located is in communication connection with the UWB module unit where the receiving end is located, so that wireless audio transmission is realized between the sending end and the receiving end. In the sending end, the audio acquisition unit is connected with the coding and decoding unit, the coding and decoding unit is connected with the CPU processing unit, and the CPU processing unit is connected with the UWB module unit. In the receiving end, the coding and decoding unit is also connected with the output playing unit. The acquisition unit is used for acquiring audio to obtain audio data, and the audio data acquired by the acquisition unit is analog audio data, and is acquired through one or more audio input interfaces such as a microphone and an AUX line access to acquire the audio data. The coding and decoding unit is used for amplifying the collected analog audio data, converting the analog audio data into digital audio data, coding the digital audio data, sending the digital audio data to the CPU processing unit, receiving the audio data from the CPU processing unit, decoding the audio data and sending the decoded audio data to the output playing unit. The CPU processing unit is used for packaging the coded audio data and then sending the audio data to the UWB module unit, and de-packaging the audio data received from the UWB module unit, and packaging the audio data to obtain a target format meeting the transmission requirement of the UWB module unit, so that the UWB module unit can be adopted to transmit the data. The UWB module unit is used for sending out local audio data, receiving audio data transmitted from the outside and sending the received audio data to the CPU processing unit. The output playing unit is used for converting the received audio data into analog audio data, amplifying the analog audio data and outputting the amplified analog audio data to a playing terminal for playing, for example, outputting the amplified analog audio data to a loudspeaker for playing.

When the circuit is used as a sending end, an audio data packet encapsulated by the CPU processing unit is sent to a far end through the UWB module unit for playing; when the circuit is used as a receiving end, the UWB module unit sends the received audio to the CPU for decapsulation, and sends the decapsulated audio data to the decoding unit for decoding, and the decoded audio data is still digital audio and needs to be sent to the output playing unit to be converted into analog audio, amplified and then output to a speaker and other terminals for playing.

The audio acquisition unit comprises an audio interface J1, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, an amplifier U3A and an amplifier U3B. The audio interface is used for receiving audio data, a pin 2 of the audio interface J1 is grounded (AGND in the figure represents ground), a pin 1 of the audio interface J1 serves as an output end and outputs the audio data to a backward-stage circuit, and the pin 1 is connected with one end of the first parallel circuit, then is sequentially connected with a capacitor C15 and a resistor R18 in series, and then is connected with one end of the second parallel circuit. The other end of the first parallel circuit is grounded, and the first parallel circuit comprises a capacitor C17 and a resistor R19 which are connected in parallel. The second parallel circuit comprises a capacitor C16 and a resistor R17 which are connected in parallel, one end of the second parallel circuit is also connected with a pin 2 (inverting input end) of the amplifier U3A, the other end of the second parallel circuit is connected with a pin 1 (output end) of the amplifier U3A, and a pin 3 (non-inverting input end) of the amplifier U3A is grounded. The output end of the amplifier U3A connected with the other end of the second parallel circuit is also used as an output end AINA-, and is connected with the pin 6 of the amplifier U3B and one end of the third parallel circuit after being connected with the resistor R20 in series. The pin 5 of the amplifier U3B is grounded, the pin 7 of the amplifier U3B is connected with the other end of the third parallel circuit to be used as an output terminal AINA +, and the third parallel circuit comprises a resistor R21 and a capacitor C18 which are connected in parallel.

The audio data collected by the audio interface J1 is subjected to inversion processing by the amplifier U3A and the amplifier U3B to form a stack of differential signals, and then the differential signals are output to the coding and decoding chip U1 for processing through an output terminal AINA & lt- & gt and an output terminal AINA & lt + & gt.

The encoding and decoding unit comprises an encoding and decoding chip U1, a reset end (RST pin) of the encoding and decoding chip U1 is connected with a 3.3V voltage after being connected with a resistor R16 in series, a pin 15 of the encoding and decoding chip U1 is connected with one end of a fourth parallel circuit, the other end of the fourth parallel circuit is grounded, and the fourth parallel circuit comprises a capacitor C13 and a capacitor C14 which are connected in parallel. And the pin 16 and the pin 17 of the coding and decoding chip U1 are respectively connected with the output end AINA-and the output end AINA + of the audio acquisition unit. The pin 20 and the pin 21 of the codec chip U1 are respectively connected with two ends of a fifth parallel circuit, the fifth parallel circuit comprises a capacitor C7 and a capacitor C8 which are connected in parallel, the pin 20 is also connected with a voltage of 5V, and the pin 21 is connected with one end of the fifth parallel circuit and then grounded. Pin 2 of the codec chip U1 is connected in series with a resistor R2 and then grounded. And a pin 8 of the encoding and decoding chip U1 is grounded, a pin 9 and a pin 10 are connected together and then connected with one end of a sixth parallel circuit and then connected with 3.3V voltage, and the other end of the sixth parallel circuit is grounded. Pin 11 and pin 12 are connected to the CPU processing unit. The pin 13 of the codec chip U1 is connected in series with the resistor R15 and then connected with 3.3V voltage. The pin 24 of the codec chip U1 serves as an output terminal AOUTA +, the pin 25 of the codec chip U1 serves as an output terminal AOUTA +, and the decoded signal is sent to the output play unit through the pin 24 and the pin 25.

The model of the codec chip U1 may be ADAU 1961.

The pin 16 and the pin 17 of the codec chip U1 receive the audio data of the differential signal, convert the analog audio data into digital audio data, complete encoding, and send the audio data to the CPU processing unit through the I2C interface formed by the pin 11 and the pin 12.

The CPU processing unit comprises an audio processing chip U4, a pin 57 and a pin 60 of the audio processing chip U4 are respectively connected with two ends of a seventh parallel circuit, one end of the seventh parallel circuit connected with the pin 57 is grounded, one end connected with the pin 60 is connected with a voltage DVCC, and the seventh parallel circuit comprises a capacitor C23 and a capacitor C24. An I2C interface formed by the pin 51 and the pin 52 of the audio processing chip U4 is respectively connected with the pin 11 and the pin 12 of the coding and decoding chip U1, so that the CPU processing unit is connected with the coding and decoding chip U1. Pin 11, pin 16, pin 25, pin 26, pin 28, and pin 29 of the audio processing chip U4 are each grounded, respectively. And the pin 30-the pin 33 of the audio processing chip U4 jointly form an SPI interface, and the SPI interface and the UWB module unit are connected through the SPI interface.

The type of the audio processing chip U4 can be ARM or FPGA or other single-chip microcomputer.

The UWB module unit comprises a UWB chip U2, wherein a 3.3V voltage is connected after pins 5-7 of a UWB chip U2 are connected together, a pin 8, a pin 16, a pin 21, a pin 23 and a pin 24 are connected together and then grounded, and a 3.3V voltage is connected together after the pin 9 and the pin 10 are respectively connected in series with a resistor R25 and a resistor R24. And the pin 17-the pin 20 jointly form an SPI interface, so that the SPI interface is connected with the SPI interface of the audio processing chip U4, and the UWB module unit is connected with the CPU processing unit. Wherein, the pin 17 of the UWB module unit is connected with the pin 33 of the CPU processing unit, the pin 18 of the UWB module unit is connected with the pin 31 of the CPU processing unit, the pin 19 of the UWB module unit is connected with the pin 32 of the CPU processing unit, and the pin 20 of the UWB module unit is connected with the pin 30 of the CPU processing unit.

The type of the UWB chip U2 may adopt DW1000, and certainly, UWB chips of other types may also be adopted, so that the UWB wireless transmitting and receiving functions may be implemented.

The output playing unit comprises a resistor R1, a resistor R3, a resistor R5, a resistor R6, a resistor R7, a resistor R9, a resistor R10, a resistor R14, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C11, a capacitor C12, an amplifier U2A and an amplifier U2B, wherein one end of the resistor R5 is connected with an output end AOUTA-of a coding and decoding chip U1 of the coding and decoding unit, one end of the resistor R9 is connected with an output end AOUTA + of a coding and decoding chip U1 of the coding and decoding unit, the other end of the resistor R5 is connected with one ends of a resistor R1, a resistor R6 and a capacitor C1, the other end of the resistor R6 is connected with one end of a pin 2 and one end of a capacitor C3 of the amplifier U2A, and the other end of the capacitor C1 is grounded. One end of a capacitor C1 connected with the resistor R5 is connected with the resistor R1 in series and then is connected with the other end of the capacitor C3 and a pin 1 of the amplifier U2A respectively, and the pin 1 of the amplifier is also connected with the capacitor C4 and the resistor R7 in series and then is connected with a pin 6 of the amplifier U2B. The other end of the resistor R9 is connected with a pin 3 of the amplifier U2A after being connected with a resistor R10 in series, a connecting node between the resistor R9 and the resistor R10 is connected with one end of a resistor R14 and then grounded together, the other end of the resistor R14 is connected with a pin 3 of the amplifier U2A after being sequentially connected with a capacitor C12 and a capacitor C6 in series, and a connecting node between the capacitor C12 and the capacitor C6 is grounded. The pin 5 of the amplifier U2B is grounded, one end of the resistor R7 connected to the amplifier U2B is further connected to one end of an eighth parallel circuit, the other end of the eighth parallel circuit is connected to the pin 7 of the amplifier U2B, the eighth parallel circuit includes a capacitor C2 and a resistor R3 which are connected in parallel, the pin 7 of the amplifier U2B is connected to the other end of the eighth parallel circuit, and then is connected in series with a capacitor C5 to serve as an output terminal LINE _ OUT, and the output terminal LINE _ OUT is used for outputting audio data to a playing terminal (e.g., a speaker) for audio playing.

The amplifier U2A receives the differential signals from the output terminal AOUT-and the output terminal AOUT +, combines the differential signals into one to form audio data, then outputs the audio data after amplification by the amplifier U2B, and finally outputs the audio data to a playing terminal (e.g., a speaker) connected to a later stage through the output terminal LINE _ OUT for output playing, thereby completing the wireless transmission of the whole audio data.

The amplifiers U2A, U2B, U3A and U3B may be conventional general amplifiers.

The embodiments disclosed in this description are only an exemplification of the single-sided characteristics of the utility model, and the scope of protection of the utility model is not limited to these embodiments, and any other functionally equivalent embodiments fall within the scope of protection of the utility model. Various other changes and modifications to the above-described embodiments and concepts will become apparent to those skilled in the art from the above description, and all such changes and modifications are intended to be included within the scope of the present invention as defined in the appended claims.

Claims

1. A UWB-based wireless audio transmission device is characterized by comprising a sending end and a receiving end, wherein the sending end comprises an audio acquisition unit, an encoding and decoding unit, a CPU processing unit and a UWB module unit which are connected in sequence, the receiving end comprises a UWB module unit, a CPU processing unit, an encoding and decoding unit and an output playing unit which are connected in sequence, the UWB module unit where the sending end is located is in communication connection with the UWB module unit where the receiving end is located,

2. The UWB-based wireless audio transmission device according to claim 1, wherein the audio collection unit comprises an audio interface J1, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, an amplifier U3A and an amplifier U3B, the audio interface is used for receiving audio data, a pin 2 of the audio interface J1 is grounded, a pin 1 of the audio interface J1 is used as an output end to output the audio data to a post circuit, the pin 1 is connected with one end of a first parallel circuit, then is connected with one end of a capacitor C15 and a resistor R18 in series, then is connected with one end of a second parallel circuit, the other end of the first parallel circuit is grounded, the first parallel circuit comprises the capacitor C17 and the resistor R19 in parallel, the second parallel circuit comprises the capacitor C16 and the resistor R17 in parallel, one end of the second parallel circuit is further connected with a pin 2 of the amplifier U3A, the other end of the second parallel circuit is connected with a pin 1 of an amplifier U3A, a pin 3 of the amplifier U3A is grounded, an output end of an amplifier U3A connected with the other end of the second parallel circuit is also used as an output end AINA-, and is also connected with a pin 6 of the amplifier U3B and one end of a third parallel circuit after being connected with a resistor R20 in series, a pin 5 of an amplifier U3B is grounded, a pin 7 of an amplifier U3B is connected with the other end of the third parallel circuit and then is used as an output end AINA +, and the third parallel circuit comprises a resistor R21 and a capacitor C18 which are connected in parallel.

3. The UWB-based wireless audio transmission device according to claim 2, wherein the codec unit includes a codec chip U1, a reset terminal of the codec chip U1 is connected in series with a resistor R16 and then connected with a 3.3V voltage, a pin 15 of the codec chip U1 is connected with one terminal of a fourth parallel circuit, the other terminal of the fourth parallel circuit is grounded, the fourth parallel circuit includes a capacitor C13 and a capacitor C14 which are connected in parallel, a pin 16 and a pin 17 of the codec chip U1 are respectively connected with an output terminal AINA-, an output terminal AINA + of the audio acquisition unit, a pin 20 and a pin 21 of the codec chip U1 are respectively connected with both terminals of a fifth parallel circuit, the fifth parallel circuit includes a capacitor C7 and a capacitor C8 which are connected in parallel, the pin 20 is further connected with a 5V voltage, the pin 21 is connected with one terminal of the fifth parallel circuit and then grounded, a pin 2 of the codec chip U1 is connected in series with a resistor R2 and then grounded, the pin 8 of the coding and decoding chip U1 is grounded, the pin 9 and the pin 10 are connected together and then connected with one end of a sixth parallel circuit and then connected with 3.3V voltage, the other end of the sixth parallel circuit is grounded, the pin 11 and the pin 12 are connected with a CPU processing unit, the pin 13 of the coding and decoding chip U1 is connected with a resistor R15 in series and then connected with 3.3V voltage, the pin 24 of the coding and decoding chip U1 serves as an output terminal AOUTA-, the pin 25 of the coding and decoding chip U1 serves as an output terminal AOUTA +, and the decoded signal is sent to an output playing unit through the pin 24 and the pin 25.

4. The UWB based wireless audio transmission apparatus of claim 3, the CPU processing unit comprises an audio processing chip U4, a pin 57 and a pin 60 of the audio processing chip U4 are respectively connected with two ends of a seventh parallel circuit, one end of the seventh parallel circuit connected with the pin 57 is grounded, one end connected with the pin 60 is connected with the voltage DVCC, the seventh parallel circuit comprises a capacitor C23 and a capacitor C24, an I2C interface formed by a pin 51 and a pin 52 of the audio processing chip U4 is respectively connected with a pin 11 and a pin 12 of the coding and decoding chip U1, therefore, the CPU processing unit is connected with the coding and decoding chip U1, the pin 11, the pin 16, the pin 25, the pin 26, the pin 28 and the pin 29 of the audio processing chip U4 are respectively grounded, and the pin 30-the pin 33 of the audio processing chip U4 jointly form an SPI interface and are connected with the UWB module unit through the SPI interface.

5. The UWB based wireless audio transmission device of claim 4 wherein the codec chip U1 is model ADAU 1961.

6. The UWB-based wireless audio transmission device of claim 5 wherein the UWB module unit comprises a UWB chip U2, wherein a 3.3V voltage is connected after the connection of pin 5-pin 7 of the UWB chip U2, the connection of pin 8, pin 16, pin 21, pin 23, pin 24 is connected to ground, a 3.3V voltage is connected after the connection of pin 9 and pin 10 in series with a resistor R25 and a resistor R24 respectively, and the pin 17-pin 20 together form an SPI interface, thereby connecting with the SPI interface of the audio processing chip U4.

7. The UWB-based wireless audio transmission device according to claim 6, wherein the pin 17 of the UWB module unit is connected with the pin 33 of the CPU processing unit, the pin 18 of the UWB module unit is connected with the pin 31 of the CPU processing unit, the pin 19 of the UWB module unit is connected with the pin 32 of the CPU processing unit, and the pin 20 of the UWB module unit is connected with the pin 30 of the CPU processing unit.

8. The UWB-based wireless audio transmission apparatus according to claim 7, wherein the UWB chip U2 has a model number DW 1000.

9. The UWB-based wireless audio transmission apparatus according to claim 8, wherein the output playing unit includes a resistor R1, a resistor R3, a resistor R5, a resistor R6, a capacitor C6, an amplifier U2 6 and an amplifier U2 6, wherein one end of the resistor R6 is connected to an output terminal AOUTA-of a codec chip U6 of the codec unit, one end of the resistor R6 is connected to an output terminal AOUTA + of the codec chip U6 of the codec unit, the other end of the resistor R6 is connected to one end of the resistor R6, one end of the capacitor R6 and the other end of the resistor R6, the other end of the resistor R6 is connected to one end of a pin 2 of the amplifier U2 6, one end of the capacitor C6, the other end of the capacitor C6 is connected to ground, and the other end of the resistor R6 is connected to a capacitor R6 and the amplifier C6 is connected to a pin 6 and a capacitor R6 and a capacitor C6 and a pin 6 is connected to a pin 6, the pin 1 of the amplifier is connected with a pin 6 of an amplifier U2B after being sequentially connected with a capacitor C4 and a resistor R7 in series, the other end of the resistor R9 is connected with a pin 3 of the amplifier U2A after being connected with a resistor R10 in series, a connecting node between the resistor R9 and the resistor R10 is connected with one end of the resistor R14 and then grounded together, the other end of the resistor R14 is connected with a capacitor C12 and a capacitor C6 in series and then connected with a pin 3 of the amplifier U2A, a connecting node between the capacitor C12 and the capacitor C6 is grounded, a pin 5 of the amplifier U2B is grounded, one end of a resistor R7 connected with the amplifier U2B is further connected with one end of an eighth parallel circuit, the other end of the eighth parallel circuit is connected with a pin 7 of the amplifier U2B, the eighth parallel circuit comprises a capacitor C2 and a resistor R3 which are connected in parallel, the pin 7 of the amplifier U2B is further connected with the other end of the eighth parallel circuit in series with a capacitor C5 to serve as an output end LINE _ OUT, and the output end LINE _ OUT is used for outputting audio data to a play terminal accessed in a later stage.