CN216387895U - Low dropout voltage regulator circuit, chip and equipment - Google Patents
Low dropout voltage regulator circuit, chip and equipment Download PDFInfo
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- CN216387895U CN216387895U CN202123270329.4U CN202123270329U CN216387895U CN 216387895 U CN216387895 U CN 216387895U CN 202123270329 U CN202123270329 U CN 202123270329U CN 216387895 U CN216387895 U CN 216387895U
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Abstract
The utility model discloses a low dropout voltage regulator circuit, a chip and equipment, wherein the low dropout voltage regulator circuit comprises: the low dropout regulator comprises an operational amplifier and a first transistor; the bias circuit module is connected with the bias end of the operational amplifier and the control electrode of the first transistor and used for adjusting the bias current of the operational amplifier. According to the low dropout voltage regulator circuit provided by the embodiment of the utility model, the glitch on the output voltage can be effectively inhibited, the output voltage is ensured to be always in a relatively stable state, and the working effect of the load is improved.
Description
Technical Field
The utility model relates to the technical field of integrated circuits, in particular to a low dropout voltage regulator circuit, a chip and equipment.
Background
When the chip is not provided with the external output capacitor, the output capacitor integrated in the chip generally adopts a capacitor with a very small capacitance value, usually in a picofarad level, so that when the load is changed rapidly, burrs on the output voltage are easily too large or too small. Especially, for LDO (Low Dropout Regulator) circuit, if the glitch on the output voltage caused by the rapid load change cannot be effectively suppressed, the too high glitch may damage the negative voltageThe circuit is loaded, and too low glitch may cause the load not to work properly. For example, as shown in FIG. 1, wherein curve A1 represents the load current IRLCurve B1 shows the output voltage Vout, the load current I when the load is lighter relative to the reference valueRLThe output voltage Vout may rise and cause a glitch, and when the glitch is too large, the load circuit may be damaged. When the load is heavy, the load current IRLThe output voltage Vout will rise rapidly, which in turn will cause the output voltage Vout to drop and cause glitches, which may cause the load to fail to operate properly.
SUMMERY OF THE UTILITY MODEL
The present invention is directed to solving at least one of the problems of the prior art. Therefore, an object of the present invention is to provide a low dropout voltage regulator circuit, which can suppress glitches on an output voltage, so as to ensure that the output voltage is always in a relatively stable state, thereby improving the working effect of a load.
The second objective of the present invention is to provide a chip.
It is a further object of the utility model to provide an apparatus.
In order to achieve the above object, a low dropout voltage regulator circuit according to an embodiment of the present invention includes: a low dropout regulator including an operational amplifier and a first transistor; and the bias circuit module is connected with the bias end of the operational amplifier and the control electrode of the first transistor and is used for adjusting the bias current of the operational amplifier.
According to the low dropout voltage regulator circuit provided by the embodiment of the utility model, the bias circuit module is added between the low dropout voltage regulators, when the load changes, the bias circuit module can adjust the bias current input to the bias end of the operational amplifier, the frequency response bandwidth of the system is increased, and the output overcharge and overdischarge voltages can be effectively inhibited by inhibiting burrs on the output voltage, so that the situations that the load is damaged or cannot normally work due to the rapid change of the load can be effectively prevented, the output voltage is always in a relatively stable state, and the working effect of the load is improved.
In some embodiments of the utility model, the bias circuit module comprises: the current synchronization circuit is connected with the control electrode of the first transistor and is used for outputting a synchronization current signal synchronized with the second electrode current of the first transistor; the first current mirror unit is connected with the current synchronization unit and used for generating a first current regulation signal according to the synchronization current signal; and the second current mirror unit is connected with the first current mirror unit and the bias end of the operational amplifier and is used for generating a second current adjusting signal according to the first current adjusting signal so as to adjust the bias current of the operational amplifier.
In some embodiments of the present invention, the bias circuit module further comprises: and the delay circuit unit is connected with the first current mirror unit and is used for carrying out delay processing on the synchronous current signal.
In some embodiments of the utility model, the current synchronization unit comprises: and a first pole of the second transistor is connected with a preset power supply, a second pole of the second transistor is connected with the first current mirror unit, and a control pole of the second transistor is connected with the operational amplifier and the control pole of the first transistor.
In some embodiments of the present invention, the first current mirror unit includes: a third transistor, a first pole of the third transistor being grounded, a second pole of the third transistor and a control pole of the third transistor being connected to a second pole of the second transistor; a fourth transistor, a first electrode of which is grounded, a second electrode of which is connected to the second current mirror unit, and a control electrode of which is connected to the delay circuit unit; a fifth transistor, a first electrode of which is grounded, a second electrode of which is connected to a second electrode of the fourth transistor and the second current mirror unit, and a control electrode of which is connected to a control electrode of the third transistor and a second electrode of the second transistor.
In some embodiments of the utility model, the second current mirror unit comprises: a sixth transistor, a first pole of which is connected to a preset power supply, a second pole of which is connected to a second pole of the fourth transistor and a second pole of the fifth transistor, and a control pole of which is connected to a second pole of the sixth transistor; a seventh transistor, a first pole of the seventh transistor is connected to a preset power supply, a second pole of the seventh transistor is connected to the bias terminal of the operational amplifier, and a control pole of the seventh transistor is connected to a control pole of the sixth transistor and a second pole of the sixth transistor.
In some embodiments of the present invention, the delay circuit unit includes: a first end of the resistor is connected with the second pole of the second transistor and the control pole of the third transistor, and a second end of the resistor is connected with the control pole of the fifth transistor; and a first end of the first capacitor is connected with the second end of the resistor and the control electrode of the fifth transistor, and a second end of the first capacitor is grounded.
In some embodiments of the present invention, the low dropout regulator further comprises: a first end of the feedback circuit unit is connected with the second pole of the first transistor, and a second end of the feedback circuit unit is connected with the first input end of the operational amplifier and used for detecting a feedback signal; the second input end of the operational amplifier is used for receiving a reference signal, and the output end of the operational amplifier is connected with the control electrode of the first transistor.
In some embodiments of the present invention, the low dropout voltage regulator circuit further comprises: and a first end of the output capacitor is connected with the second pole of the first transistor, and a second end of the output capacitor is grounded.
In order to achieve the above object, a chip according to an embodiment of a second aspect of the present invention includes the low dropout voltage regulator circuit according to any of the above embodiments.
According to the chip provided by the embodiment of the utility model, the low dropout voltage regulator circuit provided by the first aspect of the utility model is integrated in the chip, and the bias circuit module is added in the low dropout voltage regulator, so that the glitch on the output voltage can be effectively inhibited when the load connected with the chip is rapidly changed, the output voltage can be always kept in a relatively stable state, the load can be effectively prevented from being damaged or not normally working, and the like, thereby ensuring the working stability of the chip and improving the working effect of the load.
In order to achieve the above object, an embodiment of the third aspect of the present invention further provides an apparatus, which is characterized by comprising an apparatus body and the chip provided in the embodiment of the second aspect, wherein the chip is disposed on the apparatus body.
According to the device provided by the embodiment of the utility model, by adopting the chip in the second aspect, namely adding the bias circuit module in the low dropout voltage regulator circuit in the chip, the glitch on the output voltage can be effectively inhibited when the load is changed rapidly, so that the output voltage can be kept in a relatively stable state all the time, the load can be effectively prevented from being damaged or working normally, and the like, thereby ensuring that the device can be always in a stable working state and improving the working effect of the load.
Additional aspects and advantages of the utility model will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the utility model.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a diagram illustrating the variation of output voltage and load current in the prior art;
FIG. 2 is a schematic diagram of a low dropout voltage regulator circuit according to one embodiment of the present invention;
FIG. 3 is a block diagram of a bias circuit module according to one embodiment of the utility model;
FIG. 4 is a schematic diagram of a low dropout voltage regulator circuit according to another embodiment of the present invention;
FIG. 5 is a schematic diagram of the variation of the output voltage and the load current according to one embodiment of the present invention;
FIG. 6 is a block diagram of a chip according to one embodiment of the utility model;
fig. 7 is a block diagram of an apparatus according to one embodiment of the utility model.
Reference numerals:
an apparatus 1000;
the low dropout regulator 1 and the bias circuit module 2;
a feedback circuit unit 13, a current synchronization unit 21, a first current mirror unit 22, a second current mirror unit 23, a delay circuit unit 24;
the operational amplifier AMP, the first transistor MPASS, the second transistor MP2, the third transistor MN3, the fourth transistor MN4, the fifth transistor MN5, the sixth transistor MP6, the seventh transistor MP7, the load RL, the resistor R1, the first capacitor C1 and the output capacitor CL.
Detailed Description
So that the manner in which the features and aspects of the embodiments of the present invention can be understood in detail, a more particular description of the embodiments of the utility model, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.
2-5, a low dropout voltage regulator circuit 10 according to an embodiment of the present invention is described.
In some embodiments of the present invention, as shown in fig. 2, a schematic diagram of a low dropout voltage regulator circuit 10 according to an embodiment of the present invention is shown, wherein the low dropout voltage regulator circuit 10 includes a low dropout voltage regulator 1 and a bias circuit module 2.
In an embodiment, the LDO 1 generates a regulated output voltage by subtracting excess voltage from the input voltage using a Transistor or FET, such as a FET, operating in its saturation region. By droop voltage is meant the minimum value of the difference between the input voltage and the output voltage required by the regulator to maintain the output voltage within 100mV above or below its nominal value. The low dropout regulator 1 has low cost, low noise and small quiescent current, and the low dropout regulator 1 also has other functions such as load short circuit protection, overvoltage shutoff, overheat shutoff, reverse connection protection and the like.
Specifically, the low dropout regulator 1 includes an operational amplifier AMP and a first transistor MPASS. The second input of the operational amplifier AMP is for receiving a reference signal, wherein the reference signal may be denoted Vref, wherein the reference signal Vref may be a reference voltage. The output terminal of the operational amplifier AMP is connected to the control electrode of the first transistor MPASS. The first transistor MPASS is an output modulation transistor for modulating the output signal, so as to obtain the output voltage Vout for providing to the load RL.
And, the low dropout regulator 1 further comprises a feedback circuit unit 13. A first terminal of the feedback circuit unit 13 is connected to the second pole of the first transistor MPASS, and a second terminal of the feedback circuit unit 13 is connected to the first input terminal of the operational amplifier AMP, for detecting the feedback signal. The feedback circuit unit 13 is a feedback loop, and is configured to obtain a feedback signal according to the output voltage Vout and feed back the feedback signal to the first input terminal of the operational amplifier AMP. The operational amplifier AMP receives the reference signal Verf according to the feedback signal inputted from the first input terminal and the second input terminal, and modulates the reference signal Verf by the first transistor MPASS to obtain the output voltage Vout.
Further, in the embodiment of the present invention, a bias circuit module 2 is added between the low dropout regulator 1, and the bias circuit module 2 of the embodiment of the present invention is connected to the bias terminal of the operational amplifier AMP and the control electrode of the first transistor MPASS, and is used for adjusting the bias current of the operational amplifier AMP. The bias end of the operational amplifier AMP is connected with a preset power supply and a bias circuit module 2, the preset power supply is used for providing bias current ISS for the operational amplifier AMP, and the bias circuit module 2 is used for adjusting the bias current ISS input to the bias end of the operational amplifier AMP according to the change situation of the load RL.
Specifically, when the load RL suddenly gets heavier, the load current IRLThe output voltage Vout will decrease as the rise is fast. By arranging the bias circuit module 2, the bias current ISS input to the bias end of the operational amplifier AMP is increased and adjusted to increase the bandwidth of the operational amplifier AMP, the reaction speed of a system is increased, the output over-discharge voltage is restrained, and the phenomenon that the load RL cannot work normally due to the fact that the output voltage Vout is reduced and burrs occur is avoided. When the load RL suddenly becomes light, the load current IRLAnd rapidly decreases, the output voltage Vout rises. By arranging the bias circuit module 2, the bias current ISS input to the bias end of the operational amplifier AMP can be adjusted to lag behind the load change, so that the system can still keep a high-speed state and slowly drop, the output overcharging voltage is restrained, and the phenomenon that the load RL cannot normally work due to the fact that the output voltage Vout rises and burrs occur can be avoided.
According to the low dropout voltage regulator circuit 10 provided by the embodiment of the utility model, by adding the bias circuit module 2 between the low dropout voltage regulators 1, when the load RL changes, the bias circuit module 2 can adjust the bias current ISS input to the bias end of the operational amplifier AMP, the frequency response bandwidth of the system is increased, and the output overcharge and overdischarge voltages can be effectively inhibited by inhibiting the glitch on the output voltage Vout, so that the situations that the load RL is damaged or cannot normally work due to the rapid change of the load RL can be effectively prevented, the output voltage Vout is always in a relatively stable state, and the working effect of the load RL is improved.
In some embodiments of the present invention, the bias circuit module 2 includes a current synchronization unit 21, a first current mirror unit 22, a second current mirror unit 23, and a delay circuit unit 24.
The bias circuit module 2 of the embodiment of the present invention can be described with reference to fig. 3 and 4. FIG. 3 is a block diagram of a bias circuit module according to an embodiment of the utility model; FIG. 4 is a diagram illustrating a low dropout voltage regulator circuit according to another embodiment of the present invention.
The current synchronization circuit 21 is connected to the control electrode of the first transistor MPASS, and is configured to output a synchronization current signal synchronized with the second electrode current of the first transistor MPASS.
Specifically, as shown in fig. 4, the second pole of the first transistor MPASS, i.e. the drain of the first transistor MPASS, is used for outputting a drain current, i.e. the second pole current of the first transistor MPASS, which may be denoted as ID-MPASS. More specifically, the current synchronizing unit 21 includes a second transistor MP 2. A first pole of the second transistor MP2 is connected to a predetermined power source, a second pole of the second transistor MP2 is connected to the first current mirror unit 22, and a control pole of the second transistor MP2 is connected to the output terminal of the operational amplifier AMP and the control pole of the first transistor MPASS. Since the first pole of the first transistor MPASS is connected to the predetermined power source, it can be understood that the gate voltage of the second transistor MP2 is the same as the gate voltage of the first transistor MPASS, and the control pole of the second transistor MP2 is connected to the control pole of the first transistor MPASS, and the current of the drain of the second transistor MP2 varies with the drain current of the first transistor MPASS. The current at the drain of the second transistor MP2, i.e. the synchronous current signal, is used together with ID-MP2And (4) showing. That is, the synchronous current signal I outputted from the current synchronization circuit 21D-MP2With a second polarity current I of the first transistor MPASSD-MPASSAre synchronized.
The first current mirror unit 22 is connected to the current synchronization unit 21 for synchronizing the current I according to the synchronization current signalD-MP2A first current adjustment signal is generated. Specifically, in the embodiment, the first current mirror unit 22 (not shown in fig. 4) includes a third transistor MN3, a fourth transistor MN4, and a fifth transistor MN 5. Wherein, as shown in FIG. 4, the first pole of the third transistor MN3 is connectedThe second pole of the third transistor MN3 and the control pole of the third transistor MN3 are both connected to the second pole of the second transistor MP 2. A first pole of the fourth transistor MN4 is grounded, a second pole of the fourth transistor MN4 is connected to the second current mirror unit 23, and a control pole of the fourth transistor MN4 is connected to the delay circuit unit 24. A first pole of the fifth transistor MN5 is grounded, a second pole of the fifth transistor MN5 is connected to a second pole of the fourth transistor MN4 and the second current mirror unit 23, and a control pole of the fifth transistor MN5 is connected to a control pole of the third transistor MN3 and a second pole of the second transistor MP 2.
The control electrode of the fourth transistor MN4 is connected to the second electrode and the control electrode of the third transistor MN3, the first electrode of the fourth transistor MN4 and the first electrode of the third transistor MN3 are both grounded, and the drain current of the fourth transistor MN4 is proportional to the drain current of the third transistor MN 3. The control electrode of the fifth transistor MN5 is connected to the control electrode of the third transistor MN3, the first electrode of the fifth transistor MN5 and the first electrode of the third transistor MN3 are both grounded, and the drain current of the fifth transistor MN5 is proportional to the drain current of the third transistor MN 3.
In other embodiments, as shown in fig. 4, the second current mirror unit 23 is connected to the first current mirror unit 21 and the bias terminal of the operational amplifier AMP, and is configured to generate a second current adjusting signal according to the first current adjusting signal to adjust the bias current of the operational amplifier AMP.
Specifically, the second current mirror unit 23 includes a sixth transistor MP6 and a seventh transistor MP 7. A first pole of the sixth transistor MP6 is connected to the preset power source, a second pole of the sixth transistor MP6 is connected to the second pole of the fourth transistor MN4 and the second pole of the fifth transistor MN5, and a control pole of the sixth transistor MP6 is connected to the second pole of the sixth transistor MP 6. A first pole of the seventh transistor MP7 is connected to a predetermined power source, a second pole of the seventh transistor MP7 is connected to the bias terminal of the operational amplifier AMP, and a control pole of the seventh transistor MP7 is connected to the control pole of the sixth transistor MP6 and the second pole of the sixth transistor MP 6.
Since the first pole of the sixth transistor MP6 and the first pole of the seventh transistor MP7 are both connected to the preset power source, it can be understood that the gate voltages of the sixth transistor MP6 and the seventh transistor MP7 are the same, the control pole of the sixth transistor MP6 is connected to the second pole and the control pole of the seventh transistor MP7, and the current of the drain of the sixth transistor MP6 changes with the change of the drain current of the seventh transistor MP 7. The current of the drain of the seventh transistor MP7, i.e., the output current of the second pole of the seventh transistor MP7, is the second current adjustment signal, and the second current adjustment signal is proportional to the drain current of the sixth transistor MP 6.
Since the second pole of the seventh transistor MP7 is connected to the bias terminal of the operational amplifier AMP, when the output load current changes, the drain current of the seventh transistor MP7 also changes, i.e. the output second current adjusting signal I is outputD-MP7The output load current changes two to generate corresponding changes, so that the bias current ISS input to the offset end of the operational amplifier AMP can be adjusted, and the function of adjusting the bias current ISS can be realized.
Further, when the load current IRLWhen the current of the drain of the second transistor MP2 increases, the current flowing to the fourth transistor MN4 increases, and the drain current of the sixth transistor MP6 also increases, at this time, the increased current of the drain current of the sixth transistor MP6 causes the bias current ISS input to the offset terminal of the operational amplifier AMP to increase, thereby increasing the bandwidth of the operational amplifier AMP.
Further, the load current I of the embodiment of the present invention is described with reference to FIG. 5RLAnd the output voltage Vout, as shown in FIG. 5, which is a schematic diagram of the output voltage and the load current variation according to an embodiment of the present invention, wherein the curve A1 represents the load current IRLCurve B2 shows the output voltage Vout after adding the bias circuit block 2.
According to the bias circuit module 2 of the embodiment of the present invention, based on the architectures of the current synchronization unit 21, the first current mirror unit 22 and the second current mirror unit 23, when the load RL suddenly gets heavier, the load current IRLThe rapid rise (produced as curve a1 in fig. 5)Rising edge), the output voltage Vout will decrease. The bandwidth of the operational amplifier AMP is increased by increasing the bias current ISS input to the offset end of the operational amplifier AMP, the responsiveness of a system is improved, over-discharge voltage is suppressed, and further the output voltage Vout can be ensured to be kept in a relatively stable state as shown in a curve B2, or even if the output voltage Vout has burrs, the burrs are kept in a normal range, and the phenomenon that the load RL cannot normally work due to the fact that the output voltage Vout is reduced and the burrs occur is avoided.
In other embodiments of the present invention, as shown in fig. 3, the bias circuit module 2 further includes a delay circuit unit 24, wherein the delay circuit unit 24 is connected to the first current mirror unit 22 for performing a delay process on the synchronous current signal.
Specifically, as shown in fig. 4, the delay circuit unit 24 includes a resistor R1 and a first capacitor C1. A first terminal of the resistor R1 is connected to the second terminal of the second transistor MP2 and the control terminal of the third transistor MN3, and a second terminal of the resistor R1 is connected to the control terminal of the fifth transistor MN 5. A first terminal of the first capacitor C1 is connected to the second terminal of the resistor R1 and the gate of the fifth transistor MN5, and a second terminal of the first capacitor C1 is grounded.
The delay circuit unit 24 formed by the resistor R1 and the first capacitor C1 makes the change of the drain current of the fifth transistor MN5, i.e. the second pole current, lag behind the change of the load current, for example, the delay time period may be set to be less than 1 microsecond, i.e. the drain current of the fifth transistor MN5 changes after the change of the load current and a certain delay time period. Thus even at the load current IRLWhen the drain current ID-MN5 of the fifth transistor MN5 is rapidly decreased, the drain current ID-MN5 is still high for a short time, so that the system is still in a high-speed state.
According to the bias circuit module 2 of the embodiment of the present invention, by providing the delay circuit unit 24 based on the circuit structures of the current synchronization unit 21, the first current mirror unit 22, the second current mirror unit 23, and the delay circuit unit 24, when the load RL suddenly becomes light, the load current I is setRLWhen the output voltage Vout is decreased rapidly (e.g., the falling edge is generated by curve A1 in FIG. 5), the output voltage Vout will be increasedAnd (4) rising. By controlling the change of the drain current of the fifth transistor MN5 to lag the change of the load current, the bias current ISS input to the bias terminal of the operational amplifier AMP can be adjusted to lag the change of the load, so that the system still maintains a high speed state, and the system is slowly decreased, and the output overcharge voltage can be suppressed. Therefore, the output voltage Vout can be kept in a relatively stable state as shown in a curve B2, or even if the output voltage Vout has burrs, the burrs are kept in a normal range, and the phenomenon that the load RL cannot normally work due to the fact that the output voltage Vout rises and the burrs occur is avoided.
Based on the above, by providing the bias circuit module 2, the glitch on the output voltage Vout caused when the load RL changes rapidly can be effectively suppressed, for example, the glitch on the output voltage Vout is controlled to be small, and the output voltage Vout is ensured to be always in a relatively stable state, so that the load RL is effectively prevented from being damaged or cannot work normally, and the like. For example, referring to FIG. 5, it can be seen that no matter the load current IRLThe output voltage Vout is rapidly increased or decreased and is always kept in a normal state, or even if burrs occur on the output voltage Vout when the load RL is changed, the increase or decrease value of the output voltage Vout can be ensured to be less than or equal to 10% of the normal value, so that the working effect of the load RL is improved.
In other embodiments of the present invention, as shown in fig. 4, the low dropout voltage regulator circuit 10 further comprises an output capacitor CL. A first terminal of the output capacitor CL is connected to the second terminal of the first transistor MPASS, and a second terminal of the output capacitor CL is grounded. The output capacitor CL is an on-chip capacitor.
In some embodiments of the utility model, as shown in FIG. 6, a block diagram of a chip according to an embodiment of the utility model is shown, wherein the chip 100 includes the low dropout voltage regulator circuit 10 of any of the above embodiments.
According to the chip 100 provided by the embodiment of the present invention, the low dropout voltage regulator 10 according to the above first aspect of the embodiment is integrated in the chip 100, and the bias circuit module 2 is added in the low dropout voltage regulator 1, so that when the load RL changes rapidly, the glitch on the output voltage Vout can be effectively suppressed, the output voltage Vout can be kept in a relatively stable state all the time, the load RL can be effectively prevented from being damaged or failing to work normally, and the like, thereby ensuring the working stability of the chip 100 and improving the working effect of the load RL.
In other embodiments of the present invention, an apparatus 1000 is further proposed, as shown in fig. 7, which is a block diagram of an apparatus according to an embodiment of the present invention, wherein the apparatus 1000 includes an apparatus body 200 and the chip 100 proposed in the above second aspect embodiment, and the chip 100 is disposed on the apparatus body 200.
Wherein, the device 1000 may be a consumable device, and in the West lake and running state of the device, when the load RL is damaged or can not work normally, the load current IRLWhen the load is heavy, the bias circuit module 2 can adjust the bias current ISS input to the bias terminal of the operational amplifier AMP to increase, so as to increase the bandwidth of the operational amplifier AMP, improve the responsiveness of the system, and suppress the output over-discharge voltage. When the load becomes light, the delay circuit unit 24 in the bias circuit module 2 can adjust the bias current ISS input to the bias terminal of the operational amplifier AMP to lag behind the load change, so that the system still maintains a high-speed state and slowly drops, and the output overcharge voltage is suppressed.
According to the device 1000 provided by the embodiment of the present invention, by using the chip 100 according to the above second aspect embodiment, that is, by adding the bias circuit module 2 inside the low dropout voltage regulator circuit 10 inside the chip 100, when the load RL changes rapidly, the glitch on the output voltage Vout can be effectively suppressed, so that the output voltage Vout can always maintain a relatively stable state, and the situations that the load RL is damaged or cannot normally work and the like can be effectively prevented, so that the device 1000 can always be in a stable working state, and the working effect of the load RL is improved.
Other constructions and operations of the device 1000 and the chip 10 according to embodiments of the utility model are known to those skilled in the art and will not be described in detail herein.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
While embodiments of the utility model have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the utility model, the scope of which is defined by the claims and their equivalents.
Claims (11)
1. A low dropout voltage regulator circuit, comprising:
a low dropout regulator including an operational amplifier and a first transistor;
and the bias circuit module is connected with the bias end of the operational amplifier and the control electrode of the first transistor and is used for adjusting the bias current of the operational amplifier.
2. The low dropout voltage regulator circuit of claim 1, wherein the bias circuit module comprises:
the current synchronization circuit is connected with the control electrode of the first transistor and is used for outputting a synchronization current signal synchronized with the second electrode current of the first transistor;
the first current mirror unit is connected with the current synchronization unit and used for generating a first current regulation signal according to the synchronization current signal;
and the second current mirror unit is connected with the first current mirror unit and the bias end of the operational amplifier and is used for generating a second current adjusting signal according to the first current adjusting signal so as to adjust the bias current of the operational amplifier.
3. The low dropout voltage regulator circuit of claim 2, wherein the bias circuit module further comprises:
and the delay circuit unit is connected with the first current mirror unit and is used for carrying out delay processing on the synchronous current signal.
4. The low dropout voltage regulator circuit of claim 3, wherein the current synchronization unit comprises:
and a first pole of the second transistor is connected with a preset power supply, a second pole of the second transistor is connected with the first current mirror unit, and a control pole of the second transistor is connected with the operational amplifier and the control pole of the first transistor.
5. The low dropout voltage regulator circuit of claim 4, wherein the first current mirror unit comprises:
a third transistor, a first pole of the third transistor being grounded, a second pole of the third transistor and a control pole of the third transistor being connected to a second pole of the second transistor;
a fourth transistor, a first electrode of which is grounded, a second electrode of which is connected to the second current mirror unit, and a control electrode of which is connected to the delay circuit unit;
a fifth transistor, a first electrode of which is grounded, a second electrode of which is connected to a second electrode of the fourth transistor and the second current mirror unit, and a control electrode of which is connected to a control electrode of the third transistor and a second electrode of the second transistor.
6. The low dropout voltage regulator circuit of claim 5, wherein the second current mirror unit comprises:
a sixth transistor, a first pole of which is connected to a preset power supply, a second pole of which is connected to a second pole of the fourth transistor and a second pole of the fifth transistor, and a control pole of which is connected to a second pole of the sixth transistor;
a seventh transistor, a first pole of the seventh transistor is connected to a preset power supply, a second pole of the seventh transistor is connected to the bias terminal of the operational amplifier, and a control pole of the seventh transistor is connected to a control pole of the sixth transistor and a second pole of the sixth transistor.
7. The low dropout voltage regulator circuit of claim 5, wherein the delay circuit unit comprises:
a first end of the resistor is connected with the second pole of the second transistor and the control pole of the third transistor, and a second end of the resistor is connected with the control pole of the fifth transistor;
and a first end of the first capacitor is connected with the second end of the resistor and the control electrode of the fifth transistor, and a second end of the first capacitor is grounded.
8. The low dropout voltage regulator circuit of any one of claims 1-7, further comprising:
a first end of the feedback circuit unit is connected with the second pole of the first transistor, and a second end of the feedback circuit unit is connected with the first input end of the operational amplifier and used for detecting a feedback signal;
the second input end of the operational amplifier is used for receiving a reference signal, and the output end of the operational amplifier is connected with the control electrode of the first transistor.
9. The low dropout voltage regulator circuit of claim 8, further comprising:
and a first end of the output capacitor is connected with the second pole of the first transistor, and a second end of the output capacitor is grounded.
10. A chip comprising the low dropout voltage regulator circuit of any one of claims 1-9.
11. A device comprising a device body and the chip of claim 10, the chip being disposed on the device body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123270329.4U CN216387895U (en) | 2021-12-21 | 2021-12-21 | Low dropout voltage regulator circuit, chip and equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123270329.4U CN216387895U (en) | 2021-12-21 | 2021-12-21 | Low dropout voltage regulator circuit, chip and equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114578892A (en) * | 2022-05-05 | 2022-06-03 | 深圳芯能半导体技术有限公司 | Linear voltage stabilizing circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114578892A (en) * | 2022-05-05 | 2022-06-03 | 深圳芯能半导体技术有限公司 | Linear voltage stabilizing circuit |
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Address after: Room 202, Building G10, South China New Material Innovation Park, No. 31, Kefeng Road, High-tech Industrial Development Zone, Guangzhou, Guangdong, 510700 Patentee after: Guangzhou Zhongnuo Microelectronics Co.,Ltd. Address before: 510663 No. 202, G10 building, Southern China new material innovation park, No. 31, Ke Feng Road, Guangzhou hi tech Industrial Development Zone, Guangdong Patentee before: GUANGZHOU ZHONO ELECTRONIC TECHNOLOGY Co.,Ltd. |