CN216362303U - RF Signal Transceiver System Based on FPGA - Google Patents

Abstract

The utility model discloses a radio frequency signal receiving and transmitting system based on FPGA (field programmable gate array), which belongs to the technical field of wireless communication and comprises a data processing unit, an analog-digital signal acquisition unit, a signal transmitting unit and an optical receiving and transmitting unit, wherein the analog-digital signal acquisition unit, the signal transmitting unit and the optical receiving and transmitting unit are connected with the data processing unit; the system also comprises a clock unit, wherein the output end of the clock unit is connected with the data processing unit, the analog-digital signal acquisition unit and the signal transmitting unit. The utility model improves the signal direct-collecting rate by arranging a plurality of signal acquisition channels and the optical transceiver module, and can meet the high-speed and real-time data acquisition and transmission scenes; meanwhile, the analog-digital signal acquisition unit, the signal transmitting unit and the data processing unit are connected with the same clock signal, so that the synchronism of multi-channel data acquisition is ensured.

Description

RF Signal Transceiver System Based on FPGA

technical field

The utility model relates to the technical field of wireless communication, in particular to a radio frequency signal transceiver system based on FPGA.

Background technique

Wireless communication includes two parts: signal acquisition and transmission. Signal acquisition is to receive optical signals and electrical signals through signal receiving devices (optical receiving modules, antennas), and then go through the steps of conditioning, sampling, quantization, coding, and transmission. The controller performs the process of data processing or storage and recording, and signal transmission is the transmission of signals through modulation and other means. In practical engineering applications, the transceiver system is required to have the characteristics of real-time processing, high speed, multi-channel and system stability to meet the needs of application scenarios such as radio monitoring and communication radar testing. High-speed, real-time data acquisition depends on the data acquisition rate on the one hand, and on the performance of the controller that processes the data on the other. In addition, in the field of traditional data acquisition, high-speed data acquisition can be achieved by adding data acquisition channels. However, for multi-channel data acquisition, the synchronization between channels is often a key part of the data acquisition system. How to realize the multi-channel signal The synchronization of acquisition is also one of the technical problems that need to be solved urgently.

Utility model content

The purpose of the utility model is to overcome the problems of low signal acquisition rate and poor synchronization in the signal transceiver system in the prior art, and provide a radio frequency signal transceiver system based on FPGA.

The purpose of the utility model is achieved through the following technical solutions: an FPGA-based radio frequency signal transceiver system, the system includes a data processing unit, an analog-digital signal acquisition unit, a signal transmitting unit, an optical transceiver unit connected with the data processing unit, an analog-digital The signal acquisition unit includes a plurality of signal acquisition channels, and the optical transceiver unit includes a plurality of optical transceiver modules; the system further includes a clock unit, the output end of the clock unit is connected with the data processing unit, the analog-digital signal acquisition unit, and the signal transmission unit.

In an example, the data processing unit includes an FPGA and a single-chip microcomputer connected in sequence, the FPGA is connected with a first temperature sensor, and the first temperature sensor is arranged close to the FPGA.

In an example, the analog-digital signal acquisition unit includes several signal receiving channels, the signal receiving channels include a radio frequency interface, a balun matching circuit and an ADC chip connected in sequence, and the output end of the ADC chip is connected to the data processing unit via the SPI bus.

In an example, the signal transmitting unit includes a plurality of signal transmitting channels, the signal transmitting channels include a DAC chip, a driving circuit and a radio frequency interface connected in sequence, and the DAC chip is connected to the output end of the data processing unit via an SPI bus.

In an example, the optical transceiver unit is a multi-channel parallel optical receiving module.

In one example, the system further includes a trigger circuit including a buffer and a signal input device connected in sequence, the buffer being connected to the data processing unit.

In an example, the clock unit includes a temperature compensated crystal oscillator and a PLL frequency synthesizer connected in sequence, and the output end of the PLL frequency synthesizer is connected to the analog-to-digital signal acquisition unit and the signal transmission unit.

In one example, the system further includes an eMMC data storage unit connected to the data processing unit.

In an example, the system further includes a power supply unit, and the power supply unit includes a power supply circuit for providing operating voltages for the data processing unit, the analog-to-digital signal acquisition unit, the signal transmission unit, the optical transceiver unit, and the clock unit.

In an example, the system further includes a monitoring unit, the monitoring unit includes a voltage sensor and a second temperature sensor connected to the input end of the data processing unit, and both the voltage sensor and the second temperature sensor are arranged close to the power circuit.

It should be further noted that the technical features corresponding to the above examples may be combined with each other or replaced to form a new technical solution.

Compared with the prior art, the beneficial effects of the present utility model are:

1. In an example, by setting up multiple signal acquisition channels and optical transceiver modules to increase the signal direct collection rate, high-speed and real-time data acquisition and transmission scenarios can be met; at the same time, the analog-to-digital signal acquisition unit, signal transmission unit and data processing unit Access to the same clock signal to ensure the synchronization of multi-channel data acquisition.

2. In an example, the real-time working temperature of the FPGA is monitored by the first sensor to ensure its working stability.

3. In an example, the single-port signal is converted through a balun matching circuit to obtain a differential signal with high gain, anti-electromagnetic interference, power supply noise, and ground noise resistance; data transmission based on the SPI bus, Guaranteed high-speed transmission of signals.

4. In an example, the signal transmission rate can be ensured through multiple signal transmission channels, and the real-time nature of signal transmission can be ensured.

5. In an example, high-speed optical signal transmission is achieved through multiple parallel optical receiving modules.

6. In an example, an external trigger is used to control the start time of data acquisition through a trigger circuit to meet different data acquisition requirements.

7. In one example, the temperature-compensated crystal oscillator ensures that the synthesized clock frequency is more stable and accurate.

8. In one example, mass data storage is achieved through an eMMC data storage unit.

9. In an example, whether the voltage output of the power supply unit is abnormal is detected by a voltage sensor, and the working temperature of the power supply is detected based on the second temperature sensor, so as to ensure the working stability and reliability of the voltage unit.

Description of drawings

The specific embodiments of the present utility model will be described in further detail below in conjunction with the accompanying drawings. The accompanying drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application, and the same reference numerals are used in these drawings to represent The same or similar parts, the exemplary embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application.

1 is a system block diagram in an example of the present invention;

FIG. 2 is a system block diagram of a preferred example of the present invention.

Detailed ways

The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

In the description of the present utility model, it should be noted that "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" The directions or positional relationships indicated by etc. are based on the directions or positional relationships described in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, a specific orientation, or a specific orientation. Therefore, it should not be construed as a limitation on the present invention. Furthermore, the references to "first" and "second" are for descriptive purposes only, and should not be construed as indicating or implying relative importance.

In the description of the present utility model, it should be noted that, unless otherwise expressly specified and limited, “installation”, “connection” and “connection” should be understood in a broad sense, for example, it may be a fixed connection or a flexible connection Detachable connection, or integral connection; may be mechanical connection or electrical connection; may be direct connection, or indirect connection through an intermediate medium, or internal communication between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific situations.

In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as there is no conflict with each other.

In an example, an FPGA-based radio frequency signal transceiver system, as shown in FIG. 1 , specifically includes a data processing unit, an analog-to-digital signal acquisition unit, a signal transmission unit, an optical transceiver unit, and a clock unit. Specifically, the data processing unit, as the control core of the whole system, includes an FPGA for data processing. The output end of the analog-digital signal acquisition unit is connected with the data processing unit, and includes a plurality of signal acquisition channels for acquiring radio frequency signals. The signal transmitting unit is connected with the output end of the data processing unit, and is used for transmitting radio frequency signals. The optical transceiver unit and the data processing unit are bidirectionally connected, including multiple optical transceiver modules, which can be used for optical signal transmission and reception, which improves the system transceiver compatibility. Combining the above-mentioned multiple signal acquisition channels can significantly improve the signal acquisition rate and meet high-speed requirements. and real-time data collection and transmission scenarios. The output end of the clock unit is connected to the data processing unit, the analog-to-digital signal acquisition unit, and the signal transmission unit. Even if the analog-to-digital signal acquisition unit, the signal transmission unit and the data processing unit are connected to the same clock signal, the clock frequency of each unit of the system is synchronized to ensure that Synchronization of signal transmission and reception.

In an example, the data processing unit is sequentially connected with the communication unit and the upper computer, so as to realize communication with the upper computer and realize data sharing. Among them, the communication unit is any one of a WIFI communication module, a mobile communication module, a narrowband Internet of Things communication module, and a serial communication module. The data communication terminal of the communication unit communicates with the communication port of the upper computer and the FPGA in the data processing unit. port connection to establish a two-way communication connection.

In an example, the data processing unit includes an FPGA and a single-chip microcomputer connected in sequence, the FPGA is connected with a first temperature sensor and an LED indicator light, and the first temperature sensor is arranged close to the FPGA. In this example, the FPGA chip XC7K325T-2FFG900I of XILINX is specifically used to ensure the data processing capability. The microcontroller is specifically the STM32 series of microcontrollers, and the microcontroller and the FPGA communicate through the SPI bus. The data transmission pin of the first temperature sensor PT100 is connected to the I/O terminal of the FPGA, so as to transmit the collected working temperature information of the FPGA to the FPGA. When the working temperature exceeds the threshold, the FPGA controls the LED indicator to flash and alarm, which ensures the work of the FPGA chip. of stability. Of course, as an option, the output end of the first temperature sensor can be connected to the single-chip microcomputer, and at this time, the output end of the single-chip microcomputer is correspondingly connected with an LED indicator light.

It should be further noted that the circuit modules used in this application, that is, chips such as sensors, controllers, and analog-to-digital converters, are all existing chips. Those skilled in the art can check the corresponding chip manuals for details on the working principles and connection methods of the chips. , belongs to the common knowledge of those skilled in the art, and the present utility model will not further elaborate the pin connection relationship between the chips.

In an example, the analog-digital signal acquisition unit includes several signal receiving channels, the signal receiving channels include a radio frequency interface, a balun matching circuit and an ADC chip connected in sequence, and the output end of the ADC chip is connected to the data processing unit via the SPI bus. Among them, the radio frequency interface is the SAM interface, which receives the radio frequency signal through the SMA interface, and the balun matching circuit converts the single-port radio frequency signal to obtain a differential with high gain, anti-electromagnetic interference, power supply noise, and ground noise resistance. The signal and differential signal are transmitted to the ADC chip, that is, the ADC083000 realizes the analog-to-digital conversion processing of the signal to obtain a digital signal and transmits it to the FPGA, and the FPGA performs data processing on the digital signal to extract valid information.

In an example, the signal transmitting unit includes a plurality of signal transmitting channels, the signal transmitting channels include a DAC chip, a driving circuit and a radio frequency interface connected in sequence, and the DAC chip is connected to the output end of the data processing unit via an SPI bus. Among them, the DAC chip, that is, DAC9739, converts the digital signal transmitted by the FPGA to obtain an analog signal, which is driven by the driving circuit, that is, the driver, and finally radiated to the external system through the SMA interface of the radio frequency interface. In this example, the signal transmission rate can be guaranteed by using multiple signal transmission channels, and the real-time nature of signal transmission can be ensured.

In an example, the optical transceiver unit is a 12-channel parallel optical receiving module HTA8530PH, and the data transmission interface of the optical receiving module HTA8530PH is connected to the I/O interface of the FPGA for bidirectional communication, which can ensure high-speed optical signal transmission and improve system compatibility.

In one example, the system further includes a trigger circuit including a buffer and a signal input device connected in sequence, the buffer being connected to the data processing unit. Specifically, the buffer is a bus buffer, and a signal input device can implement a signal input device or device, such as a button, a control device/device, etc. In this example, a button is preferred, and the FPGA obtains the information by detecting the level change of the button pressed. To the trigger signal, in order to control the start time of data acquisition, to meet different data acquisition requirements.

In an example, the clock unit includes a temperature compensated crystal oscillator and a PLL frequency synthesizer connected in sequence, and the output end of the PLL frequency synthesizer is connected to the analog-to-digital signal acquisition unit and the signal transmission unit. In this example, a 100MHz temperature-compensated crystal oscillator is used to provide the local oscillator signal for the PLL frequency synthesizer. Combined with the reference frequency (EXT_REF_CLK), the PLL frequency synthesizer outputs the clock signals SYS_CLK, DA_CLK, and AD_CLK for the FPGA chip, DAC chip, and ADC chip, respectively. working clock.

In an example, the system further includes an eMMC data storage unit, the data transmission end of which is connected to the I/O end of the FPGA, and large-capacity data storage is realized through the eMMC data storage unit.

In an example, the system further includes a reset button and a reset circuit connected in sequence, and the reset circuit is connected with the FPGA. Among them, the reset circuit can use the reset chip TPS3705, the MR pin is connected with the button, and the PF0 pin is connected with the FPGA, so as to realize the reset of the system function through the button.

In an example, the system further includes a power supply unit, and the power supply unit includes a power supply circuit for providing operating voltages for the data processing unit, the analog-to-digital signal acquisition unit, the signal transmission unit, the optical transceiver unit, and the clock unit. Among them, the power supply unit includes several voltage-stabilizing chips, and the corresponding voltage-stabilizing chips are selected according to the power supply of each chip in the system, so as to output different working voltages to supply power to different devices.

The above examples are combined to obtain a preferred example of the present utility model as shown in Figure 2. At this time, the system includes a data processing unit, an analog-to-digital signal acquisition unit, a signal emission unit, an optical transceiver unit, a clock unit, a trigger circuit, an eMMC data storage unit and an eMMC data storage unit. The power supply unit, at this time, the FPGA in the data processing unit is also connected with JTAG, expansion interface and FLASH.

In an example, the system further includes a monitoring unit, the monitoring unit includes a voltage sensor and a second temperature sensor, and both the voltage sensor and the second temperature sensor are arranged close to the power supply circuit. In this example, the existing Hall sensor is used to detect whether the working voltage output by different voltage regulator chips is abnormal; the second temperature sensor is the same as the first temperature sensor, and the second temperature sensor is used to collect the operating temperature and voltage of the voltage regulator chip. The output terminals of the sensor and the second temperature sensor are both connected to the FPGA, and of course they can also be connected to the microcontroller to transmit the collected voltage signal and temperature signal to the FPGA. The FPGA determines whether the voltage signal and temperature exceed the threshold. If it exceeds, the LED indicator will be controlled. The light flashes (the flashing frequency is different from the LED flashing frequency when the FPGA working temperature is abnormal) to alarm.

The above specific embodiment is a detailed description of the present invention, and it cannot be considered that the specific embodiment of the present invention is limited to these descriptions. Below, some simple deductions and substitutions can also be made, all of which should be regarded as belonging to the protection scope of the present invention.

Claims (10)

1. Radio frequency signal receiving and dispatching system based on FPGA, its characterized in that: the optical transceiver comprises a data processing unit, an analog-digital signal acquisition unit, a signal transmitting unit and an optical transceiver unit, wherein the analog-digital signal acquisition unit, the signal transmitting unit and the optical transceiver unit are connected with the data processing unit;

the system also comprises a clock unit, wherein the output end of the clock unit is connected with the data processing unit, the analog-digital signal acquisition unit and the signal transmitting unit.

2. The FPGA-based radio frequency signal transceiving system of claim 1, wherein: the data processing unit comprises an FPGA and a single chip microcomputer which are sequentially connected, the FPGA is connected with a first temperature sensor, and the first temperature sensor is arranged close to the FPGA.

3. The FPGA-based radio frequency signal transceiving system of claim 1, wherein: the analog-digital signal acquisition unit comprises a plurality of signal receiving channels, each signal receiving channel comprises a radio frequency interface, a balun matching circuit and an ADC (analog-to-digital converter) chip which are sequentially connected, and the output end of each ADC chip is connected with the data processing unit through an SPI (serial peripheral interface) bus.

4. The FPGA-based radio frequency signal transceiving system of claim 1, wherein: the signal transmitting unit comprises a plurality of signal transmitting channels, the signal transmitting channels comprise DAC chips, a driving circuit and a radio frequency interface which are connected in sequence, and the DAC chips are connected with the output end of the data processing unit through SPI buses.

5. The FPGA-based radio frequency signal transceiving system of claim 1, wherein: the light receiving and transmitting unit is a multi-path parallel light receiving module.

6. The FPGA-based radio frequency signal transceiving system of claim 1, wherein: the system also comprises a trigger circuit, wherein the trigger circuit comprises a buffer and a signal input device which are sequentially connected, and the buffer is connected with the data processing unit.

7. The FPGA-based radio frequency signal transceiving system of claim 1, wherein: the clock unit comprises a temperature compensation crystal oscillator and a PLL frequency synthesizer which are sequentially connected, and the output end of the PLL frequency synthesizer is connected with the analog-digital signal acquisition unit and the signal transmitting unit.

8. The FPGA-based radio frequency signal transceiving system of claim 1, wherein: the system also includes an eMMC data storage unit connected with the data processing unit.

9. The FPGA-based radio frequency signal transceiving system of claim 1, wherein: the system also comprises a power supply unit, wherein the power supply unit comprises a power supply circuit which is used for providing working voltage for the data processing unit, the analog-digital signal acquisition unit, the signal transmitting unit, the light receiving and transmitting unit and the clock unit.

10. The FPGA-based radio frequency signal transceiving system of claim 9, wherein: the system also comprises a monitoring unit, wherein the monitoring unit comprises a voltage sensor and a second temperature sensor which are connected with the input end of the data processing unit, and the voltage sensor and the second temperature sensor are both arranged close to the power circuit.

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