CN216362303U

CN216362303U - Radio frequency signal receiving and transmitting system based on FPGA

Info

Publication number: CN216362303U
Application number: CN202220631641.7U
Authority: CN
Inventors: 王波; 张洪妹; 赵倩
Original assignee: Chengdu Jinmai Micro Technology Co ltd
Current assignee: Chengdu Jinmai Micro Technology Co ltd
Priority date: 2022-03-23
Filing date: 2022-03-23
Publication date: 2022-04-22
Anticipated expiration: 2032-03-23

Abstract

The utility model discloses a radio frequency signal receiving and transmitting system based on FPGA (field programmable gate array), which belongs to the technical field of wireless communication and comprises a data processing unit, an analog-digital signal acquisition unit, a signal transmitting unit and an optical receiving and transmitting unit, wherein the analog-digital signal acquisition unit, the signal transmitting unit and the optical receiving and transmitting unit are connected with the data processing unit; the system also comprises a clock unit, wherein the output end of the clock unit is connected with the data processing unit, the analog-digital signal acquisition unit and the signal transmitting unit. The utility model improves the signal direct-collecting rate by arranging a plurality of signal acquisition channels and the optical transceiver module, and can meet the high-speed and real-time data acquisition and transmission scenes; meanwhile, the analog-digital signal acquisition unit, the signal transmitting unit and the data processing unit are connected with the same clock signal, so that the synchronism of multi-channel data acquisition is ensured.

Description

Radio frequency signal receiving and transmitting system based on FPGA

Technical Field

The utility model relates to the technical field of wireless communication, in particular to a radio frequency signal receiving and transmitting system based on an FPGA.

Background

The wireless communication comprises two parts of signal acquisition and signal transmission, wherein the signal acquisition is that optical signals and electric signals are received by a signal receiving device (an optical receiving module and an antenna), then the optical signals and the electric signals are sent to a controller for data processing or a storage and recording process through the steps of conditioning, sampling, quantizing, encoding, transmitting and the like, and the signal transmission is realized through the modes of modulation and the like. In practical engineering application, the transceiving system is required to have the characteristics of real-time processing, high speed, multiple channels, stable system and the like so as to meet the requirements of application scenes such as radio monitoring, communication radar testing and the like. High speed, real-time data acquisition depends on the data acquisition rate on the one hand and on the performance of the controller of the data processing operation on the other hand. In addition, in the field of conventional data acquisition, high-speed data acquisition can be achieved by adding data acquisition channels, however, for multi-channel data acquisition, the synchronization between channels is often a key part in a data acquisition system, and how to achieve the synchronization of signal acquisition between multiple channels is also one of the technical problems that needs to be solved at present.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the problems of low signal acquisition rate and poor synchronism in a signal receiving and transmitting system in the prior art, and provides a radio frequency signal receiving and transmitting system based on an FPGA.

The purpose of the utility model is realized by the following technical scheme: the radio frequency signal receiving and transmitting system based on the FPGA comprises a data processing unit, an analog-digital signal acquisition unit, a signal transmitting unit and an optical receiving and transmitting unit, wherein the analog-digital signal acquisition unit, the signal transmitting unit and the optical receiving and transmitting unit are connected with the data processing unit; the system also comprises a clock unit, wherein the output end of the clock unit is connected with the data processing unit, the analog-digital signal acquisition unit and the signal transmitting unit.

In one example, the data processing unit comprises an FPGA and a single chip microcomputer which are sequentially connected, the FPGA is connected with a first temperature sensor, and the first temperature sensor is arranged close to the FPGA.

In one example, the analog-digital signal acquisition unit includes a plurality of signal receiving channels, each signal receiving channel includes a radio frequency interface, a balun matching circuit and an ADC chip, which are connected in sequence, and an output end of the ADC chip is connected with the data processing unit through an SPI bus.

In one example, the signal transmitting unit comprises a plurality of signal transmitting channels, each signal transmitting channel comprises a DAC chip, a driving circuit and a radio frequency interface which are connected in sequence, and the DAC chip is connected with the output end of the data processing unit through an SPI bus.

In one example, the optical transceiver unit is a multi-path parallel optical receiving module.

In one example, the system further comprises a trigger circuit comprising a buffer and a signal input device connected in series, the buffer being connected to the data processing unit.

In one example, the clock unit comprises a temperature compensation crystal oscillator and a PLL frequency synthesizer which are connected in sequence, and the output end of the PLL frequency synthesizer is connected with the analog-digital signal acquisition unit and the signal transmitting unit.

In an example, the system further includes an eMMC data storage unit coupled to the data processing unit.

In an example, the system further comprises a power supply unit, wherein the power supply unit comprises a power supply circuit, and the power supply circuit is used for providing working voltages for the data processing unit, the analog-digital signal acquisition unit, the signal transmitting unit, the optical transceiving unit and the clock unit.

In one example, the system further comprises a monitoring unit, the monitoring unit comprises a voltage sensor and a second temperature sensor which are connected with the input end of the data processing unit, and the voltage sensor and the second temperature sensor are both arranged close to the power circuit.

It should be further noted that the technical features corresponding to the above examples can be combined with each other or replaced to form a new technical solution.

Compared with the prior art, the utility model has the beneficial effects that:

1. in one example, the signal direct-collecting rate is improved by arranging a plurality of signal acquisition channels and an optical transceiver module, so that a high-speed and real-time data acquisition and transmission scene can be met; meanwhile, the analog-digital signal acquisition unit, the signal transmitting unit and the data processing unit are connected with the same clock signal, so that the synchronism of multi-channel data acquisition is ensured.

2. In one example, the real-time working temperature of the FPGA is monitored through the first sensor, and the working stability of the FPGA is guaranteed.

3. In one example, a single-port signal is converted through a balun matching circuit, so that a differential signal with high gain, electromagnetic interference resistance, power noise resistance and ground noise resistance is obtained; data transmission is carried out based on the SPI bus, and high-speed transmission of signals is guaranteed.

4. In one example, the signal transmission rate can be ensured through a plurality of signal transmission channels, and the real-time performance of signal transmission is ensured.

5. In one example, high-speed optical signal transmission is achieved by a multi-path parallel optical receiving module.

6. In one example, the start time of data acquisition is controlled by external triggering through a triggering circuit so as to meet different data acquisition requirements.

7. In one example, the temperature compensated crystal oscillator ensures that the synthesized clock frequency is more stable and accurate.

8. In one example, large capacity data storage is achieved by an eMMC data storage unit.

9. In one example, whether the voltage output of the power supply unit is abnormal is detected through a voltage sensor, and the working stability and reliability of the voltage unit are ensured by detecting the working temperature of the power supply based on a second temperature sensor.

Drawings

The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the utility model and together with the description serve to explain the utility model without limiting the utility model.

FIG. 1 is a block diagram of a system in one example of the utility model;

fig. 2 is a system block diagram of a preferred example of the present invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that directions or positional relationships indicated by "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like are directions or positional relationships described based on the drawings, and are only for convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

In an example, the radio frequency signal transceiving system based on the FPGA, as shown in fig. 1, specifically includes a data processing unit, an analog-to-digital signal acquisition unit, a signal transmitting unit, an optical transceiving unit, and a clock unit. Specifically, the data processing unit serves as a control core of the entire system, and includes an FPGA for data processing. The output end of the analog-digital signal acquisition unit is connected with the data processing unit and comprises a plurality of signal acquisition channels for acquiring radio frequency signals. The signal transmitting unit is connected with the output end of the data processing unit and used for transmitting radio frequency signals. The optical transceiver unit is in bidirectional connection with the data processing unit and comprises a plurality of optical transceiver modules, so that optical signals can be transmitted and received, the system transceiving compatibility is improved, the signal acquisition rate can be remarkably improved by combining the plurality of signal acquisition channels, and high-speed and real-time data acquisition and transmission scenes are met. The output end of the clock unit is connected with the data processing unit, the analog-digital signal acquisition unit and the signal transmitting unit, even if the analog-digital signal acquisition unit, the signal transmitting unit and the data processing unit are connected with the same clock signal, the clock frequency of each unit of the system is synchronized, and the signal receiving and transmitting synchronism is ensured.

In one example, the data processing unit is sequentially connected with the communication unit and the upper computer to realize communication with the upper computer and realize data sharing. The communication unit is any one of a WIFI communication module, a mobile communication module, a narrow-band Internet of things communication module and a serial communication module, and a data communication end of the communication unit is connected with a communication port of an upper computer and a communication port of an FPGA in a data processing unit so as to establish bidirectional communication connection.

In one example, the data processing unit comprises an FPGA and a single chip microcomputer which are sequentially connected, the FPGA is connected with a first temperature sensor and an LED indicator light, and the first temperature sensor is arranged close to the FPGA. In this example, XC7K325T-2FFG900I, which is an FPGA chip of XILINX, is specifically adopted to ensure the data processing capability. The singlechip is STM32 series singlechip, and communicates through the SPI bus between singlechip and the FPGA. The data transmission pin of the first temperature sensor PT100 is connected with the I/O end of the FPGA so as to transmit the collected working temperature information of the FPGA to the FPGA, when the working temperature exceeds a threshold value, the FPGA controls the LED indicator light to flash and alarm, and the working stability of the FPGA chip is guaranteed. Of course, as an option, the output end of the first temperature sensor may be connected to the single chip, and at this time, the output end of the single chip is correspondingly connected to the LED indicator.

It should be further noted that the circuit modules, i.e., the chips such as the sensor, the controller, the analog-to-digital converter, and the like, used in the present application are all existing chips, and those skilled in the art can query the corresponding chip manual for knowing the working principle and the connection mode of the specific chips, which belongs to the common general knowledge of those skilled in the art, and the present invention does not further describe the pin connection relationship between the chips.

In one example, the analog-digital signal acquisition unit includes a plurality of signal receiving channels, each signal receiving channel includes a radio frequency interface, a balun matching circuit and an ADC chip, which are connected in sequence, and an output end of the ADC chip is connected with the data processing unit through an SPI bus. The system comprises a radio frequency interface (SAM) interface, a balun matching circuit, an ADC chip (ADC 083000), a digital signal and an FPGA, wherein the SAM interface is used for receiving a radio frequency signal through the SMA interface, the balun matching circuit is used for converting the single-port radio frequency signal to obtain a differential signal which has high gain, electromagnetic interference resistance, power noise resistance and ground noise resistance, the differential signal is transmitted to the ADC chip to realize analog-to-digital conversion processing of the signal to obtain the digital signal and is transmitted to the FPGA, and the FPGA performs data processing on the digital signal to extract effective information.

In one example, the signal transmitting unit comprises a plurality of signal transmitting channels, each signal transmitting channel comprises a DAC chip, a driving circuit and a radio frequency interface which are connected in sequence, and the DAC chip is connected with the output end of the data processing unit through an SPI bus. The DAC chip, i.e., DAC9739, converts the digital signals transmitted by the FPGA to obtain analog signals, which are driven by a driving circuit, i.e., a driver, and finally radiated to an external system through the SMA interface. In this example, the signal transmission rate can be ensured by a plurality of signal transmission channels, and the real-time performance of signal transmission is ensured.

In an example, the optical transceiver unit is a 12-channel parallel optical receiving module HTA8530PH, and a data transmission interface of the optical receiving module HTA8530PH is in bidirectional communication connection with an I/O interface of an FPGA, so that high-speed optical signal transmission can be ensured, and compatibility of the system can be improved.

In one example, the system further comprises a trigger circuit comprising a buffer and a signal input device connected in series, the buffer being connected to the data processing unit. Specifically, the buffer is a bus buffer, and the signal input device may be a device or an apparatus for implementing signal input, such as a key, a control device/apparatus, and the like.

In one example, the clock unit comprises a temperature compensation crystal oscillator and a PLL frequency synthesizer which are connected in sequence, and the output end of the PLL frequency synthesizer is connected with the analog-digital signal acquisition unit and the signal transmitting unit. In this example, a 100MHz temperature compensation crystal oscillator is specifically adopted to provide a local oscillation signal for the PLL frequency synthesizer, and in combination with a reference frequency (EXT _ REF _ CLK), the PLL frequency synthesizer outputs clock signals SYS _ CLK, DA _ CLK, and AD _ CLK to provide operating clocks for the FPGA chip, the DAC chip, and the ADC chip, respectively.

In an example, the system further includes an eMMC data storage unit, a data transmission end of which is connected to an I/O end of the FPGA, and the eMMC data storage unit is used to implement large-capacity data storage.

In one example, the system further comprises a reset key and a reset circuit which are connected in sequence, wherein the reset circuit is connected with the FPGA. The reset circuit can adopt a reset chip TPS3705, the MR pin of the reset chip TPS3705 is connected with the key, and the PF0 pin is connected with the FPGA so as to reset the system function through the key.

In an example, the system further comprises a power supply unit, wherein the power supply unit comprises a power supply circuit, and the power supply circuit is used for providing working voltages for the data processing unit, the analog-digital signal acquisition unit, the signal transmitting unit, the optical transceiving unit and the clock unit. The power supply unit comprises a plurality of voltage stabilizing chips, and the corresponding voltage stabilizing chips are selected according to the power supply of each chip in the system so as to output different working voltages to supply power for different devices.

Fig. 2 shows a preferred embodiment of the present invention, which is obtained by combining the above examples, where the system includes a data processing unit, an analog-to-digital signal acquisition unit, a signal transmission unit, an optical transceiver unit, a clock unit, a trigger circuit, an eMMC data storage unit, and a power supply unit, and at this time, the FPGA in the data processing unit is further connected to a JTAG, an expansion interface, and a FLASH.

In one example, the system further comprises a monitoring unit, wherein the monitoring unit comprises a voltage sensor and a second temperature sensor, and the voltage sensor and the second temperature sensor are both arranged close to the power circuit. In the example, the existing hall sensor is specifically adopted to detect whether the working voltages output by different voltage stabilizing chips are abnormal or not; the second temperature sensor is the same as the first temperature sensor and used for collecting the working temperature of the voltage stabilizing chip, the output ends of the voltage sensor and the second temperature sensor are connected with the FPGA, and can also be connected with the single chip microcomputer of course, so that collected voltage signals and temperature signals are transmitted to the FPGA, the FPGA judges whether the voltage signals and the temperature exceed a threshold value, and if the voltage signals and the temperature exceed the threshold value, the LED indicator lamp is controlled to flicker (the flicker frequency of the LED is different from the flicker frequency of the LED when the working temperature of the FPGA is abnormal) to alarm.

The above detailed description is for the purpose of describing the utility model in detail, and it should not be construed that the detailed description is limited to the description, and it will be apparent to those skilled in the art that various modifications and substitutions can be made without departing from the spirit of the utility model.

Claims

1. Radio frequency signal receiving and dispatching system based on FPGA, its characterized in that: the optical transceiver comprises a data processing unit, an analog-digital signal acquisition unit, a signal transmitting unit and an optical transceiver unit, wherein the analog-digital signal acquisition unit, the signal transmitting unit and the optical transceiver unit are connected with the data processing unit;

the system also comprises a clock unit, wherein the output end of the clock unit is connected with the data processing unit, the analog-digital signal acquisition unit and the signal transmitting unit.

2. The FPGA-based radio frequency signal transceiving system of claim 1, wherein: the data processing unit comprises an FPGA and a single chip microcomputer which are sequentially connected, the FPGA is connected with a first temperature sensor, and the first temperature sensor is arranged close to the FPGA.

3. The FPGA-based radio frequency signal transceiving system of claim 1, wherein: the analog-digital signal acquisition unit comprises a plurality of signal receiving channels, each signal receiving channel comprises a radio frequency interface, a balun matching circuit and an ADC (analog-to-digital converter) chip which are sequentially connected, and the output end of each ADC chip is connected with the data processing unit through an SPI (serial peripheral interface) bus.

4. The FPGA-based radio frequency signal transceiving system of claim 1, wherein: the signal transmitting unit comprises a plurality of signal transmitting channels, the signal transmitting channels comprise DAC chips, a driving circuit and a radio frequency interface which are connected in sequence, and the DAC chips are connected with the output end of the data processing unit through SPI buses.

5. The FPGA-based radio frequency signal transceiving system of claim 1, wherein: the light receiving and transmitting unit is a multi-path parallel light receiving module.

6. The FPGA-based radio frequency signal transceiving system of claim 1, wherein: the system also comprises a trigger circuit, wherein the trigger circuit comprises a buffer and a signal input device which are sequentially connected, and the buffer is connected with the data processing unit.

7. The FPGA-based radio frequency signal transceiving system of claim 1, wherein: the clock unit comprises a temperature compensation crystal oscillator and a PLL frequency synthesizer which are sequentially connected, and the output end of the PLL frequency synthesizer is connected with the analog-digital signal acquisition unit and the signal transmitting unit.

8. The FPGA-based radio frequency signal transceiving system of claim 1, wherein: the system also includes an eMMC data storage unit connected with the data processing unit.

9. The FPGA-based radio frequency signal transceiving system of claim 1, wherein: the system also comprises a power supply unit, wherein the power supply unit comprises a power supply circuit which is used for providing working voltage for the data processing unit, the analog-digital signal acquisition unit, the signal transmitting unit, the light receiving and transmitting unit and the clock unit.

10. The FPGA-based radio frequency signal transceiving system of claim 9, wherein: the system also comprises a monitoring unit, wherein the monitoring unit comprises a voltage sensor and a second temperature sensor which are connected with the input end of the data processing unit, and the voltage sensor and the second temperature sensor are both arranged close to the power circuit.