CN216312957U

CN216312957U - Switching frequency control system

Info

Publication number: CN216312957U
Application number: CN202123012262.4U
Authority: CN
Inventors: 薛尚嵘; 冯翰雪; 李冬超
Original assignee: Yishi Semiconductor Shanghai Co ltd
Current assignee: Yishi Semiconductor Shanghai Co ltd
Priority date: 2021-12-02
Filing date: 2021-12-02
Publication date: 2022-04-15
Anticipated expiration: 2031-12-02

Abstract

The utility model discloses a switching frequency control system, which comprises a first phase-locked loop and a second oscillator, wherein the first phase-locked loop comprises a phase discriminator, a loop filter and a first oscillator; the second oscillator and the first oscillator form a second phase-locked loop through switching. The second oscillator can output a clock signal synchronized to the external clock signal, and the second oscillator can provide a control voltage corresponding to the frequency of the external clock signal. The first oscillator is in a PLL mode and is switched from a first working state to a second working state, and the clock signal output by the first oscillator after the first working state is exited can skip the abnormal state and be synchronized to the external clock signal by controlling the voltage. The switching frequency control system effectively realizes the control of the dual-mode switching frequency in the switching power supply, and ensures the stability of the output state of each oscillator in different working modes and working states and the stability of the output state of each oscillator when different modes are switched mutually.

Description

Switching frequency control system

Technical Field

The present invention relates to the field of integrated circuit technology, and more particularly, to a switching frequency control system.

Background

Switching power supplies, which are high-frequency power conversion devices, are widely used in the field of integrated circuits, and convert a level voltage into a voltage or a current required by a user terminal through different types of architectures. The switching power supply has high working frequency and needs to be switched among different frequencies, and when the output state of a switching frequency control system in the conventional switching power supply is switched, the frequency of an output signal is not stable enough, so that the working of the switching power supply is easily influenced.

The information disclosed in this background section is only for enhancement of understanding of the general background of the utility model and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a switching frequency control system, wherein the frequency of an output signal can be kept stable when the output state is switched.

To achieve the above object, an embodiment of the present invention provides a switching frequency control system, including: a first phase-locked loop and a second phase-locked loop. The first phase-locked loop comprises a phase discriminator, a loop filter and a first oscillator; the second oscillator and the first oscillator are capable of forming a second phase-locked loop by switching.

The first oscillator outputs a CLOCK signal CLOCK of a corresponding frequency in the PLL mode and in the first operating state, while the second oscillator outputs a CLOCK signal CLK _ OSC2 that can be synchronized to the external CLOCK signal CLK _ SYNC, and the second oscillator provides a control voltage VCONT corresponding to the frequency of the external CLOCK signal CLK _ SYNC.

The first oscillator is in the PLL mode and is switched from the first operating state to the second operating state, and the control voltage VCONT enables the CLOCK signal CLOCK output by the first oscillator after exiting the first operating state to be synchronized to the external CLOCK signal CLK _ SYNC by skipping the abnormal state.

In one or more embodiments of the present invention, the first oscillator is capable of outputting CLOCK signals CLOCK of different frequencies in the RT mode and in different operating states; the first oscillator is switched from the RT mode to the PLL mode in the second operating state and is capable of outputting a CLOCK signal CLOCK synchronized to the external CLOCK signal CLK _ SYNC.

In one or more embodiments of the present invention, the switching frequency control system further includes a first selector and a second selector, an I0 input terminal and an output terminal of the first selector are connected to the first oscillator, an I1 input terminal of the first selector is connected to the second oscillator, an I0 input terminal of the second selector is connected to an output terminal of the first oscillator, an I1 input terminal of the second selector is connected to an output terminal of the second oscillator, and an output terminal of the second selector is connected to an input terminal of the phase detector, and switching between the first oscillator and the second oscillator can be achieved through the first selector and the second selector.

In one or more embodiments of the present invention, the first oscillator includes a mode conversion circuit, a first current mirror circuit, a lowest frequency circuit, a frequency maintenance circuit, a first ramp voltage generation circuit, a first comparator, a first logic circuit, and a BUFFER1, the mode conversion circuit, the first ramp voltage generation circuit, and the first comparator are all connected to the first current mirror circuit, and the first current mirror circuit, the lowest frequency circuit, and the frequency maintenance circuit are all connected to the first selector;

the mode switching circuit is used for switching off or switching to an RT mode and outputting corresponding mirror current through the first current mirror circuit; the lowest frequency circuit is used for enabling the first oscillator to output the lowest frequency; the frequency maintaining circuit is used for maintaining the frequency corresponding to the control voltage VCONT in the RT mode; the first inclineThe slope voltage generating circuit is used for outputting a corresponding slope voltage V according to the mirror current output by the first current mirror circuit_RAMP1(ii) a The first comparator is used for converting a ramp voltage V_RAMP1And a reference voltage V_{REF_OSC}The comparison is performed and then the CLOCK signal CLOCK is outputted through the first logic circuit and the BUFFER 1.

In one or more embodiments of the utility model, the mode conversion circuit includes an operational amplifier, a switch S3, and a resistor R_SETAnd an NMOS transistor N5;

wherein the positive input end of the operational amplifier is connected with a reference voltage V_REFThe negative electrode input end of the operational amplifier is connected with the resistor R through the switch S3_SETOne end of said resistor R_SETThe other end of the operational amplifier is grounded, the negative electrode input end of the operational amplifier is simultaneously connected with the source electrode of the NMOS tube N5, the grid electrode of the NMOS tube N5 is connected with the output end of the operational amplifier, the drain electrode of the NMOS tube N5 is connected with the first current mirror circuit, and the switch S3 is in a closed state in the RT mode.

In one or more embodiments of the present invention, the first current mirror circuit includes a PMOS transistor P5 and a PMOS transistor P8, a source of the PMOS transistor P5 is connected to a power VDD, a drain and a gate of the PMOS transistor P5 are shorted and connected to an I0 input terminal of the first selector, a gate of the PMOS transistor P8 is connected to an output terminal of the first selector, a source of the PMOS transistor P8 is connected to the power VDD, and a drain of the PMOS transistor P8 is connected to a positive input terminal of the first comparator.

In one or more embodiments of the utility model, the lowest frequency circuit includes a PMOS transistor P9, a resistor R3, a capacitor C3, a PMOS transistor P6, and a bias current source IBIAS2_ FMIN;

the drain of the PMOS transistor P9 is grounded through the resistor R3, the gate of the PMOS transistor P9 is grounded through the bias current source IBIAS2_ FMIN and is connected to the power supply VDD through the capacitor C3, the source of the PMOS transistor P9 is connected to the I0 input terminal of the first selector, the gate of the PMOS transistor P9 is connected to the drain of the PMOS transistor P6, the gate of the PMOS transistor P6 is connected to the I0 input terminal of the first selector, and the source of the PMOS transistor P6 is connected to the power supply VDD.

In one or more embodiments of the present invention, the frequency maintaining circuit includes a PMOS transistor P7, a switch S4, an NMOS transistor N6, and a resistor R4;

the source electrode of the PMOS tube P7 is connected with a power supply VDD, the grid electrode of the PMOS tube P7 is connected with the I0 input end of the first selector, the drain electrode of the PMOS tube P7 is connected with one end of the switch S4 and the output end of the loop filter, the drain electrode and the grid electrode of the NMOS tube N6 are in short circuit and are connected with the other end of the switch S4, the source electrode of the NMOS tube N6 is grounded through the resistor R4, and the switch S4 is in a closed state in the RT mode.

In one or more embodiments of the utility model, the first ramp voltage generation circuit includes an NMOS transistor N7 and a capacitor C_OSC1Said capacitor C_OSC1One end of the first comparator is connected with the drain electrode of the NMOS tube N7 and the positive electrode input end of the first comparator, the other end of the first comparator is connected with the source electrode of the NMOS tube N7 and is grounded, and the grid electrode of the NMOS tube N7 is connected with the output end of the first logic circuit.

In one or more embodiments of the utility model, the second oscillator includes an NMOS transistor N3, a resistor R2, a PMOS transistor P3, a PMOS transistor P4, an NMOS transistor N4, and a capacitor C_OSC2A second comparator, a second logic circuit and a BUFFER 2;

wherein, the gate of NMOS pipe N3 is connected the output of loop filter, the source of NMOS pipe N3 is passed through resistance R2 ground connection, the source of NMOS pipe N3 is connected the I1 input of first selector, the drain and the gate short circuit of PMOS pipe P3 and connect the drain of NMOS pipe N3 and the gate of PMOS pipe P4, the source of PMOS pipe P3 is connected power VDD, the source of PMOS pipe P4 is connected power VDD, the drain of PMOS pipe P4 is connected the positive input of second comparator, electric capacity C is connected_OSC2One end of the second comparator is connected with the drain electrode of the NMOS tube N4 and the positive input end of the second comparator, and the capacitor C_OSC2The other end of the NMOS transistor N4 is connected with the source electrode of the NMOS transistor N4 and is grounded, the grid electrode of the NMOS transistor N4 is connected with the output end of the second logic circuit,the negative pole input end of the second comparator is connected with a reference voltage V_{REF_OSC}The output terminal of the second comparator is connected to the input terminal of the BUFFER2 through the second logic circuit, and the output terminal of the BUFFER2 is connected to the I1 input terminal of the second selector.

Compared with the prior art, the switching frequency control system of the embodiment of the utility model provides the control voltage VCONT corresponding to the frequency of the external CLOCK signal CLK _ SYNC while outputting the CLOCK signal CLK _ OSC2 capable of synchronizing to the external CLOCK signal CLK _ SYNC through the second oscillator, so that the CLOCK signal CLOCK output by the first oscillator can be quickly synchronized to the external CLOCK signal CLK _ SYNC in the PLL mode and when the first operating state is switched to the second operating state. The switching frequency control system effectively realizes the control of the dual-mode switching frequency in the switching power supply, and ensures the stability of the output state of each oscillator in different working modes and working states and the stability of the output state of each oscillator when different modes are switched mutually.

Drawings

FIG. 1 is a circuit schematic of a switching frequency control system according to an embodiment of the present invention;

fig. 2 is a circuit schematic of a phase detector according to an embodiment of the present invention;

FIG. 3 is a circuit schematic of a loop filter according to an embodiment of the present invention;

FIG. 4 is a circuit schematic of a first oscillator according to an embodiment of the present invention;

FIG. 5 is a circuit schematic of a second oscillator according to an embodiment of the present invention;

FIG. 6 is a system control mode flow diagram of a switching frequency control system according to an embodiment of the present invention;

FIG. 7 is a timing diagram of a circuit when a switching frequency control system is powered on according to an embodiment of the present invention;

fig. 8 is a circuit timing diagram after a switching frequency control system according to an embodiment of the present invention is started.

Detailed Description

The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.

Example 1

As shown in fig. 1, a switching frequency control system includes: a first phase-locked loop and a second phase-locked loop. The first phase locked loop includes a phase detector 100, a loop filter 200, and a first oscillator 300; the second oscillator 400 and the first oscillator 300 can form a second phase-locked loop by switching, that is, the phase detector 100 and the loop filter 200 are shared by the first phase-locked loop and the second phase-locked loop.

The switching frequency control system further comprises a first selector having an input terminal I0 and an output terminal connected to the first oscillator 300, and an input terminal I1 connected to the second oscillator 400. The I0 input of the first selector receives the PG signal and the output of the first selector outputs the PGATE signal. The I0 input of the second selector is coupled to the output of the first oscillator 300 for receiving the CLOCK signal CLOCK, and the I1 input of the second selector is coupled to the output of the second oscillator 400 for receiving the CLOCK signal CLK _ OSC 2. The output terminal of the second selector is connected to the input terminal of the phase detector 100 to output the signal CLK _ IN to the phase detector 100, and switching between the first oscillator 300 and the second oscillator 400 can be achieved by the first selector and the second selector.

The first oscillator 300 outputs a CLOCK signal CLOCK with a corresponding frequency in the PLL mode and in the first operation state, the second oscillator 400 outputs a CLOCK signal CLK _ OSC2 capable of being synchronized to the external CLOCK signal CLK _ SYNC, and the second oscillator 400 provides a control voltage VCONT corresponding to the frequency of the external CLOCK signal CLK _ SYNC; the first oscillator 300 is in the PLL mode and is switched from the first operating state to the second operating state, so that the CLOCK signal CLOCK output by the first oscillator 300 after exiting the first operating state can be synchronized to the external CLOCK signal CLK _ SYNC by skipping the abnormal state by the control voltage VCONT.

The first oscillator 300 can output CLOCK signals CLOCK with different frequencies in the RT mode and in different working states; the first oscillator 300 is switched from the RT mode to the PLL mode in the second operation state, and can output the CLOCK signal CLOCK synchronized to the external CLOCK signal CLK _ SYNC.

In the present embodiment, the RT mode and the PLL mode are two operation modes. The first working state has two signal output modes, including the lowest frequency output mode corresponding to the system just powered on for counting, at this time, the first oscillator 300 outputs the CLOCK signal CLOCK of the lowest frequency; and after the system is started, the system down-conversion output mode corresponding to the system down-conversion, at this time, the first oscillator 300 outputs the CLOCK signal CLOCK of the system down-conversion frequency. The second working state is a normal output mode after the system is started, and in the RT mode, the first oscillator 300 outputs the resistor R_SETCLOCK signal CLOCK of predetermined frequency, resistor R_SETIs an external resistor. In the PLL mode, the first oscillator 300 outputs a CLOCK signal CLOCK whose frequency can be synchronized to the external CLOCK signal CLK _ SYNC.

Therefore, the first oscillator 300 outputs the CLOCK signal CLOCK of the lowest frequency in the RT mode and the lowest frequency output mode, the first oscillator 300 outputs the CLOCK signal CLOCK of the system down-conversion frequency in the RT mode and the system down-conversion output mode, and the first oscillator 300 outputs the resistor R in the second operation state_SETA CLOCK signal CLOCK of a preset frequency. The first oscillator 300 is switched from the RT mode to the PLL mode in the second operation state, and can output the CLOCK signal CLOCK synchronized to the external CLOCK signal CLK _ SYNC.

The first oscillator 300 outputs the CLOCK signal CLOCK of the lowest frequency or the system down-conversion frequency in the PLL mode and in the lowest frequency output mode or the system down-conversion output mode, and the second oscillator 400 outputs the CLOCK signal CLK _ OSC2 capable of being synchronized to the external CLOCK signal CLK _ SYNC while the second oscillator 400 provides a control voltage VCONT corresponding to the frequency of the external CLOCK signal CLK _ SYNC.

The CLOCK signal CLOCK, which is outputted by the first oscillator 300 after exiting the lowest frequency output mode or the system down-conversion output mode, can be synchronized to the external CLOCK signal CLK _ SYNC by skipping the abnormal state by the control voltage VCONT when the first oscillator 300 is in the PLL mode and transits from the first operating state to the second operating state.

As shown in fig. 1, the switching frequency control system further includes a mode decision circuit and an enable circuit. The MODE decision circuit has an RT/SYNC input terminal, an EN input terminal, a CLK _ SYNC output terminal, an RT _ MODE output terminal and a PLL _ MODE output terminal. The enable circuit has an EN _ CK input, a FORCE _ FMIN input, a LOCK _ OSC1 input, an EN output, an EN1 output, and an EN2 output. The EN output end of the enabling circuit is connected with the EN input end of the mode judging circuit. The enable circuit receives an input signal FORCE _ FMIN through a FORCE _ FMIN input terminal, and the input signal FORCE _ FMIN is used for indicating whether the circuit works in a lowest frequency output mode.

The enable circuit receives an input signal EN _ CK from an EN _ CK input terminal and outputs an enable signal EN from an EN output terminal, an enable signal EN1 from an EN1 output terminal, and an enable signal EN2 from an EN2 output terminal. The enable signal EN is equal to the input signal EN _ CK, the enable signal EN is used to control the operating state of the switching frequency control system, and when the enable signal EN is "1", the switching frequency control system operates normally, and the analysis in the present embodiment assumes that the enable signal EN is "1". The enable signal EN1 and the enable signal EN2 correspond to the operating states of some circuits in the control switching frequency control system, respectively, and when the enable signal EN1 and the enable signal EN2 are "0", the corresponding circuits do not operate, and when the enable signal EN1 and the enable signal EN2 are "1", the corresponding circuits operate.

The MODE decision circuit determines the operation MODE of each oscillator by the state of the RT/SYNC input terminal, and outputs the external clock signal CLK _ SYNC through the CLK _ SYNC output terminal, the control signal RT _ MODE for switching the first oscillator 300 to the RT MODE through the RT _ MODE output terminal, and the control signal PLL _ MODE for switching the first oscillator 300 to the PLL MODE through the PLL _ MODE output terminal.

In this embodiment, when only the resistor RSET is connected between the RT/SYNC input terminal and the ground, the MODE decision circuit outputs the control signal RT _ MODE of "1" and the control signal PLL _ MODE of "0", and at this time, the first oscillator 300 operates in the RT MODE; at this time, if the input signal FORCE _ FMIN is "0" and there is no system down-conversion, the frequency of the CLOCK signal CLOCK outputted from the first oscillator 300 is determined by the value of the resistor RSET. When the external clock signal CLK _ SYNC is directly connected to the RT/SYNC terminal, the MODE decision circuit outputs a control signal PLL _ MODE of "1" and a control signal RT _ MODE of "0"; at this time, the first oscillator 300 operates in the PLL mode; also, if the input signal FORCE _ FMIN is "0" and there is no system down-conversion, the CLOCK signal CLOCK output by the first oscillator 300 is synchronized to the external CLOCK signal CLK _ SYNC through the first phase-locked loop; if both are present, the PLL MODE overrides the RT MODE by automatic detection, the MODE decision circuit outputs the control signal PLL _ MODE as "1" and the control signal RT _ MODE as "0", and the first oscillator 300 operates in the PLL MODE.

As shown in fig. 2, the phase detector 100 is a phase comparison module, AND the phase detector 100 includes a D flip-flop D1, a D flip-flop D2, an AND gate AND1, an inverter INV3, a PMOS transistor P1, a PMOS transistor P2, an NMOS transistor N1, an NMOS transistor N2, a switch S1, a switch S2, AND a unity gain amplifier a 1.

Specifically, an input CK terminal of the D flip-flop D1 is connected to a CLK _ SYNC output terminal of the mode decision circuit to receive the external clock signal CLK _ SYNC, and an input D terminal of the D flip-flop D1 is connected to the power supply VDD. An input CK terminal of the D flip-flop D2 is connected to an output terminal of the second selector to receive the signal CLK _ IN, and an input D terminal of the D flip-flop D2 is connected to the power supply VDD. The output Q terminal of the D flip-flop D1 is connected to the a1 input terminal of the AND gate AND1, AND the output Q terminal of the D flip-flop D2 is connected to the a2 input terminal of the AND gate AND 1. An output end of the AND gate AND1 is connected to an input end of the inverter INV3, AND an output end of the inverter INV3 is connected to R reset ends of the D flip-flop D1 AND the D flip-flop D2. The output QN terminal of the D-flip-flop D1 is connected to the gate of the PMOS transistor P2, and the output Q terminal of the D-flip-flop D2 is connected to the gate of the NMOS transistor N1. The source of the PMOS transistor P2 is connected with the drain of the PMOS transistor P1, the source of the PMOS transistor P1 is connected with the power supply VDD, and the gate of the PMOS transistor P1 is connected with the bias voltage VB 1. The source of the NMOS transistor N1 is connected to the drain of the NMOS transistor N2, the source of the NMOS transistor N2 is grounded, and the gate of the NMOS transistor N2 is connected to a bias voltage VB 2. The source of the PMOS transistor P2 is connected to one end of the switch S1, the drain of the NMOS transistor N2 is connected to one end of the switch S2, and the other end of the switch S1 is connected to the other end of the switch S2 and to the output of the unity gain amplifier A1. The drain of the NMOS transistor N1 is connected to the drain of the PMOS transistor P2 and to the input of the unity gain amplifier a1 and the loop filter 200, thereby outputting an error voltage corresponding to the phase difference between the CLOCK signal CLOCK or the CLOCK signal CLK _ OSC2 and the external CLOCK signal CLK _ SYNC, respectively, to the loop filter 200.

The phase detector 100 can compare the CLOCK signal CLOCK output from the first oscillator 300 with the external CLOCK signal CLK _ SYNC in the PLL mode to generate an error voltage corresponding to a phase difference between the CLOCK signal CLOCK and the external CLOCK signal CLK _ SYNC. Meanwhile, the phase detector 100 can compare the clock signal CLK _ OSC2 output from the second oscillator 400 with the external clock signal CLK _ SYNC to generate an error voltage corresponding to the phase difference between the clock signal CLK _ OSC2 and the external clock signal CLK _ SYNC.

As shown in fig. 3, the loop filter 200 is used to remove a high frequency signal and a noise signal in the error voltage and output a control voltage VCONT _ PRE that controls the first oscillator 300 or the second oscillator 400, thereby increasing the stability of the system by removing the high frequency signal and the noise signal in the error voltage to satisfy the performance required for each phase locked loop in the PLL mode.

Specifically, the loop filter 200 includes a resistor R1, a capacitor C1, and a capacitor C2. Specifically, one end of the capacitor C1 and one end of the capacitor C2 are both grounded, the other end of the capacitor C1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the other end of the capacitor C2 and is connected to the drain of the PMOS transistor P2 and the drain of the NMOS transistor N1 to receive the error voltage, and the second oscillator 400 is also connected to output the control voltage VCONT _ PRE.

As shown in fig. 4, the first oscillator 300 can operate in an RT mode or a PLL mode, and the RT mode and the PLL mode can be switched to each other, and a switching frequency of the switching power supply can be generated in the RT mode or the PLL mode.

Specifically, the first oscillator 300 includes a mode conversion circuit 310, a first current mirror circuit 320, a lowest frequency circuit 330, a frequency maintenance circuit 340, a first ramp voltage generation circuit 350, a first comparator, a first logic circuit, and a BUFFER1, wherein the mode conversion circuit 310, the first ramp voltage generation circuit 350, and the first comparator are all connected to the first current mirror circuit 320, and the first current mirror circuit 320, the lowest frequency circuit 330, and the frequency maintenance circuit 340 are all connected to the first selector.

As shown in fig. 4, the mode conversion circuit 310 is used to switch off or switch to the RT mode and output a corresponding mirror current through the first current mirror circuit 320.

Specifically, the mode converting circuit 310 includes an operational amplifier, a switch S3, and a resistor R_SETAnd an NMOS transistor N5. The positive input end of the operational amplifier is connected with a reference voltage V_REF. The negative input end of the operational amplifier passes through the switch S3 and the resistor R_SETIs connected to a resistor R_SETAnd the other end of the same is grounded. The drain electrode of the NMOS tube N5 is connected with the current mirror circuit, the grid electrode of the NMOS tube N5 is connected with the output end of the operational amplifier, and the source electrode of the NMOS tube N5 is connected with the negative electrode input end of the operational amplifier. The operational amplifier is controlled by an enable signal EN1, and works normally when the enable signal EN1 is '1', and does not work when the enable signal EN1 is '0'.

In the RT mode, the switch S3 is in a closed state. When the switch S3 is controlled by the control signal RT _ MODE, the control signal RT _ MODE is "1" and the control signal PLL _ MODE is "0", the switch S3 is closed, so that the MODE switching circuit 310 enters the RT MODE. When the control signal RT _ MODE is "0" and the control signal PLL _ MODE is "1", the switch S3 is turned off.

As shown in fig. 4, the first current mirror circuit 320 includes a PMOS transistor P5 and a PMOS transistor P8. The source of the PMOS transistor P5 is connected to the power supply VDD, and the drain and gate of the PMOS transistor P5 are shorted and connected to the drain of the NMOS transistor N5 and the I0 input terminal of the first selector. The drain of the PMOS transistor P8 is connected to the first ramp voltage generating circuit 350 and the positive input terminal of the first comparator, the gate of the PMOS transistor P8 is connected to the output terminal of the first selector, and the source of the PMOS transistor P8 is connected to the power supply VDD.

As shown in fig. 4, the lowest frequency circuit 330 includes a PMOS transistor P9, a resistor R3, a capacitor C3, a PMOS transistor P6, and a bias current source IBIAS2_ FMIN.

The drain of the PMOS transistor P9 is grounded through a resistor R3, the gate of the PMOS transistor P9 is grounded through a bias current source IBIAS2_ FMIN and connected to the power supply VDD through a capacitor C3, the source of the PMOS transistor P9 is connected to the I0 input terminal of the first selector and the drain and gate short-circuit terminal of the PMOS transistor P5, and the gate of the PMOS transistor P9 is connected to the drain of the PMOS transistor P6. The gate of the PMOS transistor P6 is connected to the I0 input terminal of the first selector, and the source of the PMOS transistor P6 is connected to the power supply VDD.

As shown in fig. 4, the frequency maintaining circuit 340 includes a PMOS transistor P7, a switch S4, an NMOS transistor N6, and a resistor R4.

The source electrode of the PMOS tube P7 is connected with a power supply VDD, the grid electrode of the PMOS tube P7 is connected with the I0 input end of the first selector, the drain electrode of the PMOS tube P7 is connected with one end of the switch S4 and the connected end of the resistor R1 and the capacitor C2, the drain electrode and the grid electrode of the NMOS tube N6 are in short circuit and connected with the other end of the switch S4, and the source electrode of the NMOS tube N6 is grounded through the resistor R4.

In the RT mode, the switch S4 is in a closed state. When the switch S4 is controlled by the control signal RT _ MODE, the control signal RT _ MODE is "1" and the control signal PLL _ MODE is "0", the switch S4 is closed, so that the frequency maintenance circuit 340 enters the RT MODE. At this time, the control voltage VCONT _ PRE output from the loop filter 200 is kept equal to the drain voltage of the PMOS transistor P7. When the first oscillator 300 is switched from the RT mode to the PLL mode in the second operating state, the control voltage VCONT _ PRE does not need to be gradually increased from "0", thereby speeding up the establishment of the phase-locked loop and shortening the establishment time required for synchronizing the frequency of the CLOCK signal CLOCK output by the first oscillator 300 to the frequency of the external CLOCK signal CLK _ SYNC when the first oscillator 300 is switched between the two modes.

As shown in fig. 4, the first ramp voltage generating circuit 350 is used for outputting a corresponding ramp voltage V according to the current outputted by the current mirror circuit_RAMP1。

Specifically, the first ramp voltage generating circuit 350 includes an NMOS transistor N7 and a capacitor C_OSC1. Capacitor C_OSC1One end of the first comparator is connected with the drain electrode of the NMOS transistor N7 and the positive electrode input end of the first comparator, the other end of the first comparator is connected with the source electrode of the NMOS transistor N7 and is grounded, and the grid electrode of the NMOS transistor N7 is connected with the output end of the first logic circuit.

As shown in FIG. 4, a first comparator is used to ramp the voltage V_RAMP1And a reference voltage V_{REF_OSC}After the comparison, the CLOCK signal CLOCK is output through the first logic circuit and the BUFFER BUFFER1, the output end of the BUFFER BUFFER1 is connected with the input end of the I0 of the second selector, the output end of the first comparator is connected with the input end of the first logic circuit, and the output end of the first logic circuit is connected with the input end of the BUFFER BUFFER 1.

As shown in fig. 4, the first selector has a control terminal receiving the control signal SEL _ PLL, the control terminal of the first selector is connected to an output terminal of an AND circuit AND2, an a1 input terminal of the AND circuit AND2 is connected to an output terminal of an inverter INV1, an a2 input terminal of the AND circuit AND2 is connected to an input terminal of the first logic circuit AND simultaneously transmits the control signal PLL _ MODE, AND an input terminal of the inverter INV1 is connected to an input terminal of the first logic circuit AND simultaneously transmits the input signal FORCE _ FMIN. The first logic circuit is also connected to the input signal CONT, which is used to indicate whether the system has a down conversion, and in other embodiments, the system down conversion may not be considered, that is, the first logic circuit may not be connected to the input signal CONT. The first logic circuit also outputs a control signal LOCK _ OSC 1. The control signal LOCK _ OSC1 is also used as an input signal for the enable circuit and the inverter INV 2.

As shown in fig. 5, the second oscillator 400 includes an NMOS transistor N3, a resistor R2, a PMOS transistor P3, a PMOS transistor P4, an NMOS transistor N4, and a capacitor C_OSC2A second comparator, a second logic circuit and a BUFFER 2. The PMOS transistor P3 and the PMOS transistor P4 form a second current mirror circuit. NMOS transistor N4 and capacitor C_OSC2Constitute a second ramp voltage generating circuit.

The grid electrode of the NMOS transistor N3 is connected with the connecting end connected with the resistor R1 and the capacitor C2, and the source electrode of the NMOS transistor N3 passes through the electric connection endThe resistor R2 is grounded, the source electrode of the NMOS tube N3 is connected with the I1 input end of the first selector, the drain electrode and the grid electrode of the PMOS tube P3 are in short circuit and connected with the drain electrode of the NMOS tube N3 and the grid electrode of the PMOS tube P4, the source electrode of the PMOS tube P3 is connected with a power supply VDD, the source electrode of the PMOS tube P4 is connected with the power supply VDD, the drain electrode of the PMOS tube P4 is connected with the positive input end of the second comparator, and the capacitor C is connected with the positive input end of the second comparator_OSC2One end of the second comparator is connected with the drain electrode of the NMOS tube N4 and the anode input end of the second comparator, and the capacitor C_OSC2The other end of the first comparator is connected with the source of an NMOS transistor N4 and grounded, the gate of the NMOS transistor N4 is connected with the output end of a second logic circuit, the negative electrode input end of the second comparator is connected with a reference voltage VREF _ OSC, the output end of the second comparator is connected with the input end of a BUFFER BUFFER2 through the second logic circuit so as to output a clock signal CLK _ OSC2, and the output end of the BUFFER BUFFER2 is connected with the I1 input end of the second selector. The second comparator is controlled by an enable signal EN2, and works normally when the enable signal EN2 is "1", and does not work when the enable signal EN2 is "0".

As shown in fig. 2, the control terminal of the second selector is connected to the output terminal of the inverter INV2, and the input terminal of the inverter INV2 is connected to the input terminal of the LOCK _ OSC1 of the enable circuit and receives the control signal LOCK _ OSC 1.

In this embodiment, the first selector connects the signal PG at the I0 input terminal to the output terminal by default, and the signal PGATE output by the first selector is used as the gate input signal of the PMOS transistor P8. Therefore, if there is no system down-conversion, the frequency of the CLOCK signal CLOCK output by the first oscillator 300 is set by the resistance of the resistor RSET in the RT mode or the lowest frequency corresponding to the input signal FORCE _ FMIN being "1". When the input signal FORCE _ FMIN is "0" and the control signal PLL _ MODE is "1", the control signal SEL _ PLL is set to "1", and the first selector connects the control voltage VCONT at the input terminal I1 to the output terminal, and outputs the signal PGATE as the gate input signal of the PMOS transistor P8. Therefore, if there is no system down-conversion, the frequency of the CLOCK signal CLOCK output by the first oscillator 300 is synchronized to the frequency of the external CLOCK signal CLK _ SYNC by the pll adjustment.

The second selector by default connects the signal at the input terminal I0 (i.e. the CLOCK signal CLOCK output by the first oscillator 300) to the output terminal, which outputs the signal CLK _ IN as the input CLOCK signal to the D-flip-flop D2 IN the phase detector 100. At this time, the first phase locked loop synchronizes the frequency of the CLOCK signal CLOCK output from the first oscillator 300 to the frequency of the external CLOCK signal CLK _ SYNC. When the LOCK _ OSC1 signal is "0", the second selector connects the signal at the input terminal of I1 (i.e., the output clock CLK _ OSC2 of the second oscillator 400) to the output terminal, and outputs the signal CLK _ IN as the input clock signal of the D-flip-flop D2 IN the phase detector 100. At this time, the second phase-locked loop synchronizes the frequency of the clock signal CLK _ OSC2 output from the second oscillator 400 to the frequency of the external clock signal CLK _ SYNC.

When the oscillator is operating in PLL mode, if some special condition is encountered, such as the switching power supply just powering up and operating at the lowest frequency, i.e., the FORCE _ FMIN signal is "1", the LOCK _ OSC1 signal is set to "0", and the enable signal EN2 is set to "1"; or when the system is down-clocked after the system is started, the control signal LOCK _ OSC1 is set to "0" and the enable signal EN2 is set to "1" after the input signal CONT passes through the first logic circuit. At this time, the frequency of the CLOCK signal CLOCK outputted from the first oscillator 300 is equal to the lowest frequency or equal to the system down-conversion frequency, and the frequency of the CLOCK signal CLK _ OSC2 outputted from the second oscillator 400 is fed back to the input CK terminal of the D-flip-flop D2 in the phase detector 100, so that the second phase-locked loop synchronizes the frequency of the CLOCK signal CLK _ OSC2 outputted from the second oscillator 400 to the frequency of the external CLOCK signal CLK _ SYNC, so that the voltage value of the control voltage VCONT is maintained at the voltage value of the control voltage VCONT determined by the frequency of the external CLOCK signal CLK _ SYNC. Thus, when the system exits the special conditions, that is, when the control signal LOCK _ OSC1 is set to "1" and the enable signal EN2 is set to "0", when the CLOCK signal CLOCK frequency output by the first oscillator 300 is fed back to the input CK terminal of the D2 in the phase detector 100, since the frequency corresponding to the control voltage VCONT is always maintained, the first phase-locked loop will synchronize the CLOCK signal CLOCK frequency output by the first oscillator 300 to the frequency of the external CLOCK signal CLK _ SYNC, thereby speeding up the establishment of the phase-locked loop.

When the first oscillator 300 operates in the RT mode, the voltage value of the control voltage VCONT _ PRE is maintained at the corresponding frequency by the frequency maintenance circuit 340, which is to say, the voltage value of the control voltage VCONT at the source of the NMOS transistor is maintained at the corresponding frequency. Thus, when the first oscillator 300 is switched from the RT mode to the PLL mode, the VCONT voltage does not need to be gradually increased from "0", which speeds up the establishment of the phase locked loop and shortens the time required for the frequency of the CLOCK signal CLOCK to be synchronized to the frequency of the external CLOCK signal CLK _ SYNC when the first oscillator 300 is switched between the two modes.

When the input signal FORCE _ FMIN is "1", the enable signal EN1 is set to "0", and the SEL _ PLL signal is set to "0", the minimum frequency circuit 330 adjusts so that the first oscillator 300 operates at the minimum frequency, that is, the frequency of the CLOCK signal CLOCK output by the first oscillator 300 is the minimum frequency. The lowest frequency is the lowest frequency supported by the first oscillator 300.

A switching frequency control method according to this embodiment includes:

judging a mode;

if the mode is the RT mode, the first oscillator 300 can output CLOCK signals CLOCK with different frequencies in different working states;

when the first oscillator 300 operates in the second operating state and switches from the RT mode to the PLL mode, the first oscillator 300 can output the CLOCK signal CLOCK synchronized to the external CLOCK signal CLK _ SYNC.

If it is the PLL mode, when the first oscillator 300 operates in the first operating state, the first oscillator 300 outputs the CLOCK signal CLOCK with the corresponding frequency, while the second oscillator 400 outputs the CLOCK signal CLK _ OSC2 capable of synchronizing to the external CLOCK signal CLK _ SYNC, and the second oscillator 400 provides a control voltage VCONT with the frequency corresponding to the external CLOCK signal CLK _ SYNC;

when the first oscillator 300 transitions from the first operating state to the second operating state, the first oscillator outputs the CLOCK signal CLOCK capable of skipping the abnormal state synchronization to the external CLOCK signal CLK _ SYNC by receiving the control voltage VCONT.

As shown in figure 6 of the drawings,the input signal EN _ CK is "1", and it can be seen that, when the system is just powered on, mode determination is first performed, and whether the system operates in the RT mode or the PLL mode is determined according to the state of the RT/SYNC input terminal. If it is determined that the RT MODE is operated, the control signal RT _ MODE is "1", and the control signal PLL _ MODE, the control signal SEL _ PLL, the enable signal EN2, and the control signal LOCK _ OSC1 are all "0". During the counting phase immediately after power-on, the input signal FORCE _ FMIN is "1", the enable signal EN1 is set to "0", and the frequency of the CLOCK signal CLOCK is equal to the lowest frequency. After the counting is finished, the input signal FORCE _ FMIN is changed to '0', the system is started, the enable signal EN1 is set to '1', and the frequency of the CLOCK signal CLOCK is set by the resistor R_SETThe value of (c) is determined. After startup, the system will continuously determine whether there is a downconversion. If yes, the frequency of the CLOCK signal CLOCK is equal to the frequency of the system frequency reduction; if not, the frequency of CLOCK signal CLOCK is controlled by resistor R_SETThe value of (c) is determined.

If the PLL MODE is determined to be operating in the PLL MODE, the control signal PLL _ MODE is "1", and both the control signal RT _ MODE and the enable signal EN1 are "0". Similarly, during the counting phase immediately after power-on, the input signal FORCE _ FMIN is "1", the control signal SEL _ PLL is set to "0", the enable signal EN2 is set to "1", and the control signal LOCK _ OSC1 is set to "0", in which case the frequency of the CLOCK signal CLOCK is equal to the lowest frequency and the frequency of the CLOCK signal CLK _ OSC2 is synchronized to the frequency of the external CLOCK signal CLK _ SYNC. After the counting is finished, the input signal FORCE _ FMIN becomes "0". The system starts up with the control signal SEL _ PLL set to "1", the enable signal EN2 set to "0", and the control signal LOCK _ OSC1 set to "1", at which time the frequency of the CLOCK signal CLOCK is synchronized to the frequency of the external CLOCK signal CLK _ SYNC. After the system is started, the system can continuously judge whether the frequency is reduced. If yes, after the input signal CONT passes through the first logic circuit, the control signal LOCK _ OSC1 is set to "0", the enable signal EN2 is set to "1", the frequency of the CLOCK signal CLOCK is equal to the frequency of the system down-conversion, and the frequency of the CLOCK signal CLK _ OSC2 is synchronized to the frequency of the external CLOCK signal CLK _ SYNC; if not, after the input signal CONT passes through the first logic circuit, the control signal LOCK _ OSC1 is set to "1", the enable signal EN2 is set to "0", and the frequency of the CLOCK signal CLOCK is synchronized to the frequency of the external CLOCK signal CLK _ SYNC.

As shown in fig. 7, the input signal EN _ CK is "1" and the enable signal EN is also "1". It can be seen that if the system is powered up in the RT MODE, the control signal RT _ MODE is "1", the control signal PLL _ MODE is "0", the control signal SEL _ PLL is "0", the control signal LOCK _ OSC1 is "0", and the enable signal EN2 is "0". When the input signal FORCE _ FMIN is "1" immediately after power-up, the enable signal EN1 is "0", and the frequency of the CLOCK signal CLOCK is equal to the lowest frequency. The voltage value of the control voltage VCONT is established and maintained at the voltage value of the control voltage VCONT corresponding to the lowest frequency. Then, when the input signal FORCE _ FMIN is "0", the enable signal EN1 becomes "1", the frequency of the CLOCK signal CLOCK is set by the value of the resistor RSET, and the voltage value of the control voltage VCONT is established and maintained at the corresponding frequency.

If the system is powered up in PLL MODE, the control signal RT _ MODE is "0", the control signal PLL _ MODE is "1", and the enable signal EN1 is "0". When the input signal FORCE _ FMIN is "1" immediately after power-up, the control signal SEL _ PLL is "0", the control signal LOCK _ OSC1 is "0", the enable signal EN2 is "1", the frequency of the CLOCK signal CLOCK is equal to the lowest frequency, the frequency of the CLOCK signal CLOCK _ OSC2 is synchronized to the frequency of the external CLOCK signal CLK _ SYNC, and the voltage value of the control voltage VCONT is established and maintained at the voltage value of the control voltage VCONT corresponding to the frequency of the external CLOCK signal CLK _ SYNC. Then, when the input signal FORCE _ FMIN is "0", the control signal SEL _ PLL is "1", the control signal LOCK _ OSC1 is "1", the enable signal EN2 is "0", and the frequency of the CLOCK signal CLOCK is immediately synchronized to the frequency of the external CLOCK signal CLK _ SYNC since the voltage value of the control voltage VCONT is already established and maintained at the voltage value of the control voltage VCONT corresponding to the frequency of the external CLOCK signal CLK _ SYNC. It can be seen that when the first oscillator 300 operates in the PLL mode, even when the system operates at the lowest frequency just after power-up, i.e. the input signal FORCE _ FMIN is "1", and the frequency of the CLOCK signal CLOCK output by the first oscillator 300 is equal to the lowest frequency, because the control signal LOCK _ OSC1 is set to "0" and the enable signal EN2 is set to "1" at this time, the frequency of the CLOCK signal CLK _ OSC2 output by the second oscillator 400 is fed back to the input CK terminal of the D flip-flop D2 in the phase detector 100, and the second phase-locked loop synchronizes the frequency of the CLOCK signal CLK _ OSC2 output by the second oscillator 400 to the frequency of the external CLOCK signal CLK _ SYNC at this time, so that the voltage value of the control voltage VCONT is established and maintained at the voltage value of the control voltage nt determined by the frequency of the external CLOCK signal CLK _ SYNC. Thus, when the first oscillator 300 exits the lowest frequency output mode, the frequency of the CLOCK signal CLOCK output by the first oscillator 300 is immediately synchronized to the frequency of the external CLOCK signal CLK _ SYNC by the first phase-locked loop circuit, so as to accelerate the establishment of the phase-locked loop.

It should be noted that, without the CLOCK signal CLOCK _ OSC2 synchronized to the frequency of the external CLOCK signal CLK _ SYNC, it is impossible to control the frequency of the voltage VCONT to be maintained at a frequency corresponding to the frequency of the external CLOCK signal CLK _ SYNC, which corresponds to the reduction of the function of the second oscillator 400. Then, when the input signal FORCE _ FMIN changes from "1" to "0", there may be a case where the frequency of the CLOCK signal CLOCK is higher than the frequency of the external CLOCK signal CLK _ SYNC at the beginning and then gradually decreases and synchronizes to the frequency of the external CLOCK signal CLK _ SYNC. The reason for this is that, in the PLL mode, since the input signal FORCE _ FMIN is "1" at the beginning, the frequency of the CLOCK signal CLOCK output by the first oscillator 300 is equal to the minimum frequency. Since the frequency is now less than the frequency of the external clock signal CLK _ SYNC, the adjustment through the first phase-locked loop results in the value of the control voltage VCONT being continuously charged high when it is fed back to the input CK terminal of the D flip-flop D2 in the phase-locked loop 100. Thus, when exiting the lowest frequency output mode, since the voltage value of the control voltage VCONT is high, the first oscillator 300 operates in an abnormal state of high frequency determined by the voltage value of the control voltage VCONT, and then gradually decreases and synchronizes to the frequency of the external clock signal CLK _ SYNC by the first phase-locked loop adjustment. Therefore, the CLOCK signal CLOCK output by the first oscillator 300 after exiting the lowest frequency output mode can be quickly synchronized to the external CLOCK signal CLK _ SYNC by the control voltage VCONT capable of synchronizing to the frequency of the external CLOCK signal CLK _ SYNC, skipping the abnormal state. Of course, the exit from the system down-conversion output mode is also the same as the above principle.

As shown in fig. 8, the input signal EN _ CK is "1" and the enable signal EN is also "1". It can be seen that after system start-up, the input signal FORCE _ FMIN is "0". When the system operates in the RT MODE, the control signal RT _ MODE is "1", the control signal PLL _ MODE is "0", the enable signal EN1 is "1", and the control signal SEL _ PLL, the control signal LOCK _ OSC1, and the enable signal EN2 are all "0". If the system is not down-clocked, the frequency of the CLOCK signal CLOCK is controlled by the resistor R_SETValue determination, the voltage value of the control voltage VCONT is established and maintained at the corresponding frequency; if there is a down-conversion, the frequency of the CLOCK signal CLOCK is equal to the down-conversion frequency of the system, the voltage value of the control voltage VCONT is established and maintained at the corresponding down-conversion frequency, and after the system down-conversion output mode exits, the frequency of the CLOCK signal CLOCK is determined by the value of the resistor RSET.

When the system operates in the PLL MODE, the control signal PLL _ MODE is "1", the control signal RT _ MODE is "0", the enable signal EN1 is "0", and the control signal SEL _ PLL is "1". If the system is not down-clocked, the control signal LOCK _ OSC1 is "1", the enable signal EN2 is "0", and the frequency of the CLOCK signal CLOCK is synchronized to the frequency of the external CLOCK signal CLK _ SYNC; if there is a down-conversion, the control signal LOCK _ OSC1 is "0", the enable signal EN2 is "1", the frequency of the CLOCK signal CLK _ OSC2 is synchronized to the frequency of the external CLOCK signal, and the frequency of the CLOCK signal CLOCK is equal to the frequency of the down-conversion of the system. During the down-conversion period, the voltage value of the control voltage VCONT is always maintained at the voltage value of the control voltage VCONT corresponding to the frequency of the external CLOCK signal CLK _ SYNC, so that the frequency of the CLOCK signal CLOCK is immediately synchronized to the frequency of the external CLOCK signal CLK _ SYNC after the down-conversion output mode is exited.

It can be seen that, when the first oscillator 300 operates in the PLL mode, even if the system is down-clocked, since the control signal LOCK _ OSC1 is set to "0" and the enable signal EN2 is set to "1" after the input signal CONT passes through the first logic circuit, the clock signal CLK _ OSC2 output by the second oscillator 400 is fed back to the input CK terminal of the D flip-flop D2 in the phase detector 100. At this time, the second phase-locked loop synchronizes the frequency of the clock signal CLK _ OSC2 output from the second oscillator 400 to the frequency of the external clock signal CLK _ SYNC, so that the voltage value of the control voltage VCONT is maintained at the voltage value of the control voltage VCONT determined by the frequency of the external clock signal CLK _ SYNC. And the frequency of the CLOCK signal CLOCK output by the first oscillator 3001 is equal to the system down-conversion frequency. As shown in fig. 8, in the system down-conversion output mode, since the voltage value of the control voltage VCONT is always maintained at the voltage value of the control voltage VCONT corresponding to the frequency of the external CLOCK signal CLK _ SYNC, when the system exits the system down-conversion output mode, the frequency of the CLOCK signal CLOCK output by the first oscillator 300 is immediately synchronized to the frequency of the external CLOCK signal CLK _ SYNC through the first phase-locked loop, and the establishment of the phase-locked loop is accelerated.

As shown in fig. 8, when the first oscillator 300 operates in the RT mode, the voltage value of the control voltage VCONT is established and maintained at the corresponding frequency. Therefore, when the first oscillator 300 is switched from the RT mode to the PLL mode, the control voltage VCONT does not need to be gradually increased from "0", and the frequency of the CLOCK signal CLOCK output by the first oscillator 300 is immediately synchronized to the frequency of the external CLOCK signal CLK _ SYNC, thereby speeding up the establishment of the phase locked loop and shortening the establishment time when the frequency of the CLOCK signal CLOCK output by the first oscillator 300 is synchronized to the frequency of the external CLOCK signal CLK _ SYNC when switching between the two modes.

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the utility model to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the utility model and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the utility model and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the utility model be defined by the claims and their equivalents.

Claims

1. A switching frequency control system, comprising:

a first phase-locked loop including a phase discriminator, a loop filter, and a first oscillator;

a second oscillator capable of forming a second phase-locked loop by switching with the first oscillator;

the first oscillator is capable of outputting a CLOCK signal CLOCK of a corresponding frequency in the PLL mode and in the first operating state, while the second oscillator is capable of outputting a CLOCK signal CLK _ OSC2 synchronized to the external CLOCK signal CLK _ SYNC, and the second oscillator provides a control voltage VCONT corresponding to the frequency of the external CLOCK signal CLK _ SYNC;

2. The switching frequency control system according to claim 1, wherein the first oscillator is capable of outputting a CLOCK signal CLOCK of different frequency in the RT mode and in different operation states; the first oscillator is switched from the RT mode to the PLL mode in the second operating state and is capable of outputting a CLOCK signal CLOCK synchronized to the external CLOCK signal CLK _ SYNC.

3. The switching frequency control system according to claim 1, further comprising a first selector and a second selector, wherein an I0 input and an output of the first selector are connected to the first oscillator, an I1 input of the first selector is connected to the second oscillator, an I0 input of the second selector is connected to an output of the first oscillator, an I1 input of the second selector is connected to an output of the second oscillator, an output of the second selector is connected to an input of the phase detector, and switching between the first oscillator and the second oscillator is enabled by the first selector and the second selector.

4. The switching frequency control system according to claim 3, wherein the first oscillator includes a mode conversion circuit, a first current mirror circuit, a lowest frequency circuit, a frequency maintenance circuit, a first ramp voltage generation circuit, a first comparator, a first logic circuit, and a BUFFER1, the mode conversion circuit, the first ramp voltage generation circuit, and the first comparator are all connected to the first current mirror circuit, and the first current mirror circuit, the lowest frequency circuit, and the frequency maintenance circuit are all connected to the first selector;

the mode switching circuit is used for switching off or switching to an RT mode and outputting corresponding mirror current through the first current mirror circuit; the lowest frequency circuit is used for enabling the first oscillator to output the lowest frequency; the frequency maintaining circuit is used for maintaining the frequency corresponding to the control voltage VCONT in the RT mode; the first ramp voltage generating circuit is used for outputting a corresponding ramp voltage V according to the mirror current output by the first current mirror circuit_RAMP1(ii) a The first comparator is used for converting a ramp voltage V_RAMP1And a reference voltage V_{REF_OSC}The comparison is performed and then the CLOCK signal CLOCK is outputted through the first logic circuit and the BUFFER 1.

5. The switching frequency control system of claim 4, wherein the mode conversion circuit comprises an operational amplifier, a switch S3, a resistor R_SETAnd an NMOS transistor N5;

wherein the positive input end of the operational amplifier is connected with a reference voltage V_REFThe negative electrode input end of the operational amplifier is connected with the resistor R through the switch S3_SETOne end of said resistor R_SETThe other end of the operational amplifier is grounded, the negative input end of the operational amplifier is simultaneously connected with the source electrode of the NMOS tube N5, the grid electrode of the NMOS tube N5 is connected with the output end of the operational amplifier, and the drain electrode of the NMOS tube N5 is connected with the first current mirror circuitIn the RT mode, the switch S3 is in a closed state.

6. The switching frequency control system according to claim 4, wherein the first current mirror circuit comprises a PMOS transistor P5 and a PMOS transistor P8, the source of the PMOS transistor P5 is connected to the VDD, the drain and the gate of the PMOS transistor P5 are shorted and connected to the I0 input terminal of the first selector, the gate of the PMOS transistor P8 is connected to the output terminal of the first selector, the source of the PMOS transistor P8 is connected to the VDD, and the drain of the PMOS transistor P8 is connected to the positive input terminal of the first comparator.

7. The switching frequency control system of claim 4, wherein the lowest frequency circuit comprises a PMOS transistor P9, a resistor R3, a capacitor C3, a PMOS transistor P6, and a bias current source IBIAS2_ FMIN;

8. The switching frequency control system according to claim 4, wherein said frequency maintaining circuit comprises a PMOS transistor P7, a switch S4, an NMOS transistor N6, and a resistor R4;

9. As claimed inThe switching frequency control system of claim 4, wherein the first ramp voltage generating circuit comprises an NMOS transistor N7 and a capacitor C_OSC1Said capacitor C_OSC1One end of the first comparator is connected with the drain electrode of the NMOS tube N7 and the positive electrode input end of the first comparator, the other end of the first comparator is connected with the source electrode of the NMOS tube N7 and is grounded, and the grid electrode of the NMOS tube N7 is connected with the output end of the first logic circuit.

10. The switching frequency control system of claim 3, wherein the second oscillator comprises an NMOS transistor N3, a resistor R2, a PMOS transistor P3, a PMOS transistor P4, an NMOS transistor N4, a capacitor C_OSC2A second comparator, a second logic circuit and a BUFFER 2;

wherein, the gate of NMOS pipe N3 is connected the output of loop filter, the source of NMOS pipe N3 is passed through resistance R2 ground connection, the source of NMOS pipe N3 is connected the I1 input of first selector, the drain and the gate short circuit of PMOS pipe P3 and connect the drain of NMOS pipe N3 and the gate of PMOS pipe P4, the source of PMOS pipe P3 is connected power VDD, the source of PMOS pipe P4 is connected power VDD, the drain of PMOS pipe P4 is connected the positive input of second comparator, electric capacity C is connected_OSC2One end of the second comparator is connected with the drain electrode of the NMOS tube N4 and the positive input end of the second comparator, and the capacitor C_OSC2The other end of the first comparator is connected to the source of the NMOS transistor N4 and grounded, the gate of the NMOS transistor N4 is connected to the output end of the second logic circuit, the negative input end of the second comparator is connected to a reference voltage VREF _ OSC, the output end of the second comparator is connected to the input end of the BUFFER2 through the second logic circuit, and the output end of the BUFFER2 is connected to the input end of the I1 of the second selector.