CN216216881U - Optical serial port receiving and transmitting circuit - Google Patents
Optical serial port receiving and transmitting circuit Download PDFInfo
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- CN216216881U CN216216881U CN202122822599.5U CN202122822599U CN216216881U CN 216216881 U CN216216881 U CN 216216881U CN 202122822599 U CN202122822599 U CN 202122822599U CN 216216881 U CN216216881 U CN 216216881U
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Abstract
The utility model discloses an optical serial port receiving and sending circuit, which comprises a receiving unit and a sending unit, wherein the receiving unit and the sending unit are both connected with a signal acquisition host, the signal acquisition host is an FPGA (field programmable gate array), the receiving unit comprises a resistor R200, a NAND gate U41A, a NOT gate U41B, a NOT gate U41C, a NOT gate U41D, a resistor R269, a capacitor C279, a resistor R271 and a photoelectric conversion module J12, a first pin of the NAND gate U41A is connected with a UART (universal asynchronous receiver) receiving port of the FPGA, a second pin of the NAND gate U41A, one end of the resistor R200, a thirteenth pin of the NAND gate U41D, a fourth pin of the NAND gate U41B and a ninth pin of the NAND gate U41C are connected; the utility model has the advantages that: in the area that the Ethernet cable can not cover, signal transmission can be carried out through photoelectric conversion, and the problem of signal transmission is effectively solved.
Description
Technical Field
The utility model relates to the field of signal transmission, in particular to an optical serial port receiving and transmitting circuit.
Background
The optical serial port receiving and transmitting circuit is an ethernet transmission medium conversion unit which exchanges short-distance twisted pair electrical signals and long-distance optical signals, and is called as a Fiber Converter (Fiber Converter). The product is generally applied to the actual network environment that Ethernet can not be covered by network cables in many places and optical fibers are used for prolonging the transmission distance, and is generally positioned in the access layer application of a broadband metropolitan area network; such as: monitoring high-definition video image transmission of a safety project; it also plays a significant role in facilitating the last mile of line connection of optical fibers to metropolitan and more outer networks. The optical serial port receiving and transmitting circuit has the functions of converting an electric signal to be transmitted into an optical signal and transmitting the optical signal, and meanwhile, converting the received optical signal into an electric signal and inputting the electric signal to a receiving end of people. In the process of collecting signals of the tripping and closing loop, the area which cannot be covered by the Ethernet cable adopts the optical serial port receiving and sending circuit to receive and send the signals, so that the problem of signal transmission can be effectively solved.
SUMMERY OF THE UTILITY MODEL
The technical problem to be solved by the utility model is to provide an optical serial port receiving and sending circuit, which is used for receiving and sending signals in an area which cannot be covered by an Ethernet cable, and effectively solving the problem of signal transmission.
The utility model solves the technical problems through the following technical means: an optical serial port receiving and transmitting circuit comprises a receiving unit and a transmitting unit, wherein the receiving unit and the transmitting unit are both connected with a signal acquisition host, the signal acquisition host is an FPGA, the receiving unit comprises a resistor R200, a NAND gate U41A, a NOT gate U41B, a NOT gate U41C, a NOT gate U41D, a resistor R269, a capacitor C279, a resistor R271 and a photoelectric conversion module J12, a first pin of the NAND gate U41A is connected with a UART receiving port of the FPGA, a second pin of the NAND gate U41A, one end of the resistor R200, a thirteenth pin of the NAND gate U41D, a fourth pin of the NAND gate U41B and a ninth pin of the NAND gate U41C are connected, the other end of the resistor R200 and a fourteenth pin of the NAND gate U41A are connected with a power supply V5P _ VDD, a seventh pin of the NAND gate U41A is grounded, a third pin of the NAND gate U41A, a twelfth pin of the NAND gate U41D, a fifth pin of the NAND gate U41B and a tenth pin of the NAND gate U41C are connected, an eleventh pin of the nand gate U41D, a sixth pin of the nand gate U41B, an eighth pin of the not gate U41C, one end of the resistor R269, and one end of the capacitor C279 are connected, the other end of the resistor R269 and the other end of the capacitor C279 are both connected to one end of the resistor R271, and the other end of the resistor R271 is connected to a third pin of the photoelectric conversion module J12.
The utility model provides an optical serial port receiving and sending circuit which comprises a receiving unit and a sending unit, wherein the receiving unit and the sending unit are both connected with a signal acquisition host, a photoelectric conversion module J12 is arranged in the receiving unit, and signal transmission can be carried out through photoelectric conversion in an area which cannot be covered by an Ethernet cable, so that the problem of signal transmission is effectively solved.
Further, the receiving unit further comprises a first filtering subunit, the first filtering subunit comprises a resistor R215, a resistor R208 and a capacitor C103, one end of the resistor R215, one end of the resistor R208 and one end of the capacitor C103 are connected and connected to the UART receiving port of the FPGA, the other end of the resistor R215 is connected to the second pin of the photoelectric conversion module J12, the other end of the resistor R208 is connected to the sixth pin of the photoelectric conversion module J12, and the other end of the capacitor C103 is grounded.
Furthermore, the sending unit comprises a resistor R199, a NAND gate U40A, a NAND gate U40B, a NAND gate U40C, a NAND gate U40D, a resistor R270, a capacitor C280, a resistor R272 and a chip J11, wherein a first pin of the NAND gate U40A is connected with a UART sending port of the FPGA, a second pin of the NAND gate U40A, one end of the resistor R199, a thirteenth pin of the NAND gate U40D, a fourth pin of the NAND gate U40B and a ninth pin of the NAND gate U40C are connected, the other end of the resistor R199 and a fourteenth pin of the NAND gate U40A are connected with a power supply V5 _ VDD P, a seventh pin of the NAND gate U40A is grounded, a third pin of the NAND gate U40A, a twelfth pin of the NAND gate U40D, a fifth pin of the NAND gate U40B and a tenth pin of the NAND gate U40, an eleventh pin of the NAND gate U D, an eleventh pin of the NAND gate U27, a sixth pin of the NAND gate U40, a resistor R270 and an eighth pin of the NAND gate U29, the other end of the resistor R270 and the other end of the capacitor C280 are both connected with one end of a resistor R272, and the other end of the resistor R272 is connected with a third pin of the chip J11;
furthermore, the sending unit further includes a second filtering subunit, where the second filtering subunit includes a resistor R211, a resistor R206, and a capacitor C102, one end of the resistor R211, one end of the resistor R206, and one end of the capacitor C102 are connected to the UART sending port of the FPGA, the other end of the resistor R211 is connected to the second pin of the chip J11, the other end of the resistor R206 is connected to the sixth pin of the chip J11, and the other end of the capacitor C102 is grounded.
Furthermore, the model of the photoelectric conversion module J12 is AFBR-2418 TZ.
Furthermore, the model of the chip J11 is HFBR-1414 TZ.
The utility model has the advantages that: the utility model provides an optical serial port receiving and sending circuit which comprises a receiving unit and a sending unit, wherein the receiving unit and the sending unit are both connected with a signal acquisition host, a photoelectric conversion module J12 is arranged in the receiving unit, and signal transmission can be carried out through photoelectric conversion in an area which cannot be covered by an Ethernet cable, so that the problem of signal transmission is effectively solved.
Drawings
Fig. 1 is a schematic diagram of a first part of a receiving unit of an optical serial port receiving and transmitting circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a second part of a receiving unit of an optical serial port receiving and transmitting circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a third part of a receiving unit of an optical serial port receiving and transmitting circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a first part of a transmitting unit of an optical serial port receiving and transmitting circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a second part of a transmitting unit of an optical serial port receiving and transmitting circuit according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a third part of a transmitting unit of an optical serial port receiving and transmitting circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1 to 3, an optical serial port receiving and transmitting circuit includes a receiving unit and a transmitting unit, both the receiving unit and the transmitting unit are connected to a signal acquisition host, the signal acquisition host is an FPGA, the optical serial port receiving and transmitting circuit includes a receiving unit and a transmitting unit, the receiving unit includes a resistor R200, a nand gate U41A, a not gate U41B, a not gate U41C, a not gate U41D, a resistor R269, a capacitor C279, a resistor R271 and a photoelectric conversion module J12, the photoelectric conversion module J12 is AFBR-2418TZ, a first pin of the nand gate U41A is connected to a UART receiving port of the FPGA, a second pin of the nand gate U41A, one end of the resistor R200, a thirteenth pin of the nand gate U41D, a fourth pin of the nand gate U41B and a ninth pin of the nand gate U41C are connected, the other end of the resistor R200 and a fourteenth pin of the nand gate U41A are connected to a power supply V5 VDD 5P, the seventh pin of the nand gate U41A is grounded, the third pin of the nand gate U41A, the twelfth pin of the nand gate U41D, the fifth pin of the nand gate U41B and the tenth pin of the nand gate U41C are connected, the eleventh pin of the nand gate U41D, the sixth pin of the nand gate U41B, the eighth pin of the not gate U41C, one end of the resistor R269 and one end of the capacitor C279 are connected, the other end of the resistor R269 and the other end of the capacitor C279 are both connected with one end of the resistor R271, and the other end of the resistor R271 is connected with the third pin of the photoelectric conversion module J12.
The receiving unit further comprises a first filtering subunit, the first filtering subunit comprises a resistor R215, a resistor R208 and a capacitor C103, one end of the resistor R215, one end of the resistor R208 and one end of the capacitor C103 are connected and connected with a UART receiving port of the FPGA, the other end of the resistor R215 is connected with a second pin of the photoelectric conversion module J12, the other end of the resistor R208 is connected with a sixth pin of the photoelectric conversion module J12, and the other end of the capacitor C103 is grounded. The circuit shown in fig. 1 in the receiving unit is of a compatible design, and the circuit shown in fig. 2 and 3 is used in practical applications.
As shown in fig. 4 to 6, the sending unit includes a resistor R199, a nand gate U40A, a nand gate U40B, a nand gate U40C, a nand gate U40D, a resistor R270, a capacitor C280, a resistor R272, and a chip J11, wherein the model of the chip J11 is HFBR-1414 TZ. The first pin of the nand gate U40A is connected to the UART transmit port of the FPGA, the second pin of the NAND-gate U40A, one end of the resistor R199, the thirteenth pin of the NAND-gate U40D, the fourth pin of the NAND-gate U40B and the ninth pin of the NAND-gate U40C are connected, the other end of the resistor R199 and the fourteenth pin of the NAND-gate U40A are both connected with the power supply V5P _ VDD, the seventh pin of the NAND-gate U40A is grounded, the third pin of the NAND-gate U40A is connected with the twelfth pin of the NAND-gate U40D, the fifth pin of the NAND-gate U40B and the tenth pin of the NAND-gate U40C, the eleventh pin of the nand gate U40D, the sixth pin of the nand gate U40B, the eighth pin of the nand gate U40C, one end of the resistor R270, and one end of the capacitor C280 are connected, the other end of the resistor R270 and the other end of the capacitor C280 are both connected to one end of the resistor R272, and the other end of the resistor R272 is connected to the third pin of the chip J11. For the transmitting unit, the circuit shown in fig. 5 is of a compatible design, and the circuits shown in fig. 4 and 6 are used in practical applications.
The transmitting unit further comprises a second filtering subunit, the second filtering subunit comprises a resistor R211, a resistor R206 and a capacitor C102, one end of the resistor R211, one end of the resistor R206 and one end of the capacitor C102 are connected and connected with a UART transmitting port of the FPGA in parallel, the other end of the resistor R211 is connected with a second pin of the chip J11, the other end of the resistor R206 is connected with a sixth pin of the chip J11, and the other end of the capacitor C102 is grounded.
Through the technical scheme, the utility model provides an optical serial port receiving and sending circuit which comprises a receiving unit and a sending unit, wherein the receiving unit and the sending unit are both connected with a signal acquisition host, a photoelectric conversion module J12 is arranged in the receiving unit, and signal transmission can be carried out through photoelectric conversion in an area which cannot be covered by an Ethernet cable, so that the problem of signal transmission is effectively solved.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (6)
1. An optical serial port receiving and transmitting circuit is characterized by comprising a receiving unit and a transmitting unit, wherein the receiving unit and the transmitting unit are both connected with a signal acquisition host, the signal acquisition host is an FPGA, the receiving unit comprises a resistor R200, a NAND gate U41A, a NOT gate U41B, a NOT gate U41C, a NOT gate U41D, a resistor R269, a capacitor C279, a resistor R271 and a photoelectric conversion module J12, a first pin of the NAND gate U41A is connected with a UART receiving port of the FPGA, a second pin of the NAND gate U41A, one end of the resistor R200, a thirteenth pin of the NAND gate U41D, a fourth pin of the NAND gate U41B and a ninth pin of the NAND gate U41C are connected, the other end of the resistor R200 and a fourteenth pin of the NAND gate U41A are connected with a power supply V5P _ VDD, a seventh pin of the NAND gate U41A is grounded, a third pin of the NAND gate U41A, a twelfth pin of the NAND gate U41D and a fifteenth pin 41C of the NAND gate U41B are connected with a VDD 41, an eleventh pin of the nand gate U41D, a sixth pin of the nand gate U41B, an eighth pin of the not gate U41C, one end of the resistor R269, and one end of the capacitor C279 are connected, the other end of the resistor R269 and the other end of the capacitor C279 are both connected to one end of the resistor R271, and the other end of the resistor R271 is connected to a third pin of the photoelectric conversion module J12.
2. The optical serial port receiving and transmitting circuit according to claim 1, wherein the receiving unit further includes a first filtering subunit, the first filtering subunit includes a resistor R215, a resistor R208, and a capacitor C103, one end of the resistor R215, one end of the resistor R208, and one end of the capacitor C103 are connected to and connected to the UART receiving port of the FPGA, the other end of the resistor R215 is connected to the second pin of the photoelectric conversion module J12, the other end of the resistor R208 is connected to the sixth pin of the photoelectric conversion module J12, and the other end of the capacitor C103 is grounded.
3. The optical serial port receiving and transmitting circuit according to claim 2, wherein the transmitting unit comprises a resistor R199, a nand gate U40A, a nand gate U40B, a nand gate U40C, a nand gate U40D, a resistor R270, a capacitor C280, a resistor R272 and a chip J11, the first pin of the nand gate U40A is connected to the UART transmitting port of the FPGA, the second pin of the nand gate U40A, one end of the resistor R199, the thirteenth pin of the nand gate U40D, the fourth pin of the nand gate U40B and the ninth pin of the nand gate U40C are connected to the power supply V5P _ VDD, the seventh pin of the nand gate U40A is grounded, the third pin of the nand gate U40A, the twelfth pin of the nand gate U40D, the fifth pin of the nand gate U40B, the tenth pin of the nand gate U C, the eleventh pin of the nand gate U40 and the eleventh pin of the nand gate U40D are connected to the sixth pin of the nand gate U40 and the eleventh pin of the nand gate U40 and the nand gate U40 638, An eighth pin of the nand gate U40C, one end of the resistor R270, and one end of the capacitor C280 are connected, the other end of the resistor R270 and the other end of the capacitor C280 are both connected to one end of the resistor R272, and the other end of the resistor R272 is connected to the third pin of the chip J11.
4. The optical serial port receiving and transmitting circuit according to claim 3, wherein the transmitting unit further comprises a second filtering subunit, the second filtering subunit comprises a resistor R211, a resistor R206 and a capacitor C102, one end of the resistor R211, one end of the resistor R206 and one end of the capacitor C102 are connected to each other and connected to the UART transmitting port of the FPGA, the other end of the resistor R211 is connected to the second pin of the chip J11, the other end of the resistor R206 is connected to the sixth pin of the chip J11, and the other end of the capacitor C102 is grounded.
5. The optical serial port receiving and transmitting circuit as claimed in claim 4, wherein the model of the photoelectric conversion module J12 is AFBR-2418 TZ.
6. The optical serial port receiving and transmitting circuit as claimed in claim 4, wherein the model of the chip J11 is HFBR-1414 TZ.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122822599.5U CN216216881U (en) | 2021-11-17 | 2021-11-17 | Optical serial port receiving and transmitting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122822599.5U CN216216881U (en) | 2021-11-17 | 2021-11-17 | Optical serial port receiving and transmitting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216216881U true CN216216881U (en) | 2022-04-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122822599.5U Withdrawn - After Issue CN216216881U (en) | 2021-11-17 | 2021-11-17 | Optical serial port receiving and transmitting circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216216881U (en) |
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2021
- 2021-11-17 CN CN202122822599.5U patent/CN216216881U/en not_active Withdrawn - After Issue
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Granted publication date: 20220405 Effective date of abandoning: 20231225 |
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Granted publication date: 20220405 Effective date of abandoning: 20231225 |
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